CORE Generator & IP Modules -
Top Solutions

To access the complete database of Xilinx Solutions, please consult our Answers Search page.

General Setup GUI & Implementation Cores Exemplar Foundation

Foundation and FPGA Express Synopsys FPGA Compiler Mentor Synplicity Viewlogic

General

• Solution 3681 - V1.5.0, V1.4.0 COREGEN, LOGIBLOX: Differences between COREGen and LogiBLOX
• Solution 4041 - V1.5 COREGEN:  COREGEN does not allow you to select the netlist bus delimiter format if one of your output format selections is Verilog or VHDL instantiation template or behavioral model.

Setup

• Solution 4650 - V1.5, V1.4 COREGEN:  Cannot start up COREGEN from Windows Desktop or Start menu shortcuts--xspawn hangs
• Solution 4289 - V1.5 COREGEN:  How to get a copy of the CORE Generator v1.5.0 CD.
• Solution 3628 - V1.5, V1.4 COREGEN: Errors when loading spec sheets in Acrobat 2.1
• Solution 3094 - V1.5, V1.4 COREGEN: Warning: Your directory path should not contain any directory names longer than 8 characters.
• Solution 3325 - V1.5, V1.4 COREGEN: java.lang.OutOfMemoryError "Out of memory" errors on very large cores
• Solution 3785 - V1.5, V1.4 COREGEN: Blank DOS box appears when COREGen is invoked with Windows Display set to "True Color", entire program hangs; Windows NT.
• Solution 2118 - Java: This program has performed an illegal operation and will be shut down (display settings problem)

GUI & Implementation

• Solution 4290 - V1.5.0 COREGEN: Known Problems/Release Document 
• Solution 4026 - M1.4 MAP: ERROR:x4kma:387 - Unable to obey design constraints which require the following symbols to be combined into a single CLB.
• Solution 2193 - MAP Warning:baste:102 - Logic enclosed by Fmap symbol has too many inputs
• Solution 3673 - V1.5.0, V1.4 COREGEN: Solaris Stopwatch "busy" cursor or Windows hourglass cursor lingers (seems to hang) after an operation is completed.

Cores

• Solution 3675 - V1.5, V1.4 COREGEN: Which cores / modules are being shipped in the v1.4.0 and v1.5.0 releases, and which are free of charge?
• Solution 3498 - COREGEN: Does COREGen support floating point values in the .COE coefficient files?
• Solution 3791 - V1.5, V1.4 COREGEN: After FULL indicator goes high, FIFO output changes to the first value written before READ ENABLE goes active.
• Solution 4543 - V1.5, V1.4 COREGEN:  Only the 24 LSBs of a cascade mode SDA FIR output are defined in a Verilog behavioral simulation.
• Solution 4504 - COREGEN, LOGICORE, DSP:  LogiCORE DSP Brochure on WebLINX incorrectly indicates that Sine/Cosine/Arctan Look-up tables of any bit width and table depth are supported.
• Solution 3702 - V1.5, V1.4 COREGEN: Parameter File Information tables in the COREGen datasheets

Exemplar

• Solution 4512 - Tips on how to use blackbox EDIF and XNF netlists in HDL
• Solution 3144 - M1 NGDBUILD: ERROR:basnb:79 (pin mismatch) and ERROR:basnu:93 (unexpanded) errors on Exemplar designs with instantiated modules
• Solution 3947 - COREGEN v1.4:  Exemplar flow (with and without LogiBLOX) (basnb:79 - Pin mismatch, basnu:93 - Unexpanded block error...).

Foundation

• Solution 3754 - V1.5, V1.4 COREGEN:  Foundation must be installed for Foundation users.
• Solution 4208 - V1.5, V1.4 COREGEN, FOUNDATION: Symbol pin ordering of COREGEN-generated symbols may be inconsistent between the V1.5 and V1.4 releases.
• Solution 3884 - V1.5, V1.4 COREGEN: Versions of Foundation, Viewlogic, and Synopsys supported by COREGEN.
• Solution 4521 - V1.5 COREGEN, FOUNDATION:  "Unknown component: TBUF" warnings when loading  functional simulation netlist containing COREGEN SINE-COSINE LUTs, FIFOs, ROMs, or RAM modules into the F1.5 Foundation simulator.

Foundation Express & Synopsys FPGA Express

• Solution 3884 - V1.5, V1.4 COREGEN: Versions of Foundation, Viewlogic, and Synopsys supported by COREGEN.
• Solution 2738 - FPGA EXPRESS: How to integrate CoreGen module XNF files into Express Verilog or VHDL designs
• Solution 3863 - V1.5, V1.4 COREGEN, FOUNDATION EXPRESS:   How to generate Foundation functional simulation files for a Foundation Express VHDL design

Mentor

• Solution 3046 - Integrating EDIF netlists with Mentor schematics
• Solution 2899 - Integrating XNF netlists with Mentor schematics

Synopsys FPGA Compiler

• Solution 3884 - V1.5, V1.4 COREGEN: Versions of Foundation, Viewlogic, and Synopsys supported by COREGEN.

Synplicity

• Solution 4272 - SYNPLICITY:  Which bus delimiter to select when incorporating COREGen modules.
• Solution 4891 - V5.x SYNPLIFY, COREGEN, NGDBUILD: "ERROR:basnb:79 - Pin mismatch between block..."

Viewlogic

• Solution 3884 - V1.5, V1.4 COREGEN: Versions of Foundation, Viewlogic, and Synopsys supported by COREGEN.
• Solution 3754 - V1.5, V1.4 COREGEN: Xilinx M1.4 and Viewlogic must be installed first for Viewlogic users.
• Solution 3031 - V1.5, V1.4 COREGEN, Workview Office, M1: Module implementation has much higher CLB counts than specified in datasheet  
• Solution 4318 - V1.5 COREGEN:  Direct gate level schematic simulation of Virtex designs is not supported.