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Xilinx Answer #8312 : 2.1i JTAG Programmer - Virtex-E BSDL files are available.
Xilinx Answer #8296 : 2.1i Spartan-II Package Files - The TQ144 Package has been added for Spartan-II
Xilinx Answer #8295 : 2.1i SpartanXL Speed Files - MIN speed values are now available for SpartanXL
Xilinx Answer #8264 : 2.1i JTAG Programmer - 1802 PROM support added.
Xilinx Answer #8255 : 2.1i JTAG Programmer - Boundary-scan chain test failed at bit position '3'
Xilinx Answer #8224 : 2.1i JTAG Programmer - JTAG Programmer 2.1i does not support XC1800 SVF generation
Xilinx Answer #8118 : 2.1i Spartan-II Package Files - Some package files available with Service pack 3 are not correct.
Xilinx Answer #8117 : 2.1i Speed Files - There are several speed file changes available in Service Pack 3
Xilinx Answer #8102 : XC9500XL JTAG Programmer - ISP Enable instruction different in SVF file and 2.1i JTAG Programmer
Xilinx Answer #8077 : 2.1i JTAG Programmer - Why is RUNTEST 6067 TCK in the SVF file?
Xilinx Answer #8050 : 2.1i JTAG Programmer - Data string is larger than the specified svf bit length
Xilinx Answer #7879 : F2.1i XABEL: Internal Error 0001: assert event at line 359 in file "Z:\Lib\tsokit\TSOCELL\TSO_SIG.C"
Xilinx Answer #7799 : 2.1i: 9500/XL: Hitop: CPLD Fitter gives unexpected error - "zsplit.c:324"
Xilinx Answer #7786 : FPGA Express 3.3.1: Do not use this version of Express with Foundation 2.1i
Xilinx Answer #7773 : How do I convert a Foundation 1.4 project for use in 2.1i?
Xilinx Answer #7763 : PromGen 2.1i: Parallel cable doesn't complete configuration with Virtex chains.
Xilinx Answer #7736 : 2.1i Package Files - Incorrect location for Spartan40XL BG256 DONE pin specified in the pad report.
Xilinx Answer #7710 : 2.1i: Problems printing on Solaris
Xilinx Answer #7680 : Foundation 2.1i simulation: Error- Bus Conflicts during Foundations simulation, while simulating multiplexer with tri-stated buffers
Xilinx Answer #7495 : Foundation Simulator 2.1i: Netlist Fatal error. 9230: DUMMY cannot read pin #.
Xilinx Answer #7489 : 2.1i V150-FG456 - PAD report does not match datasheets
Xilinx Answer #7481 : 2.1i JTAG Programmer - File does not exist: <path>/filename.bsd
Xilinx Answer #7428 : 2.1i Userware: xm.laroux.as virus found within $XILINX/userware/virtex_arch.zip
Xilinx Answer #7352 : 2.1i Spartanxl speed files - Updated speed files are available for -5 preliminary speed grades.
Xilinx Answer #7330 : 2.1i XC4000XV Speed files - The 2.1i Service Pack Update contains Preliminary XC4000XV speed data.
Xilinx Answer #7326 : 2.1i SpartanXL - The CS280 packages are missing
Xilinx Answer #7317 : 2.1i SP1 - The 2.1i Service Pack 1 Update is due to become available on September 2.
Xilinx Answer #7274 : Foundation 2.1i: Multimedia QuickStart: Director Player 6.0: This program requires at least 3MB of free virtual memory to run
Xilinx Answer #7185 : 2.1i package files - The 40150xv BG432 package is incorrect
Xilinx Answer #7167 : FPGAEditor 2.1i - BlockRAM initialization values are not stored after saving changes
Xilinx Answer #7161 : Foundation 2.1i The PLC attribute for clbmap primitive not supported
Xilinx Answer #7043 : Foundation 2.1i: Extra speed grades for CPLD devices.
Xilinx Answer #6989 : Foundation 2.1i: Disable guide or floorplan does not work when selecting the option to copy using custom file.
Xilinx Answer #6695 : jtag programmer 2.1i: Does verify work for virtex using parallel III cable?
Xilinx Answer #6694 : XFLOW 2.1i: Command Line tool that allows you to do away with batch files and scripts in order to run the Xilinx tools !
Xilinx Answer #6604 : 2.1i: FGPA Editor: Script playback open dialog looks in last place script loaded instead of saved.
Xilinx Answer #6534 : UNISIMS: Alliance 2.1i (or later) changes from 1.5i (or earlier) for Verilog UNISIMS simulation
Xilinx Answer #6062 : 1.5i/2.1i: Virtex Back Annotation - Incorrect models for OBUF_GTL and OBUFT_GTL
Xilinx Answer #5939 : M1.5i/2.1i: When a group gets made and a TIG is placed THRU this group the TIG gets ignored
Xilinx Answer #5572 : 2.1i: 9500/XL: How to internally source BUFGTS, BUFGSR, BUFG
Xilinx Answer #5429 : M1.5i/2.1i: Prohibiting multi-purpose configuration pins.
Xilinx Answer #5140 : M1.5i/2.1i: Using the Tri-State IOB Flip-Flop in SpartanXL, XC4000XLA, and XC4000XV
Xilinx Answer #4771 : Changes in software security for F2.1i, F1.5, A1.5 (versus v1.4 and previous)
Xilinx Answer #4258 : SIMPRIMS: Alliance 2.1 changes from 1.5i (or older) for Verilog SIMPRIMS simulation
Xilinx Answer #3404 : 2.1i CPLD: How to use programmable grounds for unused pins in 9500/XL devices
Xilinx Answer #3374 : M1.5i/2.1i: WARNING:bastw:174- The current connection evalutation limit of 1000 caused ....
Xilinx Answer #3333 : M1.5i/2.1i TRACE: What to do about tilded values (~46ns) in the report
Xilinx Answer #2633 : 2.1i PROM FILES: M1 bit mirroring and XACT bit mirroring
Xilinx Answer #1825 : UNISIMS/SIMPRIMS 2.1i: CLKDLL doesn't lock after RST is de-asserted