LogiCORE PCI32 Spartan - Top Solutions LogiCORE PCI32 Interface Solution 3762: What is the functionality of the latency timer? Solution 4835: Does the PCI interface support multi-function capability? Solution 4855: How does the LogiCORE PCI32 interface handle wait states between data phases? Solution 5094: Information about Zero and One wait states Solution 5125: Can the I/O space in the PCI core be set to greater than 256 bytes? Solution 5128: When is the S_WRDN signal in the PCI core valid? Solution 5129: What is the advantage of using BAR_x_WR/RD signals to decode the target transactions as opposed to using the S_WRDN signal in combination with uniquely decoded address signals? Solution 5159: Is snooping supported by the LogiCORE interface? Solution 5160: How many Base Address Registers does the PCI interface support? Solution 5193: How does the PCI interface handle Master Aborts? Solution 5214: Does the LogiCORE interface support interrupts? Solution 5227: How does the LogiCORE interface handle target abort? Solution 5229: How do the REQ#/GNT#/RST# lines in the LogiCORE interface behave? LogiCORE PCI32 Devices Solution 5246: Supported Device/Package/Speed grades Solution 5253: Device resource utilization summary Solution 5254: Are the XC4000XLT and Spartan devices PCI compliant? LogiCORE PCI32 Design Flows Solution 3267: Verilog synthesis/simulation with LogiCORE PCI32 Spartan, FPGA Express 2.0.2 and M1.4.12 Solution 3268: VHDL synthesis/simulation with LogiCORE PCI32 Spartan, FPGA Express 2.0.2 and M1.4.12 Solution 3547: Synplify 5.0 and PCI LogiCORE 2.0 and M1.4: Verilog and VHDL synthesis flow Solution 4647: VHDL synthesis/simulation with PCI LogiCORE v2.0, Exemplar Leonardo v4.2.2 & M1.4.12 Solution 5134: Harmless warnings during Cadence Verilog-XL simulation Xilinx M1 Implementation Software Solution 5050: NGDBUILD errors out on a LOC constraint on INTA_0 net Solution 5055: Guide does not work if M/S_SRC_EN signals are unused Solution 5171: 0.7 multiplication factor in the UCF files Solution 5247: M1 Software & Synthesis tools support Miscellaneous Solution 5126: How much time would a FPGA on a PCI bus have for configuration? Solution 3543: Why can't an I/O Base Address Register be set to > 256 bytes for a x86 processor based system? Solution 3552: PCI Power Management: Description of function power states Solution 5261: Implementing CompactPCI HotSwap with Xilinx LogiCORE PCI solution LogiCORE PCI32 Documentation Solution 5127: Key to various states depicted in the waveforms in the LogiCORE PCI32 user guide