Welcome v7.0
Quick start
About Libero IDE v6.3
Getting and Using Help
Project Management
Design Constraints Guide
Design Creation / Verification
    SmartGen Core Builder
       What's new in SmartGen?
       SmartGen user interface
       Create a workspace
       Open a workspace
       Import a legacy core
       Remove or Delete a core
       Save the workspace
       SmartGen Preferences
       Workspace settings
       Generating reports in SmartGen
       Create Cores
       Fan-in control tool
       SmartGen Cores Reference Guide - Online
          Core Reference Guide information
          Arithmetic cores
          Comparators
          Binary to Gray / Gray to Binary Converters
          Counters
          Decoder
          IOs
          Logic
          Multiplexer
          Minicores
          PLLs
          Register (Storage elements)
          Memory Cores
             Memory Cores
             Synchronous/Asynchronous Dual Port RAM
             Register file for Antifuse
             Synchronous Dual Port FIFO w/o Flags
             Synchronous Dual Port FIFO w/ Flags
             FIFO Flag Controller (no RAM)
             Axcelerator memory cores
             ProASIC, ProASICPLUS, and ProASIC3/E memory cores
                Synchronous/Asynchronous Dual Port RAM for ProASIC and ProASICPLUS
                Register file for ProASIC and ProASICPLUS
                Synchronous/Asynchronous Dual Port FIFO for ProASIC and ProASICPLUS
                FIFO using distributed memory for ProASIC and ProASICPLUS
                Creating a RAM for ProASIC3/E
                Creating a FIFO for ProASIC3/E
    FlashROM
    Analog System Builder
    Flash Memory Block Builder
    HDL Entry
    Schematic Entry
    Synthesis
    Physical Synthesis
    Testbench Creation
    Simulation
Design Implementation
Device Programming
Saving and Exiting Libero
Contacting Actel