Cadence Interface - Top Solutions

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• Solution 4086- A1.5: Cadence PE 13.x Concept-HDL will not be supported until the next Xilinx software release after A1.5
• Solution 3830- A1.5: Cadence Concept 9604 and 97a: How to target a Spartan device
• Solution 3820- M1.4 Concept: How to place a TIG property on a net in your schematic property on a net in your schematic
• Solution 3693- Cadence Concept, M1: How to LOC global buffers in Concept schematic for the XC4000 family
• Solution 3444- NGDBUILD: Could not find NET " " in design " " with Cadence Concept design 
• Solution 3134- Cadence Concept, M1: How to import a VHDL, Verilog, or LogiBLOX generated netlist into a Concept schematic
• Solution 3074- M1: Cadenece Concept and Verilog-XL: Functional simulation with Mode and Boundary Scan pins in schematic
• Solution 2278- Cadence board-level simulation M1: The -pf option not supported in Design Manager
• Solution 2766- CONCEPT2XIL: How to obtain the M1 Concept netlister
• Solution 2943- How to obtain XIL2CDS for board level integration)
• Solution 2770- CONCEPT2XIL: Problem with CONFIG, PART, TIMESPEC, and TNM properties not being translated to the EDIF file
• Solution 2223- M1.4 Cadence Concept interface: Frequently asked questions

• Solution 3930- Verilog: Timing simulation: An X_FF waveform does not look correct and may be mistaken for a latch
• Solution 3167- M1.4 NGD2VER: How to have M1 automatically specify the addition of the `uselib directive and path to the simulation netlist
• Solution 2573- M1, NGD2VER: How to retain design hierarchy in a Verilog simulation netlist generated by NGD2VER
• Solution 2432- What is needed to do Verilog simulation of 3rd party designs in M1? 
• Solution 2533- NGD2VER M1.2/M1.3: Escaped names (names prefixed with "\" in Verilog netlists generated by NGD2VER

• Solution 2202- M1.4: CADENCE LEAPFROG--Simulating VHDL designs in the Xilinx M1 release

XACT 5.X (XNF flow, Cadence 9404 through 9604)

• Solution 518 - VERILOG: How to perform a timing simulation of a Xilinx design using Verilog-XL
• Solution 649 - XNF2CDS / XNF2Verilog: Symbol does not have a corresponding entry in the PIN file
• Solution 797 - INSTALL, setup and licensing of Sun4 XACT tools with Solaris-based Cadence software
• Solution 1529 - CONCEPT / VERILOG: Concept and Verilog interim solution for doing 9500 designs
• Solution 646 - VERILOG-XL: driving GSR, GR, and GTS in Verilog simulation
• Solution 806 - Post-synthesis Verilog-XL functional simulation is not supported by FUNCNET(X)
• Solution 815 - CONCEPT2XNF 9404, 9502: Problems with GND and VCC symbols in XPADS_HDL library

Pre-XACT 5.X (9403 Cadence and earlier)

• Solution 1716 - GXILINX: Using pre-5.0 (9403 or earlier) Cadence interface with XACT 5.X
• Solution 1479 - GXILINX: FAST property not translated to XNF file / adding support for User properties
• Solution 2106- CADENCE/GXILINX: Netnames containing a "#" sign may be generated by GXILINX, causing XNFPREP Error 3517
• Solution 2018 - XNFMERGE, CONCEPT 9402: ERROR: Cannot find PWR.XNFor GND.XNF / How to connect a pin to VCC or GND