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Xilinx Answer #8354 : Virtex: Virtex has the potential race condition that can occur during the STARTUP
Xilinx Answer #6501 : M1.5i/2.1i: TRCE: What does the timing errors in a timing report correspond to in the design.
Xilinx Answer #6342 : M1.5: Trce 1.5is2: WARNING:basts:157 - PERIOD TIMESPEC ...contains a mixture of pad and synchronous elements
Xilinx Answer #6312 : M1.5i: Trce: exception access violation & Error: xvkdr: 5 - blockcheck:
Xilinx Answer #6052 : M1.5i/2.1i: Trce: Dr. Watson Exception access violation (0xc0000005) Address 0x10xxxxx
Xilinx Answer #6008 : LogiCORE PCI64 Virtex (v3.0): Some timespecs have zero items analyzed in the TRCE report
Xilinx Answer #5896 : M1.5: TRCE: Incorrect skew calculation between clock domains
Xilinx Answer #5864 : M1.5i: Timing Analyzer: SRL16s are placed in both 'RISING' and 'FALLING' clock groups by TRCE
Xilinx Answer #5804 : M1.5: TRCE: WARNING:bastw:544 - Clock nets using non-dedicated resources were found
Xilinx Answer #5510 : M1.5 Trce, WARNING:bastw:169 - The pulse width for this signal is less than the minimum pulse-width
Xilinx Answer #5326 : M1.5i: Virtex Timing - Par and TRCE report different numbers for the same design.
Xilinx Answer #5213 : M1.5i/2.1i: TRCE reports large differences in clock delay (skew) on BUFGLS in XV devices
Xilinx Answer #5103 : M1.5i/2.1i: TRCE: Confusing constraint header when 4X is invoked with CLKDLL.
Xilinx Answer #5102 : M1.5: TRCE: Unconstrained path analysis appears in the middle of the timing report for VIRTEX
Xilinx Answer #4994 : M1.5: Trce: Negative slack reported in OFFSET IN AFTER constraints.
Xilinx Answer #4477 : A1.5: TRCE/ PAR - Timing related applications (par, trce) may run out of memory.
Xilinx Answer #4367 : M1.5i/2.1i: TRACE: Information about Circuit loops reported TRCE/Timing Analyzer
Xilinx Answer #4223 : M1.4 5200: TRCE reports "0 items analyzed" on FROM:THRU:TO timespec
Xilinx Answer #4214 : M1.5: TRCE: Internal constant used to represent NODELAY conflicts with negative delays.
Xilinx Answer #4205 : M1.5i/2.1i: TRCE reports only three paths per timing constraint by default/no limit: How to increase it.
Xilinx Answer #4193 : M1.5: Trce core dumps or causes an application error
Xilinx Answer #4162 : M1.5i/2.1i: TRCE reports timing loop for Virtex designs with DLL's
Xilinx Answer #4073 : TRCE M1.4.12: Incorrect minimum period and maximum frequency reported.
Xilinx Answer #3888 : M1.5i/2.1i: TRCE : How does trce list the number of timing errors?
Xilinx Answer #3773 : M1.4 PAR, TRCE, Timing - How to invoke the "KPATHS" timing algorithm.
Xilinx Answer #3593 : M1.5i: TRCE/Timing Analyzer: 0 items analyzed for OFFSET timespec
Xilinx Answer #3466 : Constraints/UCF/TRCE: How fine can the resolution be on timing constraints?
Xilinx Answer #3143 : M1.5i/2.1i: TRCE: Path tracing behavior for RAMs
Xilinx Answer #3014 : M1.5i/2.1i: TRCE: "HIGH" or "LOW" keyword for PERIOD may not work as expected with OFFSET
Xilinx Answer #2945 : TRCE: How does TRCE calculate worst case timing values if it is unaware of the temperature grade for a part?
Xilinx Answer #2896 : M1.4: TRCE reports large delay on net driven by TBUFs with PULLUP
Xilinx Answer #2828 : M1.3.7 TRCE - Timing constraint does not relax period constraint
Xilinx Answer #2790 : M1.3.7 TRCE - Doing a TIG in the UCF file on a signal which is the output of a tristate buffer does not work.
Xilinx Answer #2740 : TRCE: How to analyze (the longest) nets/paths in timing constraints
Xilinx Answer #2728 : TRCE: How to analyze overall timing constraint performance
Xilinx Answer #2443 : TRCE M1.3: Paths that include RAMs deeper than 16 address cells not analyzed.
Xilinx Answer #2435 : M1.5i/2.1i: TRCE/Timing Analyzer: 0 paths analyzed for a TIMESPEC which should have paths
Xilinx Answer #1871 : TRCE: Reports May Contain Preliminary Timing Values
Xilinx Answer #1867 : M1.xi: TRCE: IOB register to PAD paths (and vice-versa) are not reported or controlled