CPLD Implementation Tools: Tips and Techniques  Design Entry Tools Hardware/Programming Solutions Core Implementation Tools Power Sequencing/Consumption Pin-Locking Timing

Design Entry Tools

• Solution 1045: Foundation Simulator: XC9500 flip-flop outputs unknown (PRLD signal)
• Solution 1651: XC9500: Configuring device I/Os as an open-drain (open-collector)
• Solution 1706: XABEL: How to get Test Vectors (.TMV file) into an XC9500 JEDEC file.
• Solution 3000: XC9500: Why do the XC9500 libraries have pull-up elements?
• Solution 3123: XC9500: How are initial states of flip-flops determined on 9500 CPLDs?
• Solution 3705: Foundation-Express: XC9500 Recommended Synthesis and Fitter Options
• Hints, Tips and Tricks for using XABEL with Xilinx M1.5 Design and Implementation Tools
• A CPLD VHDL Introduction
• Using ABEL with Xilinx CPLDs

Core Implementation Tools

• Solution 983: XC9500: How to set FAST slew rate for 9K outputs in PLUSASM and ABEL
• Solution 1400: XC9536: Does not have local feedback paths  
• Solution 1536: XC9500: How are unused I/O pins handled?  
• Solution 2109: XC9500: Fitter Report Equation Syntax 
• Solution 2579: XC9500: How to utilize the Wired-AND (WAND) in the UIM 
• Solution 2704: XC9500: How does CPLD Auto Device Selection Work 
• Solution 2729: XC9500: How to Control Logic Optimization in a CPLD 
• Solution 2860: XC9500: How to read the CPLD report (.RPT) file?
• Solution 3122: XC9500: How do the BUFGSR, BUFG, and OE buffers work on the 9500? 
• Solution 3194: XC9500: What is the default value of tri-states for CPLDs? 
• Planning for High Speed XC9500XL Designs
• Designing with XC9500XL CPLDs
• Designing with XC9500 CPLDs

Pin-Locking

• Solution 2719: How to control Pinout of a CPLD 
• Pin Preassigning with XC9500 CPLDs

Hardware/Programming Solutions

• XC9500: How many outputs can you simultaneously drive at 24 mA?
• XC9500: Device Slew Rates (Rise/Fall times) with capacitive loads
• XC9500: How are unused I/O pins handled?
• XC9500: When can the XC9500 internal IOB pullups be accessed?
• Solution 1701: XC9500: "Single Cell Charge Loss" (SCCL) or "Single Bit Charge Loss" (SBCL).
• Solution 1707: XC9500: Minimum Reset Signal Pulse Width.
• Solution 1625: XC9500: Quiescent Supply Current.
• XC9500: Maximum Icc by package type
• Typical I/V Characteristics of XC9500 Outputs
• Metastability Considerations

Power Sequencing/Estimation

• Solution 2717: How to control Power Consumption
• Solution 2146: XC9500: How to place a macrocell/signal in low power mode (LOWPWR) in a CPLD
• Solution 2653: Power estimation in 9500 family devices
• XC9500: Does Vccint have to be powered up before Vccio?
• XC9500 CPLD Power Sequencing
• Understanding XC9500XL CPLD Power

Timing

• Solution 2732: How to control Timing Paths in a CPLD 
• M1.3/M1.4 CPLD: How to calculate the timing across a latch in a 9K device
• M1, Timing, CPLD: What are negative setup times in CPLD Performance report?
• Using the XC9500 Timing Model
• Using the XC9500XL Timing Model