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Xilinx Answer #7378 : 1.5i/2.1i: Hierarchical constraints with dc2ncf are not supported
Xilinx Answer #6662 : M1.5i/2.1i: Timing: Instantiated TDO Pad Conflicts With UCF Constraint Causing error baste:263
Xilinx Answer #6368 : M1.5: Timing Analyzer1.5isp2: the exclude paths with nets option doesn't work.
Xilinx Answer #6309 : F1.5i: Timing: Timing Error: This program has perform an illegal operation.
Xilinx Answer #6266 : 1.5i 4KXLA Timing - New speed data is now available for XC4000XLA
Xilinx Answer #6265 : 1.5i Timing - The Preliminary -09 speed grade for the xc4000xv family is now available
Xilinx Answer #6067 : M1.5i/2.1i: How to obtain timing information from new speedfiles: Speedprint utility
Xilinx Answer #6066 : M1.5i/2.1i: RISING and FALLING constraint grouping does not filter out non-FF elements
Xilinx Answer #6032 : 1.5i SP1 - ERROR:xvkap:53 RLOC constraints have been applied to a subset of the slices
Xilinx Answer #5965 : M1.5i/2.1i; Timing: PERIOD constraint analyzes path from a FROM:THRU:TO spec
Xilinx Answer #5927 : M1.5i Virtex Pin2ucf - An incorrect signal name is used in the .ucf data for Clock signals in Virtex devices.
Xilinx Answer #5849 : M1.5i SP2 XC4000XLA Timing - New speed data is available.
Xilinx Answer #5839 : M1.5i Sp2 XC4000XV Timing - XC4000XV timing analysis incorrectly reports ~20ns delay on data input to INFF.
Xilinx Answer #5837 : 1.5i SP2 X4000XV Timing - Some incorrect speed values have been corrected in the XC4000XV speed files.
Xilinx Answer #5796 : Timing Constraint on BSCAN element
Xilinx Answer #5747 : M1.5i/2.1i: UCF priority
Xilinx Answer #5566 : M1.5i SpartanXL Timing - New speed files are available for Spartan XL in Service Pack 2.
Xilinx Answer #5552 : M1.5i Timing -Several changes are needed for virtex names to correspond to data sheets.
Xilinx Answer #5551 : 1.5i Timing - Mapper is not including Both halves of BLOCKRAM in clock net TNM.
Xilinx Answer #5550 : M1.5i Virtex Timing - Timing tools are not heeding DUTY_CYCLE_CORRECTION parameter.
Xilinx Answer #5548 : M1.5i Timing - TW is not correctly distributing a Net PERIOD if the CLKDV has a non-integer value.
Xilinx Answer #5508 : Timing Simulation: How to Generate the Testfixture file, time_sim.tv, for an existing implementation
Xilinx Answer #5489 : M1.5i/2.1i: Timing: How the OFFSET IN and OUT calculation is made?
Xilinx Answer #5178 : VERILOG-XL: Timing violation: $recovery(posedge CLKB: 800, posedge CLKA: 800, 1.0: 10)
Xilinx Answer #5121 : M1.5i/2.1i: Timing: Explaination of a Timing Report File (.TWR)
Xilinx Answer #4978 : M1.5i/2.1i: What are the resources that needs to be constrained in the user constraint file?
Xilinx Answer #4922 : Foundation/Alliance 1.5: during place and route - warning: basrt:188 routing for this placement can not meet all timing constrainsts it may have as many as 1 timing errors.
Xilinx Answer #4910 : M1.5: Timing Constraint Priority is being ignored for FROM:THRU:TO.
Xilinx Answer #4624 : M1.5i/2.1i: Timing Analyser cannot be used to analyse a path through the asych PRE/CLR of an XC9500 FDCP
Xilinx Answer #4618 : M1.5i Timing - Nets with TIGs are incorrectly being included in some timespecs.
Xilinx Answer #4616 : A1.5 xc3090l-tq176 - ERROR:baste:262 - Bad format for LOC constraint P128 on OPAD symbol ...
Xilinx Answer #4491 : A1.5 XSI: Makeucf is a PERL utility that simplifies the creation of timespecs for FPGA Compiler users
Xilinx Answer #4343 : Foundation F1.5, Timing Simulation: Must backstep out of Timing to generate Timing Simulation Data
Xilinx Answer #4334 : CST to UCF Conversion: Is there a utility I can use?
Xilinx Answer #4293 : Galileo , M1.4 : Error :x4kma : 239 - EQN symbol "mtt_modgen_2_modgen_67_ix84"(output signal = mtt_modgen_2_nx358) - The attribute RLOC has been placed on wrong type of symbol.
Xilinx Answer #4275 : M1.5: WARNING:basts:158 - PERIOD TIMESPEC 'xxx' has TIMEGRP 'xxx' which contains only PAD elements. Or mixture of PADs and synchronous elements.
Xilinx Answer #4188 : M1.5i/2.1i: Timing Report: There is no negative offset, setup, or hold time
Xilinx Answer #4161 : M1.5i/2.1i: Cannot TIMESPEC the TDO/MD1 pin on XC4000E/X FPGAs.
Xilinx Answer #4156 : M1.5 Timing analysis doesn't use TPTHRU as more specific than FROM:TO
Xilinx Answer #4085 : M1.x: Is there a way to access vertical longlines in FPGA (with ucf or pcf constraint)?
Xilinx Answer #4028 : M1.5i/2.1i :Post Layout Timing Report: No skew warning given for internal clocks
Xilinx Answer #4001 : M1.4.12: TNM does not get attached to all FFS (FDCE)
Xilinx Answer #3753 : M1.5i/2.1i: Constraints: UCF to PCF conversion examples
Xilinx Answer #3632 : M1.4:FATAL_ERROR:baste:bastetspec.c:1333:1.69 - TNM TI_H1 on NET 'TI_H1' has a reference that has no NC_BEL and no TECHMAP_SIGNAL
Xilinx Answer #3517 : M1.4 TRACE: Do NOT activate CMOS level timing for XL family
Xilinx Answer #3516 : M1.4 Timing: Do NOT use the FTP patch M1.3.7 speed files for EX
Xilinx Answer #3470 : M1.4 Constraints: LOC'ing a PAD to an edge or multiple sites
Xilinx Answer #3332 : M1.3/1.4 TRACE: A DPRAM DPO to destination FROM:TO constraint is not analyzed
Xilinx Answer #3139 : dc2ncf: ERROR [#154]: Invalid argument -max for set_input_delay constraint at line x
Xilinx Answer #3085 : M1.3: TIMING: Page Fault in Win95, FATAL_ERROR:baspp:basppphys on Workstations
Xilinx Answer #3016 : M1 TNM placed on net between PAD and BUFG/IBUF not forward traced
Xilinx Answer #3015 : M1 PERIOD placed on net between PAD and IBUF not analyzed
Xilinx Answer #2963 : Timing: How to find the paths not covered by Constraints/Advanced Analysis? i.e. coverage < 100%, i.e. 0 items analyzed
Xilinx Answer #2948 : M1.3 CPLD: Fitter patch causing timespecs to dissappear
Xilinx Answer #2898 : How to ignore/remove LOC constraints on PADS?
Xilinx Answer #2741 : --OBS--M1.3 4kex Timing - Long delays are calculated for TBUFs driving long lines with Pullups.
Xilinx Answer #2716 : M1.3/M1.4 CPLD: How to create timing simulation netlist in the XNF format
Xilinx Answer #2691 : --OBS--M1.3.7 Timing - XC4000E speed file patch available that correct three problems
Xilinx Answer #2582 : M1.5: Timing Analysis reports 0 items analyzed for IOB flops, IFD, OFD
Xilinx Answer #2570 : M1 CONSTRAINTS: How to specify SAVESIG ("S"), "KEEP", or "X" constraints on nets using a UCF file.
Xilinx Answer #2480 : M1.3: NODELAY Attribute may be ignored in .ucf file without warnings or errors.
Xilinx Answer #2374 : Timing error reported for both flop and RAM, but only applies to RAM
Xilinx Answer #2339 : M1.5i/2.1i; CPLD: TIG (Ignore Timing) timing constraint not supported
Xilinx Answer #2283 : HDL timing simulation: compiling testbench reveals port mismatches
Xilinx Answer #1763 : M1 - RLOCs May Not Be Attached to Hard Macros
Xilinx Answer #1642 : M1 : Examples of Timing Specification in the User Constraint File (.ucf)
Xilinx Answer #1607 : Constraints: How do I specify Timespec and Timegroup constraints in a UCF file
Xilinx Answer #1604 : M1: Pin Locking, I/O Constraints in UCF file
Xilinx Answer #1331 : How to add XACT-Performance (Timespec) constraints to my CST file
Xilinx Answer #800 : M1.5i/2.1i: Constraints: TNM's cannot be attached to tri-stated output flip flops (OFDT) via the TIMEGRP statement.