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Xilinx Answer #8313 : 2.1i sp4 Trce/Timing analyzer : Trace gives different timing results than the Timing Analyzer
Xilinx Answer #7827 : 2.1i PAR - PAR and TRCE report different numbers for the same routing.
Xilinx Answer #7703 : TRCE/Timing Analyzer 2.1i: Clock DLLs with period constraints appear in the reports as if they are not constrained
Xilinx Answer #7483 : 2.1i TRCE Spartan\XL: Input hold time using Primary Clock and IFF is non-zero even with delay
Xilinx Answer #7340 : 2.1i TRCE - Paths are reported against the wrong timing constraint.
Xilinx Answer #7332 : 2.1i TRCE- Results different when -u switch is used.
Xilinx Answer #7131 : TRCE/Timing Analyzer 2.1i: 0 items analysed on OFFSET constraints in Virtex designs on ofd/ifds
Xilinx Answer #6896 : 2.1i TRCE: WARNING:bastw:544 - Clock nets using non-dedicated resources
Xilinx Answer #6501 : M1.5i/2.1i: TRCE: What does the timing errors in a timing report correspond to in the design.
Xilinx Answer #6450 : 2.1i: TRCE/Timing Analyzer: Does not support reg_sr_clk path tracing control.
Xilinx Answer #6449 : 2.1i: TRCE/Timing Analyser: Skew not automatically accounted for on Virtex low skew clocks
Xilinx Answer #6448 : 2.1i: TRCE/Timing Analyzer does not provide the ability to constrain the blockram halves separately.
Xilinx Answer #6447 : 2.1i: TRCE/Timing Analyzer: Unconstrained path report contains constrained paths & paths constrained by OFFSETs.
Xilinx Answer #6445 : 2.1i: TRCE/Timing Analyzer: ERROR: basut: 162 - This Xilinx application has run out of memory ...
Xilinx Answer #6240 : TRCE/Timing Analyzer 2.1i: Elements are analyzed by Period and not FROM:THRU:TO
Xilinx Answer #6166 : 2.1i: TRCE - The number of logic levels reported differently when different trce options are used
Xilinx Answer #6094 : 2.1i: TRCE/Timing Analzyer The Datasheet Report is inconsistent with verbose path report
Xilinx Answer #6052 : M1.5i/2.1i: Trce: Dr. Watson Exception access violation (0xc0000005) Address 0x10xxxxx
Xilinx Answer #5213 : M1.5i/2.1i: TRCE reports large differences in clock delay (skew) on BUFGLS in XV devices
Xilinx Answer #5103 : M1.5i/2.1i: TRCE: Confusing constraint header when 4X is invoked with CLKDLL.
Xilinx Answer #4367 : M1.5i/2.1i: TRACE: Information about Circuit loops reported TRCE/Timing Analyzer
Xilinx Answer #4205 : M1.5i/2.1i: TRCE reports only three paths per timing constraint by default/no limit: How to increase it.
Xilinx Answer #4162 : M1.5i/2.1i: TRCE reports timing loop for Virtex designs with DLL's
Xilinx Answer #3888 : M1.5i/2.1i: TRCE : How does trce list the number of timing errors?
Xilinx Answer #3143 : M1.5i/2.1i: TRCE: Path tracing behavior for RAMs
Xilinx Answer #3014 : M1.5i/2.1i: TRCE: "HIGH" or "LOW" keyword for PERIOD may not work as expected with OFFSET
Xilinx Answer #2435 : M1.5i/2.1i: TRCE/Timing Analyzer: 0 paths analyzed for a TIMESPEC which should have paths