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Xilinx Answer #8328 : Coolrunner/XPLA : How do I use the TDO as an output pin?
Xilinx Answer #8173 : XPLA Family: Which CoolRunner devices have ISP or Boundary Scan operations capability?
Xilinx Answer #8030 : XPLA Logistics: CoolRunner packages TQFP, LQFP are equivalent to the Xilinx VQ and TQ packages respectively.
Xilinx Answer #7932 : XPLA Professional: Where can I find a CoolRunner Libraries Guide?
Xilinx Answer #7884 : XPLA Professional Documentation: XCR5128 (Quad Flat Pack 128) Pinout in the XPLA Professional Users Manual is incorrect.
Xilinx Answer #7848 : XPLA Professional: IBIS models are not available for the CoolRunner products
Xilinx Answer #7845 : XPLA Professional: What do the CoolRunner net names X_#_ stand for?
Xilinx Answer #7810 : XPLA Professional: Functional simulation works but timing simulation yields unknown outputs
Xilinx Answer #7778 : XPLA : Warning - wired or in net = <signalname>
Xilinx Answer #7707 : XPLA Professional: Y2K readiness
Xilinx Answer #7697 : XPLA Professional: Differences between ABEL and PHDL.
Xilinx Answer #7678 : XPLA Logistics: Future support of the CoolRunner software.
Xilinx Answer #7645 : XPLA Professional: Version 3.31 ignores the pin assignments in a PAF file that was generated in the previous version.
Xilinx Answer #7636 : XPLA Professional: Schematic Capture library manual.
Xilinx Answer #7635 : XPLA Professional: Where is the XPLA Professional Users Manual?
Xilinx Answer #7634 : XPLA Professional: Where can you download the workstation version of the XPLA Professional software?
Xilinx Answer #7627 : XPLA-PC-ISP :Error 02 - Write Registry failed, You may not be able to access parallel port.
Xilinx Answer #7592 : XPLA CoolRunner Programmer: Programming the XCRx032-CS or XCRx032-AS VQ44 type parts.
Xilinx Answer #7590 : Third Party Tool Flow: Third party tool flows for the Coolrunner Product
Xilinx Answer #7588 : PC-ISP Programmer: What cable should be used with the CoolRunner ISP Programmer?
Xilinx Answer #7587 : XPLA PC-ISP Programmer: Which download cable is needed to program an ISP CoolRunner CPLD.
Xilinx Answer #7586 : XPLA PC-ISP Programmer: How to obtain the CoolRunner XPLA PC-ISP Programmer software.
Xilinx Answer #7585 : XPLA PC-ISP Programmer: Software is used to program the CoolRunner ISP CPLDs.
Xilinx Answer #7583 : XPLA PC-ISP Programmer: Documentation for the ISP cable & header.
Xilinx Answer #7582 : XPLA PC-ISP Programmer: Generating MCS files for the XCR3960/XCR3320?
Xilinx Answer #7581 : XPLA PC-ISP Programmer: Large amounts of current consumed during a "Verify".
Xilinx Answer #7580 : XPLA PC-ISP Programmer: Message "driver vicprt11 not found" when software finds the parts on the board.
Xilinx Answer #7579 : XPLA PC-ISP Programmer: XPLA1 ISP Proto Board CPLD does not function improperly.
Xilinx Answer #7577 : XPLA PC-ISP Programmer: Generating binary files for JEDEC programming.
Xilinx Answer #7576 : XPLA PC-ISP Programmer: Generating vectors for Microcontroller use.
Xilinx Answer #7575 : XPLA PC-ISP Programmer: ATE vector clock speed for TCK.
Xilinx Answer #7574 : XPLA PC-ISP Programmer: New parts do not program via ISP in a known good system.
Xilinx Answer #7573 : XPLA PC-ISP Programmer: CoolRunner does not program when detected in the chain.
Xilinx Answer #7571 : XPLA PC-ISP Programmer: Accessing non-CoolRunner devices.
Xilinx Answer #7570 : XPLA PC-ISP Programmer: Debug tips on custom built download cables
Xilinx Answer #7569 : XPLA PC-ISP Programmer: Can not find ISP Cable or Board.
Xilinx Answer #7568 : XPLA PC-ISP Programmer: Programmer cannot find or recognize a file
Xilinx Answer #7567 : XPLA PC-ISP Programmer: Supported operating system.
Xilinx Answer #7566 : XPLA PC-ISP Programmer: How to load a JEDEC file, versus a JCD file?
Xilinx Answer #7565 : XPLA PC-ISP Programmer: Generating ATE vectors.
Xilinx Answer #7564 : XPLA Professional: Properties for nodes not at the top level of a schematic.
Xilinx Answer #7563 : XPLA Professional: XPLA Properties.
Xilinx Answer #7562 : XPLA Professional: Forcing a design into a specific logic block.
Xilinx Answer #7561 : XPLA Professional: Attribute ISTYPE INVERT.
Xilinx Answer #7560 : XPLA Professional: Generating a simulator clock with a delayed starting time.
Xilinx Answer #7555 : XPLA Professional: Simulator runs for long periods of time.
Xilinx Answer #7554 : XPLA Professional: Estimated Icc for a CoolRunner design from a Third party *.jed file.
Xilinx Answer #7553 : XPLA Professional: Support until CoolRunner is supported in Xilinx software.
Xilinx Answer #7552 : XPLA Professional: CoolRunner integrated into WebPACK.
Xilinx Answer #7551 : XPLA Professional: PHDL support.
Xilinx Answer #7550 : XPLA Professional: Schematic capture support.
Xilinx Answer #7548 : XPLA Professional: Designing into a CoolRunner device using VHDL or Verilog?
Xilinx Answer #7547 : XPLA Professional: Obtaining XPLA Professional.
Xilinx Answer #7546 : XPLA Professional: XPLA Designer XL.
Xilinx Answer #7545 : XPLA Professional: Simultaneous reset and preset.
Xilinx Answer #7544 : XPLA Professional: Timing driven synthesis.
Xilinx Answer #7543 : XPLA Professional: Pin reassignment.
Xilinx Answer #7542 : XPLA Professional: Creating symbols in Schematic Capture for PHDL or Verilog modules.
Xilinx Answer #7541 : XPLA Professional: Description of a node in the CoolRunner parts.
Xilinx Answer #7540 : XPLA Professional: Creating equations in the form of a *.phd or *.phj file from a *.jed file.
Xilinx Answer #7538 : XPLA Professional: Sequence of statements in a *.scl file.
Xilinx Answer #7537 : XPLA Professional: Creating a soft flip-flop with Q-bar output.
Xilinx Answer #7533 : XPLA Professional: What does the XPLA Property "TRI-STATE" do?
Xilinx Answer #7532 : XPLA Professional: How to force a value onto internal nodes during simulation?
Xilinx Answer #7531 : XPLA Professional: SPICE models for the CoolRunner family.
Xilinx Answer #7530 : XPLA Professional: How to estimated Icc for a CoolRunner design.
Xilinx Answer #7529 : XPLA Professional: Fitter errors when reset signal cannot be assigned to the global reset pin on XPLA2 devices.
Xilinx Answer #7528 : XPLA Professional: Compiler fails when tri-state buffers are defined as buried nodes.
Xilinx Answer #7527 : XPLA Professional: Fitter continues when more PLA terms are required than resources allow.
Xilinx Answer #7526 : XPLA PC-ISP Programmer: GUI has incorrect graphics and cut off messages.
Xilinx Answer #7525 : XPLA Professional: GUI has incorrect graphics and cut off messages.
Xilinx Answer #7524 : XPLA Professional: Timing simulation gives different results than simulation with the *.vho or *.vo file.
Xilinx Answer #7523 : XPLA Professional: Implementing a latch in a CoolRunner?
Xilinx Answer #7522 : XPLA Professional: Targeting an Altera design to a CoolRunner device.
Xilinx Answer #7519 : CoolRunner/XPLA Professional: What are the main software features of the XPLA Professional software?
Xilinx Answer #7516 : CoolRunner/XPLA Professional: How to use the control files with the CoolRunner/XPLA Products?
Xilinx Answer #7515 : CoolRunner/XPLA Professional: What is the recommended procedure to properly install XPLA Professional software?
Xilinx Answer #7513 : CoolRunner/XPLA Professional Simulator: Why doesn't the simulator use the *.scl file when a signal is not recognized?
Xilinx Answer #7507 : CoolRunner/XPLA Professional Simulator: What does the "Bitmap allocation error. Possible too many signals" mean?
Xilinx Answer #7506 : CoolRunner/XPLA Professional: Why does the print out of pin editor look incorrect?
Xilinx Answer #7505 : CoolRunner/XPLA Software: Which third party tool vendors provide support for the CoolRunner/XPLA devices?
Xilinx Answer #7504 : CoolRunner/XPLA Professional: What can be done to get a better fit if a design does not fit into the selected device?
Xilinx Answer #347 : XDE/EDITLCA 5.0: Explanation of ODF, OLF, DBK, LOG files