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Xilinx Answer #8509 : CPLD XC9500/XL/XV: GSR is not used when using registers that are synchronously reset
Xilinx Answer #5921 : 9500 datasheet - What is the "block software selectable" option for pullup resistors?
Xilinx Answer #5685 : F1.5i_sp1: 9500XV auto-selection does not work automatically in current release
Xilinx Answer #5657 : **Obsolete**F1.5i_sp1: 9500XV - Can be found under the 9500XL pull-down menu
Xilinx Answer #5175 : CPLD : XC9500XL: What is bus-hold circuit?
Xilinx Answer #4719 : CPLD: 9500/XL : Is there any hysteresis on the inputs to 9500 or 9500XL devices?
Xilinx Answer #4475 : CPLD: XC9500: What is the erase time required by all 9500 devices
Xilinx Answer #4449 : 9500: GENRAD ATE, Using DSM (Deep Serial Memory) to reduce DTS file size
Xilinx Answer #4288 : CPLD: XC9500/XL Programming: Write Security can be overriden in JTAG Programmer but not Hw-130 or third party programmer.
Xilinx Answer #3809 : XACT-CPLD: Mentor & Cadence interface patches available for the XC9500 family
Xilinx Answer #3807 : XACT-CPLD: Listing of all the Fitter patches
Xilinx Answer #3787 : EZTAG/JTAG Programmer: How to create a SVF file that performs a blank check operation?
Xilinx Answer #3748 : CPLD: XC9500/XL: Generic XC9500/XL IBIS (I/O Buffer Information Specification) model is on the FTP site
Xilinx Answer #3656 : XC9500: IDCODE instruction fails when used in an embedded or ATE environment using svf files
Xilinx Answer #3653 : CPLD: XC9500: Device fails to erase when used in an embedded or ATE environment
Xilinx Answer #3652 : JTAG - Troubleshooting hints for the Embedded microprocessor ISP programming
Xilinx Answer #3596 : CPLD: XC9500/XL : What cables and voltages can I use to program a CPLD?
Xilinx Answer #3579 : CPLD: 9500: What are the checksums in a JEDEC file and how do I read it?
Xilinx Answer #3571 : XC95108 with date code of 9717 is not configuring
Xilinx Answer #3567 : CPLD: 9500/XL :Sourcing internal logic with a global buffer
Xilinx Answer #3518 : CPLD: 9500: What are the differences between reset lines in simulation and on the device
Xilinx Answer #3400 : ** M1.4 CPLD: C1244, internal error, corrupted partition product term.
Xilinx Answer #3255 : XC9500: How to program mulitple devices in a single chain using the HP3070 tester?
Xilinx Answer #3254 : EZTAG: XC9500: How to create a single SVF file from multiple SVF files for devices in a single chain?
Xilinx Answer #3252 : XC9500: Miscellaneous programming questions
Xilinx Answer #3226 : CPLD: XC9500: What are the recommended maximum rise times for inputs?
Xilinx Answer #3214 : CPLD: XC9500: Difference between all the checksums for the XC9500 family
Xilinx Answer #3177 : JTAG - How to co-relate the states in the SVF file to TAP controller states?
Xilinx Answer #3173 : JTAG - How to read SVF files.
Xilinx Answer #3162 : CPLD: XC9500: What is the Maximum Junction Temperature allowed in the CPLDs
Xilinx Answer #3125 : M1.4 CPLD: Automatic Local Feedback optimization not yet supported for XC9500
Xilinx Answer #3122 : CPLD: 9500/XL :How do the BUFGSR, BUFG, OE buffers work on the 9500/XL?
Xilinx Answer #3116 : Typical I/V Characteristics of XC9500 Outputs
Xilinx Answer #3082 : CPLD : XC9500: obtaining Fcnt (operating freq for 16 bit counters)
Xilinx Answer #3026 : CPLD: 9500* : Usage of internal pullup in IOB
Xilinx Answer #3006 : CPLD: How to calculate the timing accross a latch in a 9K device
Xilinx Answer #3000 : CPLD: XC9500/XL: Why do the XC9500/XL libraries have pull-up elements?
Xilinx Answer #2997 : XC9500: Corrected model from LMG now available
Xilinx Answer #2975 : XC95108: Are Programmable grounds supported?
Xilinx Answer #2944 : XC9500: Can I Hot Sync my XC9500 device
Xilinx Answer #2876 : CPLD: XC9500: What type of drivers does the 9500 output buffers use?
Xilinx Answer #2875 : CPLD: XC9500: Maximum Icc by package type
Xilinx Answer #2780 : XC9500: Logic erroneously trimmed away when using HDL macros in 9k schematic design
Xilinx Answer #2730 : How to connect unused 9500 outputs to known levels
Xilinx Answer #2676 : TERADYNE Z1800 ATE SUPPORT FOR XC9500
Xilinx Answer #2653 : CPLD: XC9500/XL : Power estimation for the 9500/XL family devices
Xilinx Answer #2538 : CPLD: 9500 - How to invert the global set/reset pin
Xilinx Answer #2178 : CPLD : 9500: Quality Assurance: How are Xilinx xc9500/xc7300 parts tested?
Xilinx Answer #2174 : XC9500: Hitop.exe fails erroneously saying too many pins are used on 9500 design
Xilinx Answer #2150 : CPLD: XC9500: The high level output voltage of an 9500 CPLD is ~4 volts
Xilinx Answer #2144 : XC9500 JTAG - How long does it take to carry out various JTAG instructions in 9500 CPLDs?
Xilinx Answer #2139 : CPLD: 9500 : Are 9500 Inputs 5 volt tolerant when Vccio is 3.3 volts?
Xilinx Answer #2133 : CPLD: 9500: EZTag : xchecker rcab error 4059
Xilinx Answer #2126 : CPLD: 9500/XL : ESD information
Xilinx Answer #2109 : CPLD : XC9500/XL Fitter Report Equation Syntax
Xilinx Answer #2065 : HW-130/XC95216: Product code errors when programming a device
Xilinx Answer #2029 : CPLD: XC9500: Programming an XC9500 CPLD with a microcontroller (ISP)
Xilinx Answer #1956 : XACT-CPLD, XC9500: Assertion failed: ia.RetSize()==1 && ia[0]->RetInputInstance(), file outinst.cc
Xilinx Answer #1884 : CPLD XC9500/XL: What is the guaranteed spec for data retention?
Xilinx Answer #1816 : XC9500: How to detemine low power mode timing (tLP, TLOGILP)
Xilinx Answer #1791 : XC9500F JTAG - Does it support JTAG functionality?
Xilinx Answer #1707 : CPLD XC9500: Minimum reset signal pulse width
Xilinx Answer #1701 : XC9500: "Single Cell Charge Loss" (SCCL) or "Single Bit Charge Loss" (SBCL)
Xilinx Answer #1700 : CPLD XC9500/XL: Test process of devices before shipment
Xilinx Answer #1688 : XACT-CPLD, 9500: What do my environment settings need to be?
Xilinx Answer #1638 : XABEL,XACT-CPLD: Only one product term allowed for OE, Set, Reset, Clk (9500, 7300)
Xilinx Answer #1629 : 9500 EZTAG: Patches/Updates are availible on Xilinx BBS/FTP site
Xilinx Answer #1625 : XC9500: Quiescent Supply Currents
Xilinx Answer #1603 : CPLD :XC9500/XL: When can the XC9500 internal IOB pullups be accessed?
Xilinx Answer #1594 : XACT-CPLD: rg37:[Warning] Programming output for device type 95144160 is not supported
Xilinx Answer #1589 : 95216F .LCF file missing from HW-130 archive
Xilinx Answer #1572 : XC9572: JEDEC file generation and JTAG programming support
Xilinx Answer #1536 : CPLD: XC9500/XL: How are unused I/O pins handled?
Xilinx Answer #1523 : X9500: Using Local Feedback Paths
Xilinx Answer #1490 : CPLD: XC9500: Device Slew Rates (Rise/Fall times) with capacitive loads
Xilinx Answer #1489 : CPLD: 9500: How do you use global clock nets?
Xilinx Answer #1480 : CPLD: XC9500: What is the Power consumption/dissipation of a 9500 device?
Xilinx Answer #1478 : CPLD: XC9500: Does Vccint have to be powered up before Vccio?
Xilinx Answer #1408 : CPLD: XC9500/XL: What should be done with unused JTAG pins in the XC9500/XL?
Xilinx Answer #1400 : CPLD: XC9536 Does not have local feedback paths
Xilinx Answer #1367 : **Obsolete Solution**: CPLD: XC9500: What is the JTAG app note is being refered to on page 3-14 of the 7/96 Databook?
Xilinx Answer #1308 : CPLD: XC9500: How many outputs can you simultaneously drive at 24 mA?
Xilinx Answer #1282 : CPLD: XC9500: Pull-ups in IOB should pull up to VccIO, not VccINT as Data Book shows
Xilinx Answer #1162 : FPGA/CPLD: Boundary Scan: Where do you get BSDL files for the Xilinx FPGAs and CPLDs?
Xilinx Answer #1113 : **CPLD : 9500 : Programmer: EZTAG: Errors 1020, 1019: While programming 9500 device with Xchecker cable
Xilinx Answer #1081 : **Obsolete Solution**: Programmers: EZTAG: Can't find file "other.bsd" when programming chain of 9500's
Xilinx Answer #1072 : Fast outputs versus fast slew rate outputs in Xilinx devices
Xilinx Answer #1067 : FPGA/CPLD/PROM: Markings: What are the Device/Package Markings for Xilinx Devices?
Xilinx Answer #1058 : **Obsolete Solution**: XACT-CPLD: 9500: Creating Programmable Ground Pins in XC9500 Designs
Xilinx Answer #1047 : **Obsolete Solution**: XACT-CPLD: hi12:[Error]Keyword MC9500_PTERM_LIMIT in the CTL file is invalid.
Xilinx Answer #983 : CPLD: XC9500/XL: How to set FAST slew rate for 9K outputs in PLUSASM and ABEL?
Xilinx Answer #788 : **Obsolete Solution**: CPLD: Attribute Assignment: Using the LOC attribute for Function block and macrocell assignment (XEPLD v6.0)
Xilinx Answer #749 : CPLD Datasheets - How to get 9500 or 9500XL information?