|
|
|
|
|
|
Xilinx Answer #8576 : 2.1i COREGEN: 64 point FFT datasheet erroneously refers to YK_R and YK_I ports in the pinout table
Xilinx Answer #8532 : 2.1i, V1.5 COREGEN: How to run CORE Generator in verbose mode
Xilinx Answer #8497 : 2.1i COREGEN: Not all EDIF files may be copied over when generating cores made up of multiple EDIF files
Xilinx Answer #8446 : 2.1i COREGEN: Format of the COE file for the C_IP4 Virtex DA FIR Filter core
Xilinx Answer #8382 : 2.1i COREGEN, C_IP4: C_IP4 contains FAE beta version of Asynchronous FIFO datasheet
Xilinx Answer #8381 : 2.1i COREGEN, SOLARIS, HP: Coregen appears to scan newly installed cores every time it is started up
Xilinx Answer #8379 : 2.1i, V1.5x COREGEN, VIRTEX: Availability of PDA FIR and SDA FIR filter modules for Virtex
Xilinx Answer #8374 : 2.1i COREGEN, VERILOG: 'Error! Too many module instance parameter assignments [in] "XilinxCoreLib/async_fifo_v1_0.v", 839: C_GATE_BIT_V1_0'
Xilinx Answer #8372 : 2.1i COREGEN, C_IP4: Virtex Asynchronous FIFO Verilog simulation "ERROR: Module or primitive (ASYNC_FIFO_V1_0) not defined"
Xilinx Answer #8316 : 2.1i COREGEN: "ERROR: ... Can not find initial Contents file to read: <module_name>.mif" when READ MIF is selected
Xilinx Answer #8315 : 2.1i COREGEN, C_IP4: "FATAL: RPM arrangement for a1/RAM_0/BIT_1 cannot be placed in RPM arrangement for a1/RAM_0 due to resource contention." for RAM-Based Shift Register
Xilinx Answer #8314 : 2.1i COREGEN, C_IP4: RAM-based SHIFT REGISTER behavioral model does not match backannotated simulation when CE = 'X'
Xilinx Answer #8308 : 2.1i COREGEN, C_IP4: "Illegal value FALSE for variable write_mif" when regenerating Coregen RAM for Virtex
Xilinx Answer #8304 : 2.1i COREGEN, C_IP4, VIRTEX, FFT: "Generating the core will overwrite the following [xdsp_xxxx.edn] files" when generating more than one FFT
Xilinx Answer #8288 : 2.1i COREGEN: How to access the CORE Generator User Guide Documentation
Xilinx Answer #8271 : 2.1i COREGEN: Update Cores-> Custom appears to have all cores selected by default
Xilinx Answer #8261 : 2.1i COREGEN, VIRTEX, FFT, C_IP4: "WARNING: Core vfft16 did not generate product VerilogSim."
Xilinx Answer #8252 : 2.1i COREGEN, C_IP4, FFT: The Xilinx FFT cores do not support the Spartan-II architecture.
Xilinx Answer #8233 : 2.1i COREGEN, C_IP2: Virtex Variable Parallel Multiplier model shows only a 1-cycle latency in Verilog behavioral simulation
Xilinx Answer #8201 : 2.1i COREGEN: ERROR: "File com\xilinx\ip\<class name>.class not found in library <library name>"
Xilinx Answer #8177 : 2.1i COREGEN, C_IP4: Known Issues in the C_IP4 IP Update
Xilinx Answer #8171 : 2.1i COREGEN, LOGIBLOX: Where to find information on CORE Generator Virtex counterparts of 4K LogiBLOX modules
Xilinx Answer #8154 : 2.1i COREGEN: GUI for some Cores may hang when double-clicking the "Pins" or "Initial Contents" buttons
Xilinx Answer #8153 : 2.1i COREGEN, C_IP3: Synchronous INIT control does not work when "Restrict Count" option is selected for Virtex Binary Counter
Xilinx Answer #8151 : 2.1i COREGEN: Errors about components not being found when simulating myadder8_top.vhd example
Xilinx Answer #8068 : 2.1i COREGEN, 4K, Virtex: Dual Channel NCO outputs are identical in Verilog behavioral simulation
Xilinx Answer #8058 : 2.1i COREGEN, VERILOG-XL: "Error! `include file "XilinxCoreLib/xxxx.v not found"
Xilinx Answer #8028 : 2.1i COREGEN: Is there a Virtex version of the Single Port and Dual Port RAM modules in Coregen?
Xilinx Answer #8023 : 2.1i COREGEN: CoreLINX button in Coregen links you to the C_IP1 update instead of to the latest IP release
Xilinx Answer #8021 : 2.1i COREGEN (Japanese Version ONLY): "ERROR: Gui Field component_name not found"
Xilinx Answer #8015 : 2.1i COREGEN, SYNOPSYS VSS: How do I compile the Coregen Modules for VSS simulation?
Xilinx Answer #7996 : 2.1i COREGEN: Virtex-E support
Xilinx Answer #7973 : 2.1i COREGEN, MTI: "WARNING[1]:No default binding for component" messages when compiling VHDL designs containing Coregen modules
Xilinx Answer #7946 : 2.1i COREGEN, VANTAGE, VHDL: Error: Configuration "cfg_beh" cannot be created because the library already has a configuration with the same name. (util/LBR/58)
Xilinx Answer #7924 : 2.1i COREGEN, C_IP3, Distributed Memory: Customization GUI does not indicate what legal data width and depth ranges are
Xilinx Answer #7909 : 2.1i COREGEN: Incorrect data written to Virtex Block RAM in VHDL behavioral simulation / model has incorrect timing on address and data lines
Xilinx Answer #7908 : 2.1i COREGEN: Backspace/delete keys do not appear to work in module customization GUI text boxes on Solaris 5.6
Xilinx Answer #7897 : 2.1i COREGEN, C_IP3: Error in COUNTER HDL behavioral model when COUNT BY VARIABLE and COUNT TO VALUE = "MAX" are selected
Xilinx Answer #7896 : 2.1i COREGEN, C_IP3: Distributed Memory module only allows default initialization values of "0" using the MIF file
Xilinx Answer #7895 : 2.1i COREGEN, C_IP3: Known Issues in the C_IP3 IP Update
Xilinx Answer #7885 : 2.1i COREGEN: FOUNDATION: ERROR: \path\<project_name>.pdf does not exist or is not readable
Xilinx Answer #7867 : 2.1i COREGEN, BLOCK RAM: "Error:unable to open file for memory initialization: MIF file - binary error xx"
Xilinx Answer #7861 : 2.1i COREGEN: "ERROR: Duplicate core resource"
Xilinx Answer #7859 : 2.1i COREGEN VERILOG, VHDL: How to extract the CORE Generator Verilog and VHDL behavioral simulation models
Xilinx Answer #7817 : 2.1i COREGEN: "ERROR: Error locating library for class" after installing IP update
Xilinx Answer #7784 : 2.1i COREGEN USER GUIDE: Errata sheet
Xilinx Answer #7759 : 2.1i COREGEN, RAM, PC: CORE Generator does not respond / appears to hang when you try to generate/customize a module
Xilinx Answer #7711 : 2.1i COREGEN, C_IP2: "Shrink method not supported" or "ERROR: Could not load/define class file xxxxxx" / "ERROR locating library "
Xilinx Answer #7578 : 2.1i COREGEN, C_IP1, C_IP2, C_IP3: Version of generated module does not match version number in the corresponding datasheet
Xilinx Answer #7572 : 2.1i COREGEN, C_IP2: Incorrect latency values reported by Virtex Parallel Multiplier GUI
Xilinx Answer #7539 : 2.1i COREGEN: Missing MIF file for Virtex Single and Dual Port Block RAM modules
Xilinx Answer #7465 : 2.1i COREGEN: Recommended location of destination directory for compiled Verilog behavioral models
Xilinx Answer #7461 : 2.1i COREGEN, VIEWLOGIC: CORE Generator writes out Viewlogic symbol pins in reverse order for Coregen module
Xilinx Answer #7456 : 2.1i COREGEN: Text in .VEO and .VHO template files is merged into a single line when read in Windows Notepad
Xilinx Answer #7441 : V2.1i COREGEN, C_IP2: "ERROR: Unable to find library for core Sine-Cosine_Look-Up_Table|xilinx|xc4000_all"
Xilinx Answer #7433 : 2.1i COREGEN, ACTIVE-VHDL: Issues compiling the CORE Generator 2.1i VHDL models for the Active HDL simulator
Xilinx Answer #7409 : 2.1i COREGEN, FOUNDATION: Optional pins which are not requested still appear on the Foundation symbol for a CORE Generator Core
Xilinx Answer #7397 : C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier optional pins appear in a Foundation symbol even when not requested
Xilinx Answer #7396 : C_IP2, 2.1i COREGEN: Virtex Variable Parallel Multiplier "Combinatorial" and "Pipelined Registers" option interaction
Xilinx Answer #7395 : V2.1i COREGEN, C_IP2: Known Issues in the C_IP2 IP Update
Xilinx Answer #7393 : C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier module latency does not match the 4K (XC4000) version of the core
Xilinx Answer #7391 : C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier module "Set Overrides Clear" option behaves the same way as "Clear Overrides Set"
Xilinx Answer #7237 : V2.1i COREGEN, VIRTEX, FOUNDATION: Invalid EDIF with shorted nets produced for Virtex Dual & Single port Block memory on first iteration / Foundation simulator "duplicate net" errors
Xilinx Answer #7151 : 2.1i COREGEN, C_IP1, FOUNDATION: "Line: 3 Wrong number of fields BUS" on modules during symbol generation
Xilinx Answer #7149 : V2.1i COREGEN, C_IP1: Known Issues in the C_IP1 Cores update
Xilinx Answer #7148 : V2.1i COREGEN, VIRTEX: Problems with synchronous control signal (SCLR, SINIT) HDL behavioral modelling in the LD-Based LATCH module
Xilinx Answer #7143 : V2.1i COREGEN, VIEWLOGIC: "ERROR: cleanUpSymbolFile: Could not read symbol file: <project_directory>\sym\<modulename>.1"
Xilinx Answer #7128 : V2.1i COREGEN: Sine Cosine LUT module appears to be missing in CORE Generator tree
Xilinx Answer #7119 : V2.1i COREGEN, SYNPLICITY: CORE Generator does not write out a "/* synthesis black_box */ compiler directive to .VEO file for Synplicity Verilog designs
Xilinx Answer #6900 : V2.1i COREGEN, WVO VIEWDRAW v7.53: How to integrate CORE Generator v2.1i into the Workview Office ViewDraw menu
Xilinx Answer #6890 : 2.1i Foundation COREGEN: Coregen may not be able to locate the Foundation install directory on Windows
Xilinx Answer #6888 : V2.1i COREGEN, WINDOWS 95/98: COREGEN starts up with a DOS window which remains on the Windows desktop
Xilinx Answer #6868 : V2.1i COREGEN, UNIX: CORE Generator does not automatically load the coregen.prj file in its startup directory.
Xilinx Answer #6867 : V2.1i COREGEN: The name of every CORE Generator project file MUST be "coregen.prj"
Xilinx Answer #6866 : V2.1i COREGEN: Update Project Core : selecting and unselecting specifc cores to be updated is very slow
Xilinx Answer #6865 : V2.1i COREGEN: Response to double clicks to invoke module customization GUIs may be erratic and/or delayed.
Xilinx Answer #6861 : V2.1i COREGEN USER GUIDE, MTI, VHDL flow: 'Error xxxmyadder8.vhd(20): near "myadder8_top" expecting COMPONENT' in VHDL testbench example
Xilinx Answer #6831 : V2.1i COREGEN USER GUIDE, VERILOG: "Error! Module name previously declared" / Verilog parent design example is incorrect
Xilinx Answer #6830 : V2.1i COREGEN: How to remove a 2.1i CORE Generator project
Xilinx Answer #6829 : V2.1i COREGEN: How to get a copy of the 2.1i CORE Generator software
Xilinx Answer #6802 : Coregen 2.1: How do I obtain a description for each Coregen core created?
Xilinx Answer #6772 : V2.1i COREGEN, SYNOPSYS VSS, LEAPFROG VHDL: " **Error "OTHERS is not legal in this context as it is not the only element association AND the choice is not locally static"
Xilinx Answer #6771 : V2.1i COREGEN, VHDL: "**Error: Library logical name ARITHMETIC is not mapped to a host directory"
Xilinx Answer #6693 : 2.1i COREGEN USER GUIDE: Permissions for $XILINX/coregen/ip directory do not need to be 777.
Xilinx Answer #6611 : V2.1i COREGEN, VIEWLOGIC, POWERVIEW v6.1, VLLINK, UNIX, FUSION v1.4 : "ERROR: Viewlogic symbol generation failed.", "WARNING: Core xxx did not generate product ViewSym"
Xilinx Answer #6596 : 2.1i COREGEN, MTI, VERILOG: "WARNING[xx]: .../XilinxCoreLib/xxxx.v(xx): Redefinition of macro: true" (or TRUE, false, or FALSE) when analyzing COREGEN Verilog behavioral models
Xilinx Answer #6576 : V2.1i COREGEN, WINDOWS: Problems launching Web browser .exe executable from CORE Generator if Windows Explorer "Hide file extensions" Folder option is enabled (verify)
Xilinx Answer #6559 : V2.1i COREGEN: "ERROR: Could not locate specified browser /usr/local/bin/acroread" / Cannot launch Web browser & Acroread from COREGEN on HP
Xilinx Answer #6556 : V2.1i COREGEN, VERILOG, VHDL: New HDL behavioral simulation flow does not generate .VHD and .V models for simulation
Xilinx Answer #6547 : 2.1i COREGEN: COREGEN may lose all entries in listing of known projects except for the last project created in mult-user environment
Xilinx Answer #6527 : V2.1, V1.5i COREGEN, FOUNDATION: Virtex block RAM generated by CORE Generator does not simulate initial values properly in Foundation functional simulation
Xilinx Answer #6497 : 2.1i COREGEN: CORE Generator Web links may not use the Web browser specified during 2.1i installation
Xilinx Answer #6366 : V2.1i COREGEN, WINDOWS NT, 95, 98: Cannot start up Coregen on Windows NT-- application hangs after loading SizeRequirements.class
Xilinx Answer #6291 : V2.1i COREGEN: "Error creating log file coregen.log" / Location of coregen.log
Xilinx Answer #6290 : V2.1i COREGEN, ROM: COREGEN Registered ROM GUI complains too early about "No Coefficients specified" after input data width is changed.
Xilinx Answer #6250 : 2.1i COREGEN: Required order of analysis/compilation for CORE Generator VHDL and Verilog behavioral model libraries
Xilinx Answer #6242 : V2.1i COREGEN: Coregen may use CPU even when idle
Xilinx Answer #6231 : V2.1i COREGEN: Core names are case sensitive in xco and batch files.
Xilinx Answer #6190 : V2.1i, V1.5, V1.4 COREGEN: How to obtain the latest IP (COREs) for the CORE Generator
Xilinx Answer #6189 : V2.1i COREGEN: List of existing / known projects does not always appear in COREGEN GUI known projects list dropdown
Xilinx Answer #6187 : V2.1i COREGEN: What's new in the 2.1i release of the CORE Generator System (TM)
Xilinx Answer #6149 : V2.1i COREGEN: Coregen windows may not refresh or may simply hang on Windows NT if left running for extended periods of time (REL)
Xilinx Answer #6148 : V2.1i COREGEN, SOLARIS: Cannot bring up module customization GUI on Solaris 2.6/2.7 Openwin platform when window activation setting is set to "ClickMouse" to activate
Xilinx Answer #6116 : V2.1i COREGEN, HP: NullPointerException thrown after error dialog pops up on HP only (release notes)
Xilinx Answer #6082 : 2.1i COREGEN: How to install new CORE Generator IP updates / newly installed cores not visible
Xilinx Answer #6081 : 2.1i COREGEN: CORE Generator does not display installed cores until a valid project has been specified
Xilinx Answer #6073 : 2.1i COREGEN: COREGEN project path drop-down menu does not appear to be dismissed if you click outside of it
Xilinx Answer #6068 : 2.1i, V1.5 COREGEN, DATASHEETS: the CLB count is incorrect for a 16-bit wide loadable registered adder
Xilinx Answer #6039 : 2.1i COREGEN: A new Netscape session is launched when you click on Web links in COREGEN.
Xilinx Answer #6038 : 2.1i COREGEN: Netscape launched from COREGEN does not point to the correct page
Xilinx Answer #6037 : 2.1i COREGEN, MTI, VHDL: Required MTI commands for analyzing/compiling the CORE Generator VHDL models
Xilinx Answer #6020 : 2.1i COREGEN: Coregen may take a while to start up the first time.
Xilinx Answer #6019 : 2.1i COREGEN, MTI, VERILOG: MTI "xxxx already exists" compilation errors when analyzing CORE Generator Verilog behavioral models
Xilinx Answer #6018 : 2.1i COREGEN: Getting Started dialog does not always open up the right "last project"
Xilinx Answer #6017 : 2.1i COREGEN: Busy cursor goes away if Overwrite Files dialog pops up before elaboration of a module begins.
Xilinx Answer #6016 : 2.1i COREGEN: Projects accessible only to a local user may get displayed in the global Known Projects list. (REL)
Xilinx Answer #6012 : V2.1i COREGEN, C_IP2: Latency may be incorrect in Virtex Variable Multiplier VHDL behavioral model
Xilinx Answer #5907 : V2.1 COREGEN: Path entered in New Project GUI is not read in when you click on Browse button
Xilinx Answer #5899 : 2.1i COREGEN, SOLARIS 2.6: Project Choose Browser takes several minutes to browse to /home and other mount points on Solaris 2.6 (REL)
Xilinx Answer #5815 : 2.1i COREGEN: Coregen 2.1i displays all known projects for all users in the available projects listing in multi-user environment
Xilinx Answer #5083 : 2.1i, V1.5 INSTALL, COREGEN: " Your registry HKEY_LOCAL_MACHINE/SOFTWARE/JavaSoft/Java RuntimeEnvironment/1.1/javahome" messages and "JAVA was not found " or "Unsatisfied link" errors)
Xilinx Answer #4913 : 2.1i COREGEN: Sample COREGEN .COE coefficient files for a FIR filter, Distributed RAM, Distributed ROM, and Block RAM
Xilinx Answer #4631 : 2.1i, V1.5, V1.4 COREGEN, FOUNDATION: How to invoke NET2SYM in command line mode
Xilinx Answer #4427 : 2.1i, 1.5, 1.4 COREGEN: How the PDA FIR Filter module calculates its full precision output width.
Xilinx Answer #4270 : 2.1i, V1.5 COREGEN, JAVA: "NoclassDefFoundError: xilinx/widget/frame/PaneListener"
Xilinx Answer #4225 : 2.1i, V1.5, V1.4 COREGEN: "WARNING: Core 12x12_Multiplier (8x8_Multiplier) did not generate product VerilogSim"
Xilinx Answer #4220 : 2.1i COREGEN: "ERROR: SETPROJECT command failed"
Xilinx Answer #3884 : 2.1i, V1.5, V1.4 COREGEN:: versions of third party CAE platforms and M1 supported by COREGEN
Xilinx Answer #3883 : 2.1i, 1.5, V1.4 COREGEN: How to permanently set the default output format for COREGen
Xilinx Answer #3873 : 2.1i COREGEN, WORDPAD: "The document xxxx is in use by another application and cannot be accessed." / The CORE Generator does not release its "lock" on an XCO file
Xilinx Answer #3863 : 2.1i, V1.5, V1.4 COREGEN, FOUNDATION EXPRESS: How to generate Foundation functional simulation files for a VHDL design
Xilinx Answer #3791 : 2.1i, V1.5, V1.4 COREGEN: 4K Synchronous FIFO LogiCORE output is only valid when RE is enabled
Xilinx Answer #3673 : 2.1i, V1.5, V1.4.x COREGEN: Solaris Stopwatch "busy" cursor or Windows hourglass cursor lingers (seems to hang) after an operation is completed.
Xilinx Answer #3628 : V1.5, V1.4 COREGEN: Errors when loading spec sheets in Acrobat 2.1
Xilinx Answer #3627 : 2.1i, V1.5, V1.4 COREGEN GUI: Hourglass "busy" cursor lingers indefinitely until mouse is moved
Xilinx Answer #3493 : 2.1i, V1.5, V1.4 COREGEN, XC4000: Incorrect data on output of 4K PDA FIR and SDA FIR cores when maximum output width is not selected
Xilinx Answer #3399 : 2.1i, V1.5, V1.4 COREGEN: How to debug COREGEN hang and startup problems
Xilinx Answer #2695 : 2.1i COREGEN, NCO: "WARNING: ...XilinxCoreLib/ncovht.vhd(xx): Function get_factor may complete without a RETURN"