|
|
|
|
|
|
Xilinx Answer #8336 : INTERNAL_ERROR:NgdBuild:basnbsrch.c:327:1.1.2.6 "entity or component" is missing the TYPE property.
Xilinx Answer #8191 : 1.5i/2.1i Ngdbuild: Error : NGDBUILD 303 - <pathname> could not be written to. Please make sure you have adequate disk space and have write privledges.
Xilinx Answer #8107 : Mentor: NGDBuild gives: ERROR:NgdHelpers:312 - logical block "I$1563/I$1/I$32" of type "vcc!1" is unexpanded (or "gnd!1")
Xilinx Answer #8086 : NGDBUILD, EXEMPLAR, SYNPLICITY: Error ngdhelpers 634: Port ".." is specified. There is no pad allocated to this signal
Xilinx Answer #8065 : COREGEN: How to generate a VERILOG or VHDL post-NGDBUILD gate level simulation netlist from a standalone EDIF netlist
Xilinx Answer #8057 : Warning: Ngdhelpers 312: Logical block U## of type <Macro_name> is unexpanded. or ngdbuild 76
Xilinx Answer #8017 : Synopsys Compiler, NGDBuild: A port list construct was found in .... EDIF file, this is not supported. Try enabling bus expansion.
Xilinx Answer #7860 : Virtex-E NGDbuild error on LVPECL and LVCMOS18 IOSTANDRD: ERROR:NgdHelpers:33 - Invalid UCF/NCF file entry value "LVCMOS1" ...
Xilinx Answer #7031 : ngdbuild 1.5isp2, 2.1i: basnb:79, basnu:93, basnu:115, Ngdhelper:312, Ngdhelper:335, Ngdbuild:79
Xilinx Answer #7030 : NGDBUILD does not process all XNF files before it reads NCF file (NgdHelpers:14)
Xilinx Answer #6782 : NGDBUILD netlist priority: What's the searching order NGDBUILD uses to merge hierarchical modules into a .ngd file
Xilinx Answer #6654 : M1.5is2/NGDBUILD: ERROR:basnu:93 - logical block "<blockname>" of type "f402" is unexpanded
Xilinx Answer #6474 : NGDBUILD: Error:basnu:138 - output pad net has multiple drivers
Xilinx Answer #6435 : ngdbuild: BUFE or BUFT cannot drive an OPAD directly for Virtex. ERROR xvkpu - The symbol page1$4p/i5 failed to join a regular I/O component as required. Buffer is not an I/O buffer.
Xilinx Answer #6406 : ngdbuild Virtex designs: ERROR:basnu:118 - logical net "xxxx" has both a pullup and a pulldown.
Xilinx Answer #6402 : Virtex ngdbuild: ERROR:NgdHelpers:664 - Period specification "TS_clkdv" references the TNM group "clkdv", which contains only pad elements
Xilinx Answer #6307 : NGDBuild WARNING:basnu:159 - Attribute "TNM_NET" on "CLK" is on the wrong type of object. Please see...
Xilinx Answer #6301 : ngdbuild: ngdbuild does not error with conflicting LOCs
Xilinx Answer #6034 : Virtex designs running ngdbuild: ERROR:NgdHelpers:342 - input pad net "xxxx" drives multiple buffers
Xilinx Answer #5788 : NGDBUILD: ERROR:based:58 - On or above line 890 in file "repic.edf" with Synplify netlist
Xilinx Answer #5576 : M1.5i - Ngdbuild : ERROR:basnu:192 - The LUT2_L symbol ... does not have any programming information
Xilinx Answer #5494 : M1.5i NGDbuild - ERROR:basnb:79 - File cannot be merged into block
Xilinx Answer #5477 : F1.5i NGDBUILD: ERROR:basnu:93 - logical block "<instance_name>" of type "OBUFN_S" is unexpanded
Xilinx Answer #5440 : Mentor/NGDBuild warning:basnu:159-Attribute TNM_NET on "CLK" is on the wrong type of object
Xilinx Answer #5399 : ngdbuild M1.5i: WARNING:basnu:159 - Attribute "LOC" on "tx1a_dup0" is on the wrong type of object.
Xilinx Answer #5387 : NGDBUILD: "logical block ' ' of type 'READBACK' is unexpanded" with a Exemplar netlist
Xilinx Answer #5085 : M1.5 DC2NCF: TNM attribute created from DC2NCF causes warnings in NGDBUILD
Xilinx Answer #5054 : ngdbuild: ERROR:bascp:94 - Invalid UCF/NCF file entry value "" detected on line 4, offset 64,
Xilinx Answer #5050 : LogiCORE PCI32 4000/Spartan (v2.0.x): NGDBUILD errors out on a LOC constraint on INTA_0 net
Xilinx Answer #4983 : Foundation F1.5: ngdbuild/Virtex: basnu:93 -logical block "<name>" of type "GND" is unexpanded
Xilinx Answer #4891 : NGDBUILD 1.4: "ERROR:basnb:79 - Pin mismatch between block ..." with Synplify 5.x
Xilinx Answer #4833 : NGDBuild - ERROR:basla:106 - failed to launch program e, ERROR:basnb:48 - top leven input design file cannot be created
Xilinx Answer #4811 : ngdbuild: ERROR:basnu:93 logical block of type RAM16X1D is unexpanded ( unexpanded primitives)
Xilinx Answer #4799 : F1.5 / FPGA Express 2.1.2 : illegal connection on instantiated BUFG gives NGDBUILD error 142
Xilinx Answer #4774 : NGDBUILD M1.5: ERROR: based: 6 - On or above line <line> in file <file>...
Xilinx Answer #4751 : ngdbuild: FATAL_ERROR:basut:basutptrfil.c:66:1.4 - Pointer already registered.
Xilinx Answer #4711 : M1.5 LOGIBLOX, NGDBUILD, SPARTAN, SPARTANXL: "ERROR:basnu:173 - The WAND symbol "../WANDxx" is not supported in the spartanxl architecture." LogiBLOX infers wired-ANDs for Spartan-XL Comparat or & RAM
Xilinx Answer #4517 : ngdbuild : basnu:93, unexpanded logical block.
Xilinx Answer #4442 : M1.4 NGDBUILD: ERROR:bascc:64 - decoder symbol 'i_8': Missing "CONFIG" property on LogiBLOX and COREGEN modules.
Xilinx Answer #4341 : M1 NGDBUILD: ERROR:basnb:79 (pin mismatch) and ERROR:basnu:93 (unexpanded) on Synopsys Design Compiler design with instantiated Coregen or Logiblox modules.
Xilinx Answer #4321 : Synopsys, M1.4 ngdbuild : WARNING:basxn:70 - 870 obsolete timing specification(s) was/were found:
Xilinx Answer #4182 : M1.4/M1.5: ngdbuild/map:INCDEC-G-0 (cy4_34) is instantiated, got error on INCDEC-G-CI
Xilinx Answer #4089 : How to simulate Exemplar written VHDL in MTI or QuickHDL. Post synthesis pre NGDBuild
Xilinx Answer #4065 : M1.5: NGDBUILD/CSTTRANS: Why INST can sometimes be used instead on NET for Pad LOCs
Xilinx Answer #4041 : V1.5.x COREGEN, NGDBUILD, (VIRTEX BLOCK RAM): "ERROR: BASNB Pin mismatch". COREGEN does not allow you to select the netlist bus delimiter format if one of your selections is VHDL or Verilog I nstantiation Template.
Xilinx Answer #3941 : NGDBUILD 1.4/1.5: basnb: 79- Pin mismatch with FPGA Express XNF instantiated in Foundation schematic
Xilinx Answer #3898 : M1, ngdbuild, Error: basnu:94 - logical root block ... of type ... is unexpanded.
Xilinx Answer #3825 : M1 NGDBUILD error based51: on or above line ... in design.edf, using Mentor flow
Xilinx Answer #3611 : NGDBUILD: "logical block" of type 'DFFRSE' is unexpanded with a Synplify netlist
Xilinx Answer #3595 : NGDBUILD: "logical block ' ' of type 'READBACK' is unexpanded" with a Synplify netlist
Xilinx Answer #3513 : M1.5i/2.1i: NGDBUILD: invalid NCF/UCF file entry value "~" detected on line ##.
Xilinx Answer #3444 : NGDBUILD: Could not find NET " " in design " " with Cadence Concept design
Xilinx Answer #3410 : Design Mangager/ngdbuild M1.4: Application error/Invalid Page Fault in module mfc40.dll
Xilinx Answer #3324 : NGDBUILD/MAP 1.5i/2.1i: "Unexpanded block" warnings/errors with design from a third party entry tool (e.g. Orcad, Protel, Synario) (basnu:93).
Xilinx Answer #3291 : F1.5, NGDBUILD: FATAL_ERROR:basnb:basnbctxt.c:140:1.14.1.2 - design 'ROOT' has invalid CAE_VENDOR property 'metamor'
Xilinx Answer #3276 : Foundation F1.x Schematic, NGDBUILD: ERROR: basnu - logical net "net_name_int" has both active and tristate drivers
Xilinx Answer #3256 : M1.5i/2.1i: NGDBUILD: OFFSET constraint gives "ERROR:basts:69 - NET CLK ... is not a pad-related net"
Xilinx Answer #3233 : Viewlogic: Aurora Synthesis 7.4 produces global GND and VDD instances in schematics; NGDBUILD fails
Xilinx Answer #3155 : Ngdbuild: ERROR:basnu-The signal "GSR" in block "<component>" uses a Xilinx reserved global signal name
Xilinx Answer #3145 : Foundation XVHDL, NGDBuild: Warning:basnu-The input pad net "<nonclk signal>" is driving one or more clock loads, but is not using a dedicated clock buffer
Xilinx Answer #3144 : Exemplar/M1 NGDBUILD: ERROR:basnb:79 (pin mismatch) and ERROR:basnu:93 (unexpanded) design with instantiated modules
Xilinx Answer #3027 : XABEL6, Foundation F1.x, NGDBUILD: Warning- logical net VCC_net (or GND_net) has no load
Xilinx Answer #3011 : M1.5i/2.1i: NGDBUILD: UCF constraint on element with special char. gives "ERROR:baspr - SSLex0105e: Invalid token"
Xilinx Answer #2964 : m1.x ngdbuild. ERROR basut - Problem parsing '_'.
Xilinx Answer #2950 : Design Manager/Ngdbuild M1: Can't find files accross Novell network
Xilinx Answer #2938 : A1.4/A1.5: logical block reported as 'unexpanded' by ngdbuild
Xilinx Answer #2933 : NGDBUILD: ERROR:basnb - SECURITY ERROR -- Unable to lock license for ngdbuild: No such feature exists (-5,116:2) No such file or directory.
Xilinx Answer #2912 : M1.3/M1.4 NGDBUILD: ERROR:basxn:68 - The XNF file does not contain a valid PART
Xilinx Answer #2911 : NGDBUILD M1.4: DC2NCF is not invoked automatically for .sedif and .sxnf files
Xilinx Answer #2870 : M1.4/M1.3 NGDBUILD, FOUNDATION. M1.4 COREGEN: ERRORS: basnu - logical net...has multiple drivers, illegal connection, no legal driver, no driver...
Xilinx Answer #2864 : M1.4, 1.3 LogiBLOX, NGDBUILD/MAP: Warning/Error:basnu - logical block "<instance_name>" of type "<logiblox_module>" is unexpanded
Xilinx Answer #2781 : M1 NGDBUILD: ERROR:bascp:69 and/or WARNING:basts:19 on Mentor TIMEGRPs
Xilinx Answer #2749 : M1 ngdbuild error: ngdbuild.exe -entrypoint not found
Xilinx Answer #2619 : M1.37 ngdbuild - ERROR:bascp - Could not find NET 'NET entry is '%s'
Xilinx Answer #2593 : Foundation XVHDL, NGDBUILD: ERROR: basnu - logical net "net_name_int" has both active and tristate drivers
Xilinx Answer #2331 : M1 NGDBUILD: ERROR:basts:68 - NET...which has a NET OFFSET...not pad-related...
Xilinx Answer #2268 : Concept2xil causes NGDBUILD to issue "ERROR:based:48-..Duplicate port a in cell "alias_bit".
Xilinx Answer #2264 : NGDBUILD: Launcher: NOT compiling module.ngo because its source was not found
Xilinx Answer #2256 : NGDBUILD: WARNING:basnu:11 - Ignoring unexpected data value "true" on "FAST" property
Xilinx Answer #2240 : M1.5/M1.4/M1.3 LOGIBLOX: LogiBLOX warnings are not indicated in NGDBUILD summary
Xilinx Answer #2234 : M1.5, M1.4 MAP/NGDBUILD, LogiBLOX: Pin mismatch between block ... at pin ....
Xilinx Answer #2181 : M1: ERROR: basnb - SECURITY ERROR -- Unable to lock license for ngdbuild: Cannot find license file (-1,73:2) No such file or directory
Xilinx Answer #2099 : M1: NGDBUILD fails with Multiple Driver errors. EDIFNETO option missing
Xilinx Answer #1983 : NGDBUILD M1.1.1a: Invalid UCF/NCF file entry value detected while searching for PART
Xilinx Answer #1982 : ngdbuild m1.1.1a: Prohibit pin locations in ucf file.
Xilinx Answer #1916 : NGDBUILD m1.1.1a: error 0:Unable to lock license for ngdbuild, no such feature exists.
Xilinx Answer #1900 : NGDBUILD (csttrans) M1.1.1A: ERROR:0 - Could not find INST(S) <signal name> in design
Xilinx Answer #1883 : M1: ERROR:basnb - SECURITY ERROR --Unable to lock license for ngdbuild: license file syntax (-2,134:2) No such file or directory