LogiCORE PCI64 Virtex - Top Solutions LogiCORE PCI64 Interface Solution 3549: BAse Address Register Attributes Solution 3762: What is the functionality of the latency timer? Solution 4835: Does the PCI interface support multi-function capability? Solution 4855: How does the LogiCORE PCI interface handle wait states between data phases? Solution 4856: How does the LogiCORE PCI Target interface behave when the first data phase requires more than 16 clocks? Solution 5094: Information about Zero and One wait states Solution 5125: Can the I/O space in the PCI core be set to greater than 256 bytes? Solution 5128: When is the S_WRDN signal in the PCI core valid? Solution 5159: Is snooping supported by the LogiCORE interface? Solution 5160: How many Base Address Registers does the PCI interface support? Solution 5193: How does the PCI interface handle Master Aborts? Solution 5202: How does the PCI interface handle Single Cycle Grants? Solution 5214: Does the LogiCORE interface support interrupts? Solution 5227: How does the LogiCORE interface handle target abort? Solution 5229: How do the REQ#/GNT#/RST# lines in the LogiCORE interface behave? Solution 5239: Can the 64-bit PCI Interface support 32-bit applications? Solution 5441: Which addressing mode is supported by the PCI interface during Memory Burst Addressing mode? Solution 5760: Is the user free to use any BAR desired, for I/O or Memory space? Solution 7152: Information about plugging a 64-bit card in a 32-bit slot Solution 7300: Inserting Initial Latency in a Target Design Solution 7413: LogiCORE PCI master may stop bursting data after 2 clocks during simulation LogiCORE PCI Devices Solution 5246: Supported Device/Package/Speed grades Solution 5253: Device resource utilization summary Solution 7108: Are the Virtex devices PCI compliant? LogiCORE PCI Virtex Design Flows Solution 5247: Xilinx Software & Synthesis tools support Solution 5991: Is timing simulation supported for the LogiOCRE PCI Virtex? Solution 6696: All signals designated s/t/s in the PCI spec must be pulled-up during simulation Xilinx Implementation Software Solution 5055: Guide does not work if M/S_SRC_EN signals are unused Solution 5171: 0.7 or 0.75 multiplication factor in the UCF files Solution 5705: Can the top level hierarchy be modified in a Xilinx PCI design? Miscellaneous Solution 3543: Why can't an I/O Base Address Register be set to > 256 bytes for a x86 processor based system? Solution 3552: PCI Power Management: Description of function power states Solution 5126: How much time would a FPGA on a PCI bus have for configuration? Solution 5261: Implementing CompactPCI HotSwap with Xilinx LogiCORE PCI solution Solution 5299: What loads should be used when calculating the maximum clock-to-out timing per the PCI spec? Solution 7176: Base Address Registers (BAR)s and Configuration Accesses in a PCI system LogiCORE PCI64 Documentation Solution 5127: Key to various states depicted in the waveforms in the LogiCORE PCI64 user guide Solution 5926: What is the correct way to drive S_TERM and S_READY?