Virtex: Tips and Techniques To access our full database of Xilinx Solutions, please consult our Answers Search.  Virtex Software Implementation Tools Virtex Hardware and Configuration

Software Implementation tools

Ngdbuild



• Solution 7860 - Virtex-E LVPECL, LVCMOS NGDbuild: ERROR:NgdHelpers:33 - Invalid UCF/NCF file entry value "LVCMOS1" detected on line 1, offset 27.
• Solution 5054 - ngdbuild: ERROR:bascp:94 - Invalid UCF/NCF file entry value "" detected on line 4, offset 64.
• Solution 7071 - 2.1i Ngdbuild- ngdbuild ignoring drive strength constraints attached to output nets.

Map



• Solution 8046 - 2.1i VirtexE Map - Map does not make use of the fastdll feedback path between DLLIOBs and Secondary DLLs.
• Solution 6572 - 2.1i Virtex Map - Device utilization appears to increase because of new default packing rules.
• Solution 6793 - 2.1i Virtex MAP - Map will not put two unconstrained SRL16s into a single Virtex slice.
• Solution 6624 - 2.1i Virtex Map - Map errors atttibuted to incorrect CLKDLL usage (ERROR:xvkmm:12 and ERROR:xvkmm:16).
• Solution 7290 - 2.1i Virtex Map - IOB=true attribute is ingored for tri-state enable register in Virtex.

Par



• Solution 7025 - 2.1i Virtex PAR - ERROR:Place:1631, 1632 Could not find a legal placement for the following components....
• Solution 7243 - 2.1i Virtex Map/PAR - Map and PAR issues related to Virtex Carry chains.
• Solution 8259 - 2.1i VirtexE PAR - ERROR:Place:1670 - The IOB component has an IO standard of LVDS which must be placed with locate constraints to specific IOB locations that support.



Ngdanno



• Solution 6665 - 2.1i Ngdanno: ngdanno leaves BlockRam's inputs unconnected if they are driven by more than one power/ground or constant signals.



Ngd2vhdl, Ngd2ver, and simulation


• Solution 6362 - Virtex HDL simulation: LOCKED signal doesn?t lock if it?s not in ps time resolution.
• Solution 5995 - Virtex clkdll: How to simulate CLKDV_DIVIDE in pre-synthesis functional simulation.
• Solution 7792 - Virtex CLKDLL timing simulation in MTI: WARNING[1]:No default binding for component : "x_clkdll". ( Generic "tperiod_clkin" is not on the entity).
• Solution 7174 - Foundation 2.1i: Functional and timing simulation of the CLKDLL.
• Solution 8263 - Virtex CLKDLL VHDL simulation: DLL outputs are not toggling (No output) CLKIN is delayed.
• Solution 648 - VERILOG-XL: Buffer output does not follow transitions on its input (transport and inertial delays).
• Solution 7816 - Virtex CLKDLL: If 2 CLKDLLs are cascaded together with the Lock signal driving the RST of the second CLKD.

Trce



• Solution 6449 - 2.1i: TRCE/Timing Analyser: Skew not automatically accounted for on Virtex low skew clocks.
• Solution 8313 - 2.1i sp4 Trce/Timing analyzer : Trace giving different timing results than the Timing Analyzer.
• Solution 6448 - 2.1i: TRCE/Timing Analyzer does not provide the ability to constrain the blockram halves separately.

Bitgen



• Solution 7706 - Bitgen M1/M2: Why is there no -t (tie down unused interconnect) or -n (write out tied ncd) for Virtex?
• Solution 7852 - Virtex CLKDLL: How to make sure the DONE does not go high until the CLKDLL has been locked.

Virtex Hardware and Configuration

Hardware



• Solution 8006 - Virtex-E CLKDLL: What are the input clock frequency range for VirtexE CLKDLLs to be locked.
• Solution 7880 - Virtex-E: Are the Virtex-E I/O pins 5V compatible?
• Solution 6902 - Virtex SSO: how did we come up with the power/ground pairs in the Select IO application notes.
• Solution 7821 - Virtex SSO: The power/ground pair numbers for various Virtex devices and packages.
• Solution 7402 - Virtex CLKDLL: Will the CLKDLL lock if the input frequency is below 25Mhz, if not, what would the outputs of the CLKDLL be like.
• Solution 8383 - Virtex: Can Virtex Inputs be driven by input voltages lower that -500mV?
• Solution 7034 - Virtex: Is it possible to remove Vccint whilst applying Vcco?
• Solution 8354 - Virtex: Virtex has the potential race condition that can occur during the STARTUP.
• Solution 6670 - Virtex: What happens to the I/O pins of the Virtex device during power ramp up.
• Solution 7843 - Virtex: How to pull the IOs to 5V with external Pullups.
• Solution 6971 - Virtex: Virtex devices have potential high current draw for the engineering samples.
• Solution 4709 - Virtex JTAG - Dedicated JTAG Pins do not need external pullups.



Configuration



• Virtex Configuration FAQ.
• xapp138: Virtex Configuration and Readback.
• xapp139: Virtex Configuration and Readback through Boundary Scan



• Solution 5381 - Virtex Configuration: Issues on configuring Virtex and 4000X devices in daisy chain.
• Solution 5666 - Virtex Configuration: Configuring Multiple Virtex Devices in SelectMAP mode.
• Solution 5865 - Virtex Configuration: Done goes High, but device does not startup.
• Solution 5368 - Virtex Configuration: what valid configuration speeds are available for virtex?
• Solution 5108 - Virtex Configuration: What is the status of user I/O during configuration?
• Solution 6484 - Virtex Configuration: Can CRC be disabled.
• Solution 5662 - Virtex: How to program/configure a single Virtex device via JTAG with debugging options.
• Solution 5718 - Virtex: How to program multiple Virtex devices in a JTAG daisy chain.
• Solution 7172 - Virtex JTAG - How to perform a Readback Verify on the Virtex devices?
• Solution 8149 - Virtex JTAG - Xapp139 has a misprint on shutdown sequence for AGHIGH command.