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Xilinx Answer #7856 : Viewlogic VHDL simulation:How to simulate Xilinx Virtex primitives (e.g. ramb4_s4)
Xilinx Answer #6350 : VCS: Error: undefined system task or function $sdf_annotate
Xilinx Answer #6349 : VCS: How to back annotate the SDF file for timing simulation?
Xilinx Answer #6330 : VCS: How to compile the 2.1i Simprim, LogiBLOX, Unisim, and Coregen HDL libraries?
Xilinx Answer #5968 : 2.1i: Virtex schematic library for Viewlogic that supports Functional Simulation in Viewsim
Xilinx Answer #5263 : VCS: Running simulation
Xilinx Answer #5251 : VCS: Assertion failed "qop & arg1->pe.real & 0" at line 583 in file eval.c
Xilinx Answer #4964 : How to use Viewlogic Workview Office 7.5 with Foundation F1.5/F2,1i
Xilinx Answer #4649 : POWERVIEW 6.1 : Primitive symbols (AND2, OR2, etc) appear as empty box in schematics
Xilinx Answer #4611 : VCS: time_sim.sdf:2901, SDF Error: Cannot find timing check (accSetup) in type X_FF,
Xilinx Answer #4472 : Workview Office, Viewdraw: How to change color settings in Viewdraw
Xilinx Answer #4316 : V1.5, V1.4 COREGEN, VIEWLOGIC SPEEDWAVE, ACTIVE-VHDL, SUMMIT, VHDL-93 support: COREGEN Sync FIFO FULL and EMPTY outputs stuck high on VHDL-93 simulators
Xilinx Answer #3847 : WVO7.4, M1.4, 5200:ERROR: baste:266-An extension is required on the "RLOC" parameter for CY_MUX/FDCE
Xilinx Answer #3827 : Workview Office EDIFNETO: Error opening project from ygraflib
Xilinx Answer #3622 : Workview Office: Required License file not found (Errror 8030)
Xilinx Answer #3523 : V1.5, V1.4 COREGEN: Required license features for Viewlogic Viewdraw interface executables used by COREGen v1.4.0 (EDIFNETI, EDIFNETO, VHDL2SYM)
Xilinx Answer #3512 : Viewlogic: Inverted signals (with tilde, ~) can be used with M1
Xilinx Answer #3494 : Workview Office 7.4: Tutorial in "Getting Started" guide will not work with Xilinx license
Xilinx Answer #3490 : Workview Office: Calc tutorial needs newer commmand (.CMD) files
Xilinx Answer #3401 : Workview Office 7.4, Windows NT: Path to LogiBLOX under tools menu is incorrect
Xilinx Answer #3320 : ViewSim - "Error: Could not find memory component U1" when loading XMM file
Xilinx Answer #3303 : Workview Office 7.31, 7.4, 7.5: Initialization Error written to viewdraw.err while starting ViewDraw
Xilinx Answer #3109 : Viewlogic: ViewDraw 7.31 is missing BAF2VL.EXE, cannot run XREF
Xilinx Answer #3081 : Workview Office 7.4, Powerview 6.1 EDIFNETI: viewbase error 413: Pin not on symbol error
Xilinx Answer #3080 : M1.3/M1.4: Viewlogic board level simulation methodology
Xilinx Answer #2995 : Workview Office 7.31: Cannot open Project Manager.
Xilinx Answer #2947 : VIEWLOGIC: Converting pre-Unified library schematic designs to Unified libraries
Xilinx Answer #2926 : ViewSim and M1.2: Loading func_sim.xmm gives error that none of the RAM instances are found.
Xilinx Answer #2923 : Powerview 6.0, Edif Netlist Reader V2.3: BNF Parser Error Internal stack overflow
Xilinx Answer #2922 : Workview Office 7.3x: The symbol wizard in viewdraw gives a Dr. Watson vsec: Error 8002(vseccode.vmb)
Xilinx Answer #2883 : Viewlogic Pre-Unified Libraries (hm4000, mx3000, mx4000) available on the WEB/FTP site
Xilinx Answer #2880 : WorkView Office: Viewdraw error vipc -e -1347 unable to connect to vnsd and vipc init()
Xilinx Answer #2877 : Viewsim/Viewtrace: vector is specified in command file and wfm statement but shows up as XXXX in Viewtrace
Xilinx Answer #2874 : XACTstep wir2xnf 5.2.1 may fail with WIR files created by Powerview 6.1
Xilinx Answer #2853 : M1.x, Powerview, How to create logiblox symbols in powerview6.x
Xilinx Answer #2842 : Workview Office: License platform restriction errors (1055, 8031, 8052)
Xilinx Answer #2721 : Workview Office 7.31: ViewDraw not installed; license-based installer does not work
Xilinx Answer #2699 : Workview Office: How to install Sentinel driver for Windows NT 4.0 (error 8037)
Xilinx Answer #2689 : ViewSynthesis: Flow for black box instantiation
Xilinx Answer #2688 : M1, ViewSynthesis: Bus Naming and Post-place-and-route Bus Reconstruction
Xilinx Answer #2687 : M1, ViewSynthesis: Analyzing Simprims and Unified libraries with SpeedWave
Xilinx Answer #2686 : M1, ViewSynthesis: SpeedWave may have difficulty analyzing large models
Xilinx Answer #2646 : Workview Office: VSM Error 222. Could not find wir file XC9000 AND2B1.1
Xilinx Answer #2536 : M1.2, Workview Office: EDIFNETI reports unconnected ports reading TIME_SIM.EDN
Xilinx Answer #2531 : Workview Office Viewdraw: "file is locked" while editing schematic.
Xilinx Answer #2511 : Workview Office: How to label incrementing/decrementing bus signals
Xilinx Answer #2431 : M1: Powerview/Viewdraw->"vscript: Error 4307: logiblox.vs: Unbound variable-RequireFac"
Xilinx Answer #2095 : Workview Office: Viewsynthesis support is available for XC9500 family.
Xilinx Answer #2076 : Problem with pin mismatch, macro in Workview Office, xnf from Synplicity or FPGA Express
Xilinx Answer #2075 : Viewsynthesis: How to disable automatic XBLOX insertion
Xilinx Answer #2060 : Workview Office: Project Manager issues "unexpected file format" and "invalid page fault"
Xilinx Answer #2046 : Bad Workview Office 7.2 CDs have been sent out by Xilinx
Xilinx Answer #1985 : M1.3/M1.4/M1.5/A2.1i ,Workview Office : Adding custom functions to ViewDraw (EDIFNETO/EDIFNETI/LogiBLOX)
Xilinx Answer #1967 : Viewsynthesis: PULLUP/PULLDOWN instantiation
Xilinx Answer #1966 : Viewsynthesis: BSCAN and Mode pin instantiation
Xilinx Answer #1959 : Prowave: Can't load .wfm file into Prowave
Xilinx Answer #1924 : Prowave: Sharing violation error
Xilinx Answer #1921 : PROsim: Out of Memory when loading a VSM file
Xilinx Answer #1902 : Check issues warnings on ASHEETP, ASHEETL, BSHEETL, etc
Xilinx Answer #1893 : M1/A2.1i, Workview Office: Viewlogic library description file (LIBS.LST) for Workview Office/M1
Xilinx Answer #1729 : Workview Office: Error 8031: Flex/LM Error: Cannot find license file[-1,73:2]
Xilinx Answer #1710 : XNF2WIR Error 13: Unsupported XNF netlist version '6'.
Xilinx Answer #1643 : WIR2XNF 5.2.x: Check program failed, symbol for ___ is newer than WIR file
Xilinx Answer #1630 : How to manually edit a prowave waveform
Xilinx Answer #1622 : Xaltran: How to install and use with Workview Office.
Xilinx Answer #1606 : Viewsynthesis: Unexpected Heap Error 6000
Xilinx Answer #1590 : Viewsynthesis - vhdl error: the name "pfalling"/"prising" is undefined
Xilinx Answer #1559 : "error #83 buffer too small" is given when starting PROcapture
Xilinx Answer #1550 : PROsim: Simulation with OSC4.1: could not find WIR file xc4000:osc4.1
Xilinx Answer #1546 : WIR2XNF ERROR: SEC: HOST is not in the HOSTS file. ERROR 4: IWINIT Failure.
Xilinx Answer #1531 : Viewsim: vsec error 1026 Required license not found for product Viewsim
Xilinx Answer #1504 : **XACT-CPLD: Need two Project.lst files if using both XACT and XACT-CPLD and PROflow
Xilinx Answer #1493 : PROFlow 3.0: About "PSFM !No resume"
Xilinx Answer #1482 : Workview Office: Viewsynthesis SML semantic errors during synthesis: %PIN_LOAD
Xilinx Answer #1451 : How to run Viewsynthesis from DOS
Xilinx Answer #1447 : xnf2wir/xsimmake: General Protection Fault on Windows95.
Xilinx Answer #1445 : Viewsynthesis: STARTUP instantiation
Xilinx Answer #1444 : Workview Office gives "Error" but no error message. (WVOinstall info)
Xilinx Answer #1440 : PROCapture 6.1: Can I print entire design and change fonts before printing?
Xilinx Answer #1429 : Workview Office: What Workview Office products should I install for a Xilinx restricted license? (OEM1/OEM2)
Xilinx Answer #1411 : OSC4.vli is not included in the XC4000E unified library.
Xilinx Answer #1394 : Workview Office: License exclusive restriction errors (1055, 8031, 8051)
Xilinx Answer #1389 : Xsimmake, Workview Office: Using Workview Office 7.1.2 or 7.2 with XACTstep 6.0.1 (Xsimmake failed)
Xilinx Answer #1381 : Workview Office: use VCD format with ViewTrace; fixes bad clock pulses in simulation
Xilinx Answer #1360 : Error message when running XACT 6.0 on a network when translating
Xilinx Answer #1334 : ProCapture displays CB4CLED.1 symbol pins 'D0' and 'Q0' as diagonals
Xilinx Answer #1315 : XDRAW/Xsimmake: Invalid KeyWord 'WINDOW_BACKGROUND'
Xilinx Answer #1295 : BIDIRectional IOs with Viewsynthesis
Xilinx Answer #1283 : Viewsynthesis: Symbol precompiled_xc3000:FDPE cannot be found
Xilinx Answer #1273 : Check, Procapture, viewdraw: Schematic components cannot be found.
Xilinx Answer #1264 : PROcapture: "Pin/Net disassociation at location ..."
Xilinx Answer #1253 : Viewlogic: How do I LOC an IPAD4/8/16 or an OPAD4/8/16 ?
Xilinx Answer #1247 : patch for Flex/LM errors with xsimmake/check in Workview Office 7.2 (Error 8034)
Xilinx Answer #1244 : PROsim or ViewSim: Outputs of ROM primitives are 'x' (indeterminant state).
Xilinx Answer #1225 : How to re-target a different Xilinx device family with Viewlogic's Altran
Xilinx Answer #1217 : Viewsim: backannotation from Viewsim/Viewtrace to Viewdraw doesn't work
Xilinx Answer #1210 : Possible cause of XNFPREP 3527 :"Pad connected to invalid symbol pins"
Xilinx Answer #1203 : 5200 VL libs : FJKRSE or FJKSRE does not function properly
Xilinx Answer #1193 : WIR2XNF:Error-V (version) statement not unique, out of order or missing
Xilinx Answer #1186 : XNF2WIR ERROR 217: The logical function of <component> and its Viewlogic model do not match.
Xilinx Answer #1183 : Proflow : Project Verification Error
Xilinx Answer #1182 : procapture dos error #75 occurred: access denied...
Xilinx Answer #1181 : Proflow : DOS error #53 : Can't open file.
Xilinx Answer #1161 : Workview Office, PCI v1.1: Simulation fails if using unit delays only.
Xilinx Answer #1139 : Workview Office 7.1.2 is the only version that is compatible with Windows 3.11
Xilinx Answer #1135 : PROsim error: Could not find wir file xc5200:osc52.1
Xilinx Answer #1124 : Viewlogic: Do NOT use $ARRAY in Xilinx designs
Xilinx Answer #1102 : How to use PROflow with the 4000e family.
Xilinx Answer #1091 : VCS: Error: undefined hierarchical reference "glbl.GSR" (<design>.v line ####)
Xilinx Answer #1075 : wir2xnf gives error 4 when using Powerview 6.0 (iwinit failure), need lsclient daemon
Xilinx Answer #1062 : Procapture: SECURITY no valid license for product: ProSeries
Xilinx Answer #1037 : ProCapture will not open up when selecting Design Entry from Proflow
Xilinx Answer #1012 : WVOffice: while printing a project, the printouts are fuzzy
Xilinx Answer #1005 : When items are selected in Procapture, selected color is the opposite color.
Xilinx Answer #973 : How to specify a BUFGP vs. BUFGS using Viewsynthesis?
Xilinx Answer #970 : Defining pin attributes/locations for a VHDL code using Viewsynthesis
Xilinx Answer #922 : WIR2XNF error: could not find WIR file for a user-created component
Xilinx Answer #897 : ProCapture Error when printing : vlwp Metafile does not exist
Xilinx Answer #881 : Specifying an FDCE in VIEWsynthesis
Xilinx Answer #875 : VSMUPD: vsec: Error 8037: License node restriction does not match client's node for product ViewBASE
Xilinx Answer #872 : Workview: Viewdraw gives Pharlap error 33 when plotting
Xilinx Answer #867 : Proflow changes the Viewdraw.ini file while using Pre-Unified Libraries
Xilinx Answer #856 : ProWave and ProSim: How to change system colors
Xilinx Answer #818 : Printing problems with PROcapture 6.1: Missing or greyed out lines
Xilinx Answer #809 : How to select a pin on a symbol in PROcapture
Xilinx Answer #775 : runtime error R6018 - unexpected heap error
Xilinx Answer #767 : xnf2wir error 214: pin names for <component> do not match Viewlogic symbol
Xilinx Answer #755 : PROSeries is not compatible with Windows 95/NT
Xilinx Answer #751 : XNF2WIR Error 10: Unknown record type 'bsm(X).xnf'.
Xilinx Answer #713 : PROsim hangs with a win32s error (multiple causes/resolutions)
Xilinx Answer #707 : FITNET will not use PIN 1 (MR) even if MRINPUT=ON was specified in Viewlogic
Xilinx Answer #700 : 6.0: About "Problem inv.PROCapture...Leave PSFM"
Xilinx Answer #687 : XSimMake, XDraw: "Could not access Sheet 1 of SCHEMATIC <top>." Powerview 5.3.2
Xilinx Answer #678 : PROflow: DOS Error # 83: Buffer too small
Xilinx Answer #637 : PROFLOW: Does not always display all available Xilinx device speed grades.
Xilinx Answer #632 : PROsim, ViewSim: Using the LOADM command with Xilinx FPGA simulations
Xilinx Answer #621 : PROWAVE: Printing section of waveform causes entire waveform to print.
Xilinx Answer #609 : WIR2XNF 5.x: INIT attribute on macros may not be passed to lower levels.
Xilinx Answer #604 : Viewlogic PROseries 6.0: System Error, sharing violation on drive <drive>:
Xilinx Answer #598 : PROSERIES 6.0: About error, "386 chip is currently exectuing in virtual mode"
Xilinx Answer #597 : PROcapture: Plotting to PostScript file doesn't work, possible cause (SHARE.EXE)
Xilinx Answer #594 : VIEWLOGIC PROFLOW 6.0: Will continue executing after Xilinx errors occur.
Xilinx Answer #592 : PROFLOW: Does not call PPR with all user-defined parameters (PPR.PRO problem)
Xilinx Answer #590 : PROSERIES: Plotting, other features are not MS Windows standard.
Xilinx Answer #588 : PROCAPTURE: cannot recognize the Xilinx C key. (No valid license for product)
Xilinx Answer #587 : VIEWLOGIC SIMULATION: FXC2K, FXC3K, FXC4K, FXC7K libs give quicker simulation
Xilinx Answer #586 : PROsynthesis PC INSTALL: PC locks up/crashes while installing, possible cause
Xilinx Answer #583 : PROcapture 6.0: Iconified PROcapture automatically quits on MS Windows exit
Xilinx Answer #577 : XNF2WIR returns error 201 if viewdraw.ini is not in project directory
Xilinx Answer #556 : POWERVIEW 5.3.1, WIR2XNF 5.x:Error 4 'Couldn't find workview.msg in WDIR'
Xilinx Answer #505 : WIR2XNF 5.0: About 'Unexpected token design_may_contain_rippers_recompilation..'
Xilinx Answer #486 : VIEWSIM timing simulation: "x" on the output of flip flop. XSIMMAKE
Xilinx Answer #485 : XNF2WIR ERROR 210 : could not load symbol of type [COULD_NOT_IDENTIFY]
Xilinx Answer #482 : XNF2WIR 5.x: Gives Error 210 if CY4 symbol is in design using pre XACT5 libs
Xilinx Answer #435 : PowerView,wir2xnf,xnf2wir: Working around 'SEC: host is not responding'
Xilinx Answer #428 : VIEWSIM: How to fix 'Could not open VHDL file...', 'Unrecognized component...'
Xilinx Answer #417 : PROwave: Dynamic annotation of signal values in PROcapture stored in PROwave
Xilinx Answer #378 : XACT 5: Using ViewSim to simulate board-level epld design
Xilinx Answer #351 : VIEWSIM Error, XC7000 EPLD: Could not find WIR file xc7000:pl22v10.1
Xilinx Answer #341 : xnf2wir 5.0: VSM gives 'ER Error - Could not find WIR file startup.1.'
Xilinx Answer #251 : Viewsim:ERROR:Multiple conflicting floatval attributes
Xilinx Answer #246 : VIEWsynthesis: Infering an xc4000 `set' flip-flop or an inverted xc3000 `reset' flip-flop
Xilinx Answer #240 : PROcapture: Do not use RAM16.1, RAM32.1, ROM16.1, and ROM32.1 components
Xilinx Answer #218 : Powerview: values not displayed on schematic during simulation
Xilinx Answer #183 : PROwave: Viewing an arbitrary set of signals as a bus in the waveform window
Xilinx Answer #161 : How to see more of the error messages in PROcapture status window
Xilinx Answer #146 : VIEWLOGIC programs report no license for symbol or schematic
Xilinx Answer #135 : WIR2XNF:SEC:license not found For product GENERIC Error 4:iwinit failure
Xilinx Answer #128 : ViewSim: Global reset signal names for 2k, 3k, 4k, 5k, 7k, and 9k (startup)
Xilinx Answer #110 : Viewlogic Simulation: Forcing a value to a signal and then releasing will cancel any FLOATVAL attributes
Xilinx Answer #109 : PROcapture: Do not remove the security key during the middle of a session
Xilinx Answer #101 : Viewsim: About ? Nodes in Timing Simulations