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Xilinx Answer #8532 : 2.1i, V1.5 COREGEN: How to run CORE Generator in verbose mode
Xilinx Answer #8379 : 2.1i, V1.5x COREGEN, VIRTEX: Availability of PDA FIR and SDA FIR filter modules for Virtex
Xilinx Answer #7462 : Viewlogic VHDL2SYM syntax
Xilinx Answer #7201 : COREGEN, VIRTEX : Virtex BaseBLOX Cores released in the C_IP1 Cores update
Xilinx Answer #7084 : V1.5 COREGEN: problems with Delay Element locking up and providing only 2 clock delays due to illegal state in LFSR
Xilinx Answer #7056 : COREGEN: How to generate a CORE Generator FIR filter with less than 6 taps
Xilinx Answer #6886 : V1.5 COREGEN, VIRTEX, BLOCK RAM: Block RAM generated EDIF still contains <> bus delimiters when ( ) (parentheses) or [ ] (square brackets) were specified as the desired delimiter
Xilinx Answer #6843 : V1.5, V1.4 COREGEN, WINDOWS NT: Text/fonts in GUI labels shows up as small squares instead of letters
Xilinx Answer #6732 : COREGEN: What state will SOUTR and SOUTF be in if the SDA FIR is generated in non-cascadeable mode?
Xilinx Answer #6611 : V2.1i COREGEN, VIEWLOGIC, POWERVIEW v6.1, VLLINK, UNIX, FUSION v1.4 : "ERROR: Viewlogic symbol generation failed.", "WARNING: Core xxx did not generate product ViewSym"
Xilinx Answer #6527 : V2.1, V1.5i COREGEN, FOUNDATION: Virtex block RAM generated by CORE Generator does not simulate initial values properly in Foundation functional simulation
Xilinx Answer #6260 : V1.5, V1.4 COREGEN, VERILOG, VHDL: .vhd and .v files produced by COREGEN are only for simulation.
Xilinx Answer #6190 : V2.1i, V1.5, V1.4 COREGEN: How to obtain the latest IP (COREs) for the CORE Generator
Xilinx Answer #6068 : 2.1i, V1.5 COREGEN, DATASHEETS: the CLB count is incorrect for a 16-bit wide loadable registered adder
Xilinx Answer #6002 : V1.5i, V1.5, V1.4 COREGEN : Unsatisfied link error on startup
Xilinx Answer #5787 : V1.5.2 COREGEN: Coregen User Guide version specified incorrectly as v1.5.2i on the cover page
Xilinx Answer #5783 : COREGEN C1_5.17 IP MODULE PATCH INSTALL: Cannot overwrite existing Coregen directories on PC
Xilinx Answer #5756 : V1.5, V1.4 COREGEN: Coregen EDIF targets 4013EPQ240-3 part when architecture is set to 4000 and Spartan families
Xilinx Answer #5727 : COREGEN, LOGIBLOX: Differences between 4K Dual Port RAM generated by Coregen and LogiBLOX
Xilinx Answer #5661 : C1_5.17 COREGEN IP MODULE LIBRARY UPDATE: Known problems with the ROM-Based Correlators, NCO, and Divider
Xilinx Answer #5648 : V1.5.2/V1.5i_sp1 COREGEN, INSTALL: Coregen 1.5.2 in A1_5i Service Pack 1 contains readme from the older 1.5 release / How to verify the Coregen 1_5i Service Pack 1 install.
Xilinx Answer #5630 : V1.5.2 COREGEN: Information on the Coregen v1.5.2 release shipped with F1.5i_sp1/sp2, and A1.5i_sp1/sp2 (Service Pack 1 and 2 for Foundation F1.5i or Alliance A1.5i).
Xilinx Answer #5445 : V1.5 COREGEN, FOUNDATION: Bus Conflict errors during Foundation functional and timing simulation of NCO modules
Xilinx Answer #5402 : V1.5.2 COREGEN, XC4000: 4K 1-D ROM-based Correlator bit masking function irregularities: problems excluding MSBs, use of 0's to mask out bits, apparent incorrect behavioral and backannotated simulation model
Xilinx Answer #5358 : COREGEN, VHDL: Output still available from VHDL behavioral model for area-optimized multiplier when CE is deactivated
Xilinx Answer #5264 : A1.5i, F1.5i, COREGEN: What version of COREGEN is shipped with M1.5i (Performance Pack bundle)?
Xilinx Answer #5218 : V1.5 COREGEN, VIRTEX, VERILOG, VHDL, MIF, COE: What files are required for proper initialization of a Virtex Block RAM in an HDL behavioral simulation? / What is the MIF file?
Xilinx Answer #5209 : V1.5, V1.4 COREGEN DATASHEET, 4K RAM: CLB utilization formula is incorrect for odd-valued Single Port 4K RAM sizes (sizes of the form 2N+1)
Xilinx Answer #5165 : COREGEN, 4K: Estimating the number of 4K RAM/ROM primitives used in COREGen memories / When does COREGEN use 16x1 and 32x1 RAM/ROM primitives
Xilinx Answer #5083 : 2.1i, V1.5 INSTALL, COREGEN: " Your registry HKEY_LOCAL_MACHINE/SOFTWARE/JavaSoft/Java RuntimeEnvironment/1.1/javahome" messages and "JAVA was not found " or "Unsatisfied link" errors)
Xilinx Answer #4993 : V1.5 COREGEN, VERILOG-XL: "Error! syntax error ... parameter signed =<-" / COREGEN Verilog behavioral models use Verilog-XL reserved word "signed" as a user parameter
Xilinx Answer #4831 : COREGEN: Output of Delay Element module does not change in simulation if CE is unconnected
Xilinx Answer #4821 : V1.5, V1.4 COREGEN: COREGen does not support dual-port ram with unregistered outputs
Xilinx Answer #4675 : COREGEN: How to do an impulse response simulation of a SINGLE cascade mode SDA FIR filter
Xilinx Answer #4650 : V1.5, V1.4 COREGEN: Cannot start up COREGEN from Desktop and Start Menu shortcut on some PC's
Xilinx Answer #4631 : 2.1i, V1.5, V1.4 COREGEN, FOUNDATION: How to invoke NET2SYM in command line mode
Xilinx Answer #4610 : COREGEN: How to calculate the clock/pipeline latency of the COREGEN PDA FIR filter
Xilinx Answer #4543 : V1.5, V1.4 COREGEN: Only the 24 LSBs of a cascade mode SDA FIR output are defined in a Verilog behavioral simulation
Xilinx Answer #4521 : V1.5 COREGEN, FOUNDATION, XC4000, SPARTAN: "Warning 9199: Unknown component - B998, TBUF" when loading Foundation design containing COREGEN SINE-COSINE LUT, FIFOs, ROMs, or RAMs into the F1.5 Foundation simulator
Xilinx Answer #4504 : COREGEN, DSP, WEBLINX: DSP brochure on WebLINX indicates that Xilinx supports Sine/Cosine/Arctan LUTs of any width and table depth.
Xilinx Answer #4445 : M1.5, M1.4 COREGEN, ORCAD: bus delimiter setting in COREGEN XNF for Orcad designs
Xilinx Answer #4427 : 2.1i, 1.5, 1.4 COREGEN: How the PDA FIR Filter module calculates its full precision output width.
Xilinx Answer #4317 : V1.5, V1.4 COREGEN: directory and project naming restrictions
Xilinx Answer #4306 : V1.5, V1.4 COREGEN INSTALL, WINDOWS NT: uninstall "setup failed to initialize" error when installing on Windows NT
Xilinx Answer #4290 : V1.5.0 COREGEN: Known Problems / Issues (README file / release document).
Xilinx Answer #4289 : V1.5 COREGEN: How to get a copy of the CORE Generator v1.5 CD-ROM
Xilinx Answer #4270 : 2.1i, V1.5 COREGEN, JAVA: "NoclassDefFoundError: xilinx/widget/frame/PaneListener"
Xilinx Answer #4245 : V1.5 COREGEN, VIEWLOGIC, HP: "ERROR: ViewlogicInterface Exiting due to IOException:java.io.IOException: Not enough space" on HP-UX platform
Xilinx Answer #4242 : V1.5 COREGEN: Wrong (fixed) time stamp / date in EDIF generated by COREGEN
Xilinx Answer #4232 : V1.5, V1.4 COREGEN: Fixed point Speed-Optimized Multipliers lack CE pin.
Xilinx Answer #4229 : V1.5, V1.4 COREGEN, SOLARIS: "Load Coefficients" browser displays all files instead of just files with a .coe extension
Xilinx Answer #4228 : V1.5 COREGEN: "View Init Values Button" is not supported for Virtex Block RAM
Xilinx Answer #4227 : V1.5 COREGEN: Data width is limited to 31 or less for some CORE Generator functions (Single Port RAM, Dual Port RAM, ROM, PDA FIR Filter)
Xilinx Answer #4226 : V1.5, V1.4 COREGEN: Disk full condition may cause Coregen infinite loop (ERROR: java.io.IOException: write error)
Xilinx Answer #4225 : 2.1i, V1.5, V1.4 COREGEN: "WARNING: Core 12x12_Multiplier (8x8_Multiplier) did not generate product VerilogSim"
Xilinx Answer #4224 : V1.5, V1.4 COREGEN: Cursor (arrow) keys produce numbers when NumLock key is active on Solaris
Xilinx Answer #4213 : V1.4.0, V1.5.0 COREGEN: Warning: Your directory path <directory_path> should not contain any directory names longer than 8 characters.
Xilinx Answer #4212 : V1.5, V1.4 COREGEN: Clarification on bus naming convention in COREGEN datasheet tables and block diagrams--N, n, M & m indices
Xilinx Answer #4209 : V1.4, V1.5 COREGEN, VIEWLOGIC, FOUNDATION: symbols generated by COREGen do not match those shown in the datasheets for the core.
Xilinx Answer #4208 : V1.5, V1.4 COREGEN, FOUNDATION: symbol pin ordering may be inconsistent between the V1.4 and V1.5 releases
Xilinx Answer #4207 : V1.5 COREGEN: Some columns are blank in the (performance/speed) characterization data tables for -08 speed grade parts.
Xilinx Answer #4191 : V1.5 COREGEN: Sample .COE files for Virtex block RAM
Xilinx Answer #4179 : C1.4 COREGEN Installation gives message "The Register is Not Properly Configured for CORE Generator. Please Reinstall Original Software."
Xilinx Answer #4166 : V1.5 COREGEN: What's new in the v1.5 release
Xilinx Answer #4164 : V1.5, V1.4 COREGEN, HP: Folder icons are not displayed when COREGEN is invoked on an HP and GUI is displayed on Solaris
Xilinx Answer #4158 : V1.4 COREGEN: How to install the pre-C1.5 version of the DFT/FFT core zip archive
Xilinx Answer #4157 : V1.5 COREGEN: None of the AllianceCore Cores are grayed out when Virtex is selected as the target architecture
Xilinx Answer #4152 : V1.5 COREGEN: Which cores / modules are being shipped in this release?
Xilinx Answer #4151 : V1.5 COREGEN: Can V1.5 be installed over the V1.4 release?
Xilinx Answer #4123 : V1.5 COREGEN, LOGIBLOX, VIRTEX: Virtex ROMs and SelectRAM (distributed RAM, dual port RAM, single port RAM, synchronous RAM) generation support
Xilinx Answer #4109 : V1.4.0 COREGEN, Install, French Windows95: "a file .dll required, MSVCRT.DLL has not been found"
Xilinx Answer #4099 : V1.4.0 COREGEN, VF1.3 Foundation: "Call to Undefined Dynalink" while generating a core in COREGen
Xilinx Answer #4020 : V1.5 COREGEN, FOUNDATION: Version of Foundation compatible with COREGEN V1.5
Xilinx Answer #4017 : COREGEN: What is SystemLINX?
Xilinx Answer #4011 : V1.5 COREGEN: coregen.ini variables
Xilinx Answer #4009 : V1.5, 1.4 COREGEN, VHDL: where is the UL_UTILS.vhd library for behavioral simulation
Xilinx Answer #3965 : V1.5, V1.4.0 COREGEN: COREGen may create .VHX, XNF(v1.4)/EDN(v1.5) and .XSF output files even when not directed to do so
Xilinx Answer #3949 : COREGEN: Registered Scaled Adder: What is the "floor()" function mentioned in the data sheet?
Xilinx Answer #3947 : Coregen v1.4: Exemplar flow (with and without LogiBLOX) (basnb:79 - Pin mismatch, basnu:93 - Unexpanded...).
Xilinx Answer #3915 : V1.4.0 COREGEN: 30-bit bus input width limit on COREGEN modules / Cannot specify 32-bit input bus widths / integer arithmetic overflow
Xilinx Answer #3891 : COREGEN: What is "SystemView" from Elanix, and how can I get more information on it?
Xilinx Answer #3884 : 2.1i, V1.5, V1.4 COREGEN:: versions of third party CAE platforms and M1 supported by COREGEN
Xilinx Answer #3883 : 2.1i, 1.5, V1.4 COREGEN: How to permanently set the default output format for COREGen
Xilinx Answer #3872 : COREGEN V1.4.0, FOUNDATION F1.3: "Invalid call to .DLL" error during netlist creation in Foundation F1.3 after installing COREGen v1.4.0
Xilinx Answer #3863 : 2.1i, V1.5, V1.4 COREGEN, FOUNDATION EXPRESS: How to generate Foundation functional simulation files for a VHDL design
Xilinx Answer #3862 : V1.4.0 COREGEN: "Parameter value is not in allowed range"
Xilinx Answer #3850 : V1.4.0 COREGEN: What's new in the v1.4.0 release
Xilinx Answer #3846 : COREGEN: Tips on simulating the SDA FIR filter
Xilinx Answer #3840 : V1.5, V1.4 COREGEN: How to obtain the latest COREs, software enhancements, and patches / SDA FIR Filter module available in v1.4.0p1 patch supplement
Xilinx Answer #3819 : V1.4.0 COREGEN: CD jacket has an error in path to workstation install--/cdrom.cdrom0/install should be /cdrom/cdrom0/install
Xilinx Answer #3791 : 2.1i, V1.5, V1.4 COREGEN: 4K Synchronous FIFO LogiCORE output is only valid when RE is enabled
Xilinx Answer #3790 : V1.4.0 COREGEN: Output Options dialog box background color is two shades of gray instead of one uniform shade
Xilinx Answer #3785 : V1.4 COREGEN: Blank DOS box appears when COREGen is invoked with Windows Display set to "True Color", entire program hangs; Windows NT.
Xilinx Answer #3754 : V1.5, V1.4 COREGEN: Xilinx M1.4 and Viewlogic must be installed first for Viewlogic users, and Foundation must be installed for Foundation users
Xilinx Answer #3729 : COREGen v1.4.0: MS-DOS box on the Windows 95 taskbar does not terminate when you exit COREGen
Xilinx Answer #3713 : V1.4 COREGEN: Integer arithmetic overflow during VHDL behavioral simulation of SQRT (square root) function
Xilinx Answer #3702 : V1.5, V1.4 COREGEN: Parameter File Information tables in the COREGen datasheets
Xilinx Answer #3700 : V1.4.0 COREGEN, VIEWLOGIC: "ERROR starting PM. Missing LIBBASUT.DLL"
Xilinx Answer #3697 : V1.5, V1.4 COREGEN: COREGen does not release CPU after generating a core module
Xilinx Answer #3696 : COREGen v1.4.0: COREGen overwrites files in the working or project directory without checking with the user
Xilinx Answer #3695 : V1.4 COREGEN, VIEWLOGIC: "The VLLINK.BAT file has a line that is longer than 254 characters."
Xilinx Answer #3694 : V1.5, V1.4 COREGEN: Limitations on running the CORE Generator over networks on UNIX & Win95 platforms
Xilinx Answer #3681 : V1.5, V1.4 COREGEN, LOGIBLOX: Differences between COREGen and LogiBLOX, which modules are generated as RPMs
Xilinx Answer #3677 : V1.5, V1.4 COREGEN: How can I install AcroRead on a Solaris system if it is not already installed?
Xilinx Answer #3676 : COREGEN v1.4.0: How can I get a copy of the CORE Generator v1.4.0 CD?
Xilinx Answer #3675 : V1.5, V1.4 COREGEN: Which cores / modules are being shipped in these releases?
Xilinx Answer #3674 : ** OBSOLETE ** V1.4.0 COREGEN: Can v1.4.0 be installed over the Alpha 3.0.x release?
Xilinx Answer #3673 : 2.1i, V1.5, V1.4.x COREGEN: Solaris Stopwatch "busy" cursor or Windows hourglass cursor lingers (seems to hang) after an operation is completed.
Xilinx Answer #3670 : COREGen v1.4.0, Windows: Blank / empty warning message boxes pop up when warning message is too long on 800x600 video resolution (e.g., Viewlogic, PDA FIR)
Xilinx Answer #3668 : V1.5, V1.4 COREGEN: How to determine the build version of the CORE Generator GUI
Xilinx Answer #3663 : Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R
Xilinx Answer #3658 : V1.4.0 COREGEN: Known Problems / Issues (README file / release document).
Xilinx Answer #3639 : V1.5, V1.4 COREGEN: How do I get my COREGen module implementation to match the performance / speed specified in the COREGen spec sheet?
Xilinx Answer #3635 : Naming restrictions for CORE Generator modules (upper case names are illegal)
Xilinx Answer #3633 : V1.5, V1.4 COREGEN: How to uninstall it
Xilinx Answer #3629 : V1.5, V1.4: COREGEN VIEWLOGIC: PINORDER property/attribute is visible on Viewlogic symbols generated by COREGen
Xilinx Answer #3628 : V1.5, V1.4 COREGEN: Errors when loading spec sheets in Acrobat 2.1
Xilinx Answer #3627 : 2.1i, V1.5, V1.4 COREGEN GUI: Hourglass "busy" cursor lingers indefinitely until mouse is moved
Xilinx Answer #3625 : V1.5, V1.4 COREGEN: How VLLINK.BATand VLLINK are invoked by the COREGEN GUI in v1.4 and v1.5 / debugging problems with VLLINK
Xilinx Answer #3558 : C1.5., C1.4 COREGEN: cannot expand module folders by double clicking them on Openwindows
Xilinx Answer #3498 : V1.5, V1.4 COREGEN: Does COREGen support floating point values in the .COE coefficient files?
Xilinx Answer #3493 : 2.1i, V1.5, V1.4 COREGEN, XC4000: Incorrect data on output of 4K PDA FIR and SDA FIR cores when maximum output width is not selected
Xilinx Answer #3432 : V1.5.x, V1.4 COREGEN: Not all processing output is logged to the coregen.log file.
Xilinx Answer #3399 : 2.1i, V1.5, V1.4 COREGEN: How to debug COREGEN hang and startup problems
Xilinx Answer #3327 : COREGEN: When are TBUFs used for muxing in ROMs, single port RAMs, and dual port RAMs?
Xilinx Answer #3325 : V1.5.0, V1.4.0 COREGEN: java.lang.OutOfMemoryError "Out of memory" errors on very large cores
Xilinx Answer #3180 : V1.5, V1.4 COREGEN, VIEWLOGIC: Error: Could not read symbol file <path_to_SYM_dir>\SYM\<modulename>.1 java.io.File NotFoundException: <path_to_SYM_dir>\SYM\<modulename>.1
Xilinx Answer #3094 : ** OBSOLETE ** ALPHA 1.1 COREGEN: Warning: Your directory path <directory_path> should not contain any directory names longer than 8 characters.
Xilinx Answer #3040 : V1.5, V1.4 COREGEN: sample COREGen .COE coefficient files for a PDA FIR filter, RAM and ROM.
Xilinx Answer #3031 : V1.5, V1.4 COREGEN, WORKVIEW OFFICE, M1: Implemented module has much higher CLB counts than specified in the datasheet
Xilinx Answer #2955 : V1.5 COREGEN: What architectures are supported?
Xilinx Answer #2861 : ** OBSOLETE ** ALPHA v3.0.x COREGEN, FOUNDATION F1.3: problems generating Foundation symbol in Windows 95 and NT
Xilinx Answer #2837 : ** OBSOLETE ** COREGEN: Rice FFT (DFT) Data Sheets
Xilinx Answer #2625 : How to calculate sample rate for SDA filters.
Xilinx Answer #2546 : V1.4.0 CORE Generator: Viewlogic Synthesis Flow (VHDL only)
Xilinx Answer #2411 : COREGEN: Latency of the Variable Multiplier core
Xilinx Answer #2209 : V1.4.0 CORE Generator: Foundation Schematic Flow
Xilinx Answer #2118 : V1.5, V1.4 COREGEN, JAVA: This program has performed an illegal operation /page fault in module WINAWT.DLL on Windows (display settings problem)
Xilinx Answer #2116 : V1.4 COREGEN: SYNOPSYS VHDL FLOW