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Xilinx Answer #8572 : 2.1i Virtex-E Map - Map outputs incorrect message when processing invalid Virtex LOC constraints.
Xilinx Answer #8492 : 2.1i Virtex Map - FATAL_ERROR:baspu:baspupacker.c:313:1.40 - read of floorplanner file ....
Xilinx Answer #8490 : 2.1i Virtex Map - Inversion between MUXCY and Flop is dropped/
Xilinx Answer #8368 : 2.1i Virtex-E Map: XCV600E-BG32 Map report lists an incorrect number of bonded IOBs.
Xilinx Answer #8310 : EXEMPLAR 1999.1g, MAP 2.1i: GSR is connected to GND, ERROR:OldMap:928 - There is no signal on pin A0 of CY4 symbol (sourceless)
Xilinx Answer #8262 : 2.1i 4KXLA Map - FATAL_ERROR:OldMap:x45maclb.c:204:1.1.2.2 - Unknown input pin Q
Xilinx Answer #8148 : 2.1i Virtex Map - Apparently legal MUXF5 pack is rejected.
Xilinx Answer #8143 : 2.1i Virtex Map - FDRSE optimized to zero incorrectly.
Xilinx Answer #8092 : 2.1i Virtex Map - FATAL_ERROR:xvkpu:xvkpulocal.c:246:1.3
Xilinx Answer #8073 : 2.1i Virtex Map - ERROR:basmm:227 - LUT2 symbol "G_6919" (output signal=N_8071) has an equation..
Xilinx Answer #8046 : 2.1i VirtexE Map - Map does not make use of the fastdll feedback path between DLLIOBs and Secondary DLLs.
Xilinx Answer #7995 : 2.1i 4000XL Map- ERROR:OldMap:256 - Clock buffer BUFG symbol "..." cannot be converted to a BUFGLS due to location constraints.
Xilinx Answer #7965 : 2.1i Map - Pack errors on floorplanned gates do not always report problem area.
Xilinx Answer #7906 : 2.1i COREGEN, C_IP3: MAP: "ERROR:xvkpu - Unable to obey design constraints" / Distributed Memory Cores may fail in MAP
Xilinx Answer #7905 : 2.1i 4K Map - Map does not support the use of three external inputs to an HLUT.
Xilinx Answer #7888 : 2.1i Virtex Map - Eligible flop is not considered for input IOB merge.
Xilinx Answer #7868 : 2.1i 4KX* Map - ERROR : DesignRules: 207 - Blockcheck: The pin "O" on comp (mapped physical logic cell) "inst_name" is configured to be used but has no signal attached to it.
Xilinx Answer #7854 : 2.1i 4000XL Map/Fplan - Constrain from placement gets tripped up by Map route-thru.
Xilinx Answer #7841 : 2.1i Virtex Map - Application Error crash occurs when loading NGD file. Design contains Pullups on some inputs.
Xilinx Answer #7795 : 2.1i 4K* Map - Packing error fails to list the comps involved.
Xilinx Answer #7733 : 2.1i Virtex Map - Unable to pack the register xxx because of connectivity restrictions.
Xilinx Answer #7731 : 2.1i Virtex Map - Map errors out due to invalid trimming of OBUFT control signal
Xilinx Answer #7728 : 2.1i Virtex Map - The default input path delay element usage is being changed.
Xilinx Answer #7709 : 2.1i Virtex Map - MAP uses the incorrect JF setting for a CLKDLLHF
Xilinx Answer #7685 : 2.1i Virtex Map - Pack Error: MULT_AND symbol X must be connected to ...
Xilinx Answer #7638 : 2.1i Virtex Map - Pack of two RAMs into one slice fails with incorrect message.
Xilinx Answer #7509 : 2.1i Virtex Map: FATAL_ERROR:xvkpu:xvkpucarry.c:604:1.23 - The carry multiplexer U_RDCONT/U_OUTCONT/add_102/plus/plus/A_CY_12 has an unconnected output
Xilinx Answer #7487 : 2.1i SP1 Virtex Map -FATAL_ERROR:xvkpk:xvkpkslice.c:146:1.30
Xilinx Answer #7478 : 2.1i 4K Map - Map can not combine dual port ram with registers into the same CLB when local set /reset signal used.
Xilinx Answer #7466 : 2.1i Virtex Map - Mapper creates unroutable connection when F6mux is driven by two F5muxes.
Xilinx Answer #7453 : 2.1i Virtex Map - Map hangs at "Reading NGD file ..." on XCV1000 design
Xilinx Answer #7408 : 2.1i 4KX* Map - Map does not properly place floorplanned DPRAMs
Xilinx Answer #7364 : 2.1i Virtex Map - Mapped design results in sourceless net leading to DRC errors.
Xilinx Answer #7360 : 2.1i SPXL Map - GLUT to FFY connection uses external path
Xilinx Answer #7359 : 2.1i 4KX* Map - FATAL_ERROR:x4kma:x4kmagrclapse.c:3138:1.110.16.3
Xilinx Answer #7357 : 2.1i 4000 Map - ERROR:OldMap:56 - The LOC constraint "W2" (a MODE1 location) is not valid for OPAD symbol "$xx" which is being mapped to the following site type CLKIOB, FCLKIOB,IOB
Xilinx Answer #7349 : 2.1i Virtex Map - Virtex mapper treats OBUF driving PU, PD, or KEEPER inconsistently.
Xilinx Answer #7325 : 2.1i Virtex Map - Map creates bad .pcf constraints from floorplanner constraints.
Xilinx Answer #7321 : 2.1i Virtex Map - The Virtex packer is failing to process the local output directive properly.
Xilinx Answer #7299 : 2.1i Virtex Map - Map: exception:0xc0000005 at 0x00245970
Xilinx Answer #7290 : 2.1i Virtex Map - IOB=true attribute is ingored for tri-state enable register in Virtex
Xilinx Answer #7279 : 2.1i Virtex Map - Map drops inverter when FF pushed into IOB.
Xilinx Answer #7277 : 2.1i Virtex Map - ERROR:xvkpu - Unable to obey design constraints ...
Xilinx Answer #7264 : 2.1i Virtex Map - exception: Access Violation (oxc0000005), address:ox00255920
Xilinx Answer #7239 : 2.1i 4000XL Map - Guided map creates a corrupted CLB configuration
Xilinx Answer #7228 : 2.1i Virtex Map - Some pullup/pulldown/keeper configurations are not being handled properly.
Xilinx Answer #7222 : 2.1i Virtex MAP Error:xvkpu - Unable to obey design constraints
Xilinx Answer #7213 : 2.1i Map - FATAL_ERROR:Ncd:basncinfo.c:139:1.1.2.4 SiteParams are out of sync
Xilinx Answer #7147 : 2.1i Virtex Map - Can any component drive the CLKIN input of a clkdll?
Xilinx Answer #7142 : 2.1i XC4000XL Map - FATAL_ERROR:OldMap:x4emamerge.c:2410:1.1.2.6 - Illegal merge detected
Xilinx Answer #7124 : 2.1i Virtex Map - A case has been seen where map does not pack CYMUX and XORCY with the register they drive.
Xilinx Answer #7083 : 1.5i/2.1i 4K Map - ERROR:OldMap:532 - Unable to obey design constraints which require the following symbols into a single CLB. . .
Xilinx Answer #7072 : 2.1i Virtex Map - Virtex mapper treats OBUF driving PU, PD, or KEEPER inconsistently.
Xilinx Answer #7008 : 2.1i Virtex Map - Map may configure a BUFT driven by PWR/GND in a way that will not work in the hardware.
Xilinx Answer #6994 : 1.5i/2.1i Map - Xnf (sxnf) file created by FPGA Compiler is processed differently that xnf files from other vendors.
Xilinx Answer #6799 : MAP: 1.5i/2.1i, FPGA Express: basnccomp.c:3346:1.1.2.4-cannot find other bel. . .
Xilinx Answer #6796 : 2.1i SpartanXL Map - FATAL_ERROR:OldMap:bastemacro.c:897:1.1.2.2 - Signal doesn't drive comps in macro.
Xilinx Answer #6793 : 2.1i Virtex MAP - Map will not put two unconstrained SRL16s into a single Virtex slice.
Xilinx Answer #6708 : 2.1i Virtex Map - ERROR:xvkpu - Unable to obey design constraints...
Xilinx Answer #6624 : 2.1i Virtex Map - Map errors atttibuted to incorrect CLKDLL usage (ERROR:xvkmm:12 and ERROR:xvkmm:16)
Xilinx Answer #6572 : 2.1i Virtex Map - Device utilization appears to increase because of new default packing rules.
Xilinx Answer #6563 : 1.5i, 2.1i Map - A .mfp constraint for LOC'd FF is incorrecty overridden by "-pr b"
Xilinx Answer #6562 : 1.5i/2.1i Map - FATAL_ERROR:basnc:basncsignal.c:263:1.67 - Could not find a bel...
Xilinx Answer #6438 : 2.1i Floorplanner: Map file naming is causing problems for the Design Manager
Xilinx Answer #6314 : 1.5i, 2.1i Virtex Map - FATAL_ERROR:basmm:basmmfact.c:1349:1.84 - Unknown pad pin type
Xilinx Answer #6229 : Map 1.5i, 2.1i Map - FATAL_ERROR:basut:basutcname.c:410:1.8; Utilities:UtilCname.imp.c:400:1.1.2.2: Maximum name length exceeded
Xilinx Answer #6194 : 1.5i, 2.1i Map - A level of logic is used for inverter between IBUF and Register.
Xilinx Answer #5778 : 1.5i, 2.1i 4K Map - Guided map of unchanged design is unable to guide several CLBs.
Xilinx Answer #5394 : 1.5i, 2.1i 4KX* Map - Map errors out on carry logic when trimming is disabled.
Xilinx Answer #5031 : 2.1i 4KX* MAP - FATAL_ERROR:x4ema:x4emamerge.c:3535:1.43 - Pin 8 already in use. moveflopinpin() for CLB: [3793] Process will terminate.
Xilinx Answer #4991 : 1.5i, 2.1i Map - 4KXLA design seg faults in Map after "Removing unused logic..."
Xilinx Answer #4406 : 2.1i, M1.5, M1.4 MAP, LOGIBLOX: Map:ERROR:x4kma:179 - <symbolname> symbol "instance" cannot be packed into an IOB
Xilinx Answer #4081 : 1.5i, 2.1i Map- FATAL_ERROR:x4kma:x4kmaclkinfo.c:786:1.24 - Clkinfo: sitearray overrun: page1$1p/page1$i135.
Xilinx Answer #3867 : M1.5i/2.1i: Timing Analyzer: No default physical constraints file "\...\map.pcf" was found.
Xilinx Answer #2337 : 1.5i, 2.1i Map - "place instance *" constraint causes ERROR:x4kma:148 - IBUF symbol cannot be merged, incompatible site types
Xilinx Answer #2312 : 1.5i, 2.1i 4K* Map - 'ERROR: baste:125 - The RLOC value of "R62C2.FFY" on CLB .... in RPM ....'. The design is too large for the given device and package (can't fit design).