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Xilinx Answer #8545 : 2.1i Spartan-XL PAR - Placer fails to place TDO comp when Exact Guide is used.
Xilinx Answer #8486 : 2.1i Virtex PAR - Exception integer divide by zero par.exe caused exception 0xc000094 in module C;\xilinx\virtex\bin\nt\libplvirt_place.dll at 001B : 09c6B88A"
Xilinx Answer #8421 : 2.1i Spartan-XL PAR - Router gets poor results on XCS30XL and XCS40XL designs compared to 1.5i.
Xilinx Answer #8322 : 2.1i Spartan-XL PAR - FATAL_ERROR:Route:basrtsanity.c:234:1.1.2.2 - Process will terminate.
Xilinx Answer #8297 : 2.1i XV1000E PAR - A data file fix for XV1000E may improve placement results for some designs.
Xilinx Answer #8251 : 2.1i Virtex PAR - Application Error during Placement of V300 design
Xilinx Answer #8182 : PAR2.1isp3: Par hangs after the message "Starting Initial Timing Analysis"
Xilinx Answer #8150 : 2.1i Virtex PAR - Memory leak seen during timing analysis of V800 design.
Xilinx Answer #8094 : 2.1i VirtexE PAR - Placer continues even if LVDS IO comps have no locate constraints
Xilinx Answer #8093 : 2.1i Virtex PAR - FATAL_ERROR:Utilities:basagconjgradient.c:202:1.1.4.2 - CG SOLVER: residual
Xilinx Answer #8032 : 2.1i Virtex Map/PAR- Error:Place:871 - Carry chain placement conflicts with floor planned register LOCs.
Xilinx Answer #8008 : Synopsys FPGA Compiler, M2.1i PAR: ERROR:Parsers:3 - Unable to parse "+" in line 4.
Xilinx Answer #8000 : PAR 2.1is2 - par report does not give the correct Vcco value for LVDS IO
Xilinx Answer #7988 : 2.1i PAR - PAR fix improves results for all device families.
Xilinx Answer #7950 : 2.1i Virtex PAR - par.exe exception:divide by zero (0xc0000094) Address: 0x0d36689a
Xilinx Answer #7938 : 2.1i XC4000XL PAR - Guided par of 4000XL device does not work in 2.1i Service Pack 1 or 2.
Xilinx Answer #7813 : 2.1i Virtex PAR - Router has difficulty connecting Block RAM pins
Xilinx Answer #7788 : 2.1i PAR - S40XLPQ240-5 pad report does not match data book
Xilinx Answer #7766 : 2.1i Virtex PAR - PAD report does not show usage of VREF pins on Virtex devices, whether or not they are used
Xilinx Answer #7745 : 2.1i PAR - Will Multiple Processors Speed up PAR times?
Xilinx Answer #7734 : 2.1i Virtex PAR - The .par results file reports incorrect number of logic levels
Xilinx Answer #7628 : 2.1i Virtex PAR: par.exe, exception:access violation (0x0000005), address: 0x05f07efd
Xilinx Answer #7503 : 2.1i Par:placement pass 2 FATAL_ERROR:Utilities:basagconjgradient.c:202:1.1.4.2 - CG SOLVER: residual after solving
Xilinx Answer #7471 : 2.1i SpartanXL PAR - Crash caused by design containing signals with no pins.
Xilinx Answer #7372 : 2.1i Virtex PAR - PC only crash occurs after "Starting the placer".
Xilinx Answer #7350 : 2.1i PAR - PAR does not cleanup low-end results when running turns engine (ignores -s)
Xilinx Answer #7345 : 2.1i Virtex PAR - Placer leaves source pin of high fanout net unplaced, leading to router crash.
Xilinx Answer #7342 : 2.1i SpartanXL PAR - FATAL_ERROR:Route:basrtsanity.c:241:1.1.2.2 -Process will terminate.
Xilinx Answer #7335 : 2.1i SpartanXL PAR - PAR fails to produce consistent results when running a cost table twice.
Xilinx Answer #7316 : 2.1i Virtex PAR - Placer has been enhanced to use MAXSKEW preference to assign secondary global clock buffers for external clock nets.
Xilinx Answer #7296 : 2.1i 4KX* PAR - Prohibit constraint ignored
Xilinx Answer #7249 : 2.1i 4KX* PAR - Dr Watson during routing. Access violation (0xc0000005), Address: 0x0024b0b1
Xilinx Answer #7245 : 2.1i 4KX* PAR - Application error has occured. Exception:Access Violation (0xc0000005), Address: 0x039313b9
Xilinx Answer #7243 : 2.1i Virtex Map/PAR - Map and PAR issues related to Virtex Carry chains
Xilinx Answer #7141 : 2.1i Virtex PAR - FATAL_ERROR:Route:xvkrtconn.c:116:1.1.2.4 - UNPLACED COMP ENCOUNTERED
Xilinx Answer #7121 : 2.1i PAR - How to determine the amount of memory used by PAR (and other Xilinx applications).
Xilinx Answer #7086 : 2.1i Virtex Map/PAR - Designs combining non-RLOC'd carry chains and macros may fail.
Xilinx Answer #7085 : 2.1i Spartan Par - Crashes with access violation when two bufgs are locked to same location
Xilinx Answer #7078 : 2.1i Virtex PAR - Placer ignores list constraint involving IOB.
Xilinx Answer #7064 : 2.1i Virtex PAR - Router terminates with Segmentation fault during PWR/GND routing.
Xilinx Answer #7052 : 2.1i Virtex PAR - Using the -k switch on Virtex designs may cause a Segmentation Fault/ Access Violation in PAR.
Xilinx Answer #7025 : 2.1i Virtex PAR - ERROR:Place:1631, 1632 Could not find a legal placement for the following components....
Xilinx Answer #6999 : 2.1i Virtex PAR - FATAL_ERROR:Route:xvkrtconn.c:116:1.1.2.4 - UNPLACED COMP ENCOUNTERED
Xilinx Answer #6996 : 2.1i Virtex PAR - FATAL_ERROR:Route:basrtsanity.c:241:1.1.2.2 - Process will terminate.
Xilinx Answer #6986 : 2.1i Virtex PAR - Placer can not successfully place DLL configurations that worked in 1.5i.
Xilinx Answer #6984 : 2.1i Virtex PAR - PAR is failing to allow 2 DLL design with 3 BUFGs to complete.
Xilinx Answer #6980 : 2.1i Virtex PAR - Core dump with leverage guide when dealing with non-aligned carry chains.
Xilinx Answer #6953 : 2.1i Virtex PAR - Virtex designs with area constraints may run out of memory during placement.
Xilinx Answer #6739 : 2.1i Virtex PAR - Virtex design is taking too long to route PWR/GND signals.
Xilinx Answer #6737 : 2.1i VirtexE PAR - PAR fails with Acess Violation on XCV100E and XCV200E.
Xilinx Answer #6672 : LogiCORE PCI: M2.1i PAR does not guide all connections for 4KXLA/XLT, SpartanXL/Spartan PCI cores
Xilinx Answer #6633 : 1.5i, 2.1i PAR - High density placer (4085XL+, 4KXV) fails on area constrained TBUFs.
Xilinx Answer #6573 : 2.1i Virtex PAR - MPPR usage less effective due to less dependence on cost table differences.
Xilinx Answer #6568 : 2.1i Spartan2 PAR - Spartan2 placer may crash when placing routed hard macros.
Xilinx Answer #6408 : 1.5i, 2.1i Virtex PAR - PAR crashes with Exception: access violation (0xC0000005) Address 0x031335A6
Xilinx Answer #6335 : 1.5i, 2.1i 4KX* PAR - Pad report contains TDO as a reserved pin even when not using boundary scan
Xilinx Answer #5779 : 2.1 Virtex PAR - Guided Par can't match components using guide file created in 1.5i release or earlier.
Xilinx Answer #5098 : 2.1i PAR - Route results lead to DRC warning: WARNING:basdr:7 - Netcheck: An antenna was found on signal "hp_rdy";
Xilinx Answer #3813 : 1.5i, 2.1i XC4000XL PAR - Router duplicates registers for use as output to output route-thrus.
Xilinx Answer #3534 : M1.5i/2.1i: How to preserve the pinout of a previous PAR run (pad2ucf)