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I/O
    resetting to defaults
    unassigning pins from
I/O assignment constraints
I/O Attribute Editor
    starting
I/O Attribute Editor MVN
    editing I/O attributes
    editing multiple rows
    formatting rows and columns
    sorting attributes
    specifying an I/O Standard
I/O attributes
   About I/O Attributes
   I/O Attributes and I/O Standards Applicability
   I/O Attributes by Family
   I/O attributes by family (MVN version)
    bank name
    by family
    hot swap
    I/O standard
    I/O threshold
    input delay
    loading
    locked
    macro cell
    output drive
    output level
    output load
    pin number
    port name
    power-up state
    resistor pull
    schmitt trigger
    skew
    slew
    use register
I/O Bank reports
    creating with Tcl
I/O bank settings
I/O Banks
    assigning technologies to
    automatically assigning technologies
    configuring
    for Axcelerator
    manually assigning technologies to
    overview
    reset to default settings
    specifying technologies for
    VREF standards
I/O compatibility
    Axcelerator
    ProASIC3
    ProASIC3E
I/O standard
    specifying in I/O Attribute Editor
I/O standards
    Axcelerator
    compatibility
    ProASIC3
    ProASIC3E
I/O threshold
Implementations
Import a core
Import existing core in ACTgen
import_aux
import_source
Importing
   Importing Files
   Importing source files
    auxiliary files
       Importing Auxiliary files
       Importing PDC files
    constraint files
    PDC files
Importing GCF files
Importing SDC files
inclusive regions
    creating
Incrementer (ACTgen macro)
input and output nets
    viewing
input delay
instances
    keeping connected to a net
       Reset net's criticality to default level
       Set net's criticality
Internet
   Internet Features
   Internet Proxy
io_arrival_times
is_design_loaded
is_design_modified
is_design_state_complete
is_source_file_current



keep existing
Keyed lock
Keywords, reserved



layout
    Axcelerator (advanced options in Tcl)
    ProASICPLUS (advanced options in Tcl)
    SX (advanced options in Tcl)
    Tcl command
Layout options eX/SX/SX-A, advanced
Layout options, eX, SX, SX-A
Layout Options, ProASIC and ProASICPLUS
LeonardoSpectrum
   Integration issues
   Synthesizing your design with LeonardoSpectrum
Libero
    Design Flow window
    Log Window
    Log Window preferences
    Preferences
    Project Manager
    Text editor
Libero Gold
Libero Platinum
Libero Platinum Evaluation
Libero Silver
Libero tools
lists
lists and arrays
    in Tcl
Literature
loading
LOC file
local clock
    assigning a net to
LocalClock
    creating
    regions
    renaming
location
    assigning a macro to
    defined
locking
    logic to location
locking pins
    PinEditor in MVN
    PinEditor Standalone
LOG file
Log window
    colors and symbols in MVN
Log Window preferences
Log Window, Preferences in Designer
logic
    assigning to location
    assigning to locations in ChipEditor
    locking to a location in ChipEditor
    locking to location
    moving to other locations
    moving to other locations in ChipEditor
    unassigning from location
Logic menu
    in MVN
logic region
logic regions
Logical Cone
    adding a group of highlighted objects
    adding driven instances to
    adding drivers to
    adding objects to
    changing the name
    clearing all objects from
    creating
       Creating a LogicalCone
       What is a LogicalCone?
    defined
    deleting
    displaying hidden logic
    hiding logic
    removing highlighted objects from
    removing selected objects from
    setting the active cone
logical tab
    hierarchy window
LogicalCone menu
    in MVN
LogicalCone tab
    hierarchy window



macro
    assigning to a location
    assigning to a region
macro cell
    attribute
macro command (GCF)
macros
    assigned and unassigned in ChipEditor
    unassigning from a region
    unassigning from location
    unassigning from region
       Unassign macro from region
       Unassign macros on net from region
Manuals
max_delays/min_delays
Menu
   Creating a new project
   Creating HDL Sources
   Deleting Files
   Design Hierarchy
   File association
   File Manager
   Generating a Bitstream file
   Importing Files
   Menu Commands
   Navigating the work environment
   Opening a project
   Opening a Schematic Source File
   Performing Timing Simulation
   Proxy settings
   Saving
   Version Checking
menus
    in MVN
message bar
messages
MOD file
ModelSim, selecting stimulus file
Modules, finding
More I/O Bank Attributes dialog box
move_region
multi-pass layout
multi pass layout
multipass layout
multiple pass layout
MultiView Navigator
    ChipPlanner tool
    defined
    Edit menu
    File menu
    Format menu
    Help menu
    hierarchy views
    interface
    Log window
    Logic menu
    menus and toolbar buttons
    message bar
    Nets menu
    Package menu
    Schematic menu (MVN)
    selecting objects
    status bar
    tools
    Tools menu
    View menu
    Window menu
    World window
MVN
    Edit menu
    File menu
    Format menu
    Help menu
    Logic menu
    LogicalCone menu
    Nets menu
    Package menu
    Region menu
    Schematic menu
    Tools menu
    View menu
    window menu


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