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Xilinx Answer #8390 : Virtex: How does signal grouping affect the number of SSO a device can support before ground bounce becomes a problem?
Xilinx Answer #8298 : 2.1i Virtex-E Packages - The XV600E FG900 and XV1000E FG1156 packages have bad banking information and missing N.C.
Xilinx Answer #8294 : 2.1i Virtex-E Speed Files - New speed files are available for Virtex-E.
Xilinx Answer #8263 : Virtex CLKDLL VHDL simulation: DLL outputs are not toggling (No output) CLKIN is delayed
Xilinx Answer #8149 : Virtex JTAG - XAPP139 has a misprint on shutdown sequence for AGHIGH command
Xilinx Answer #8114 : Virtex V1000, V2000E BG560: Pin compatibility between V1000 and V2000E
Xilinx Answer #8022 : Virtex Configuration: Toggling /WRITE during serial configuration (DONE does not go high)
Xilinx Answer #8007 : Virtex CLKDLL: Why is it the output jitter spec on the data book is less than the cycle-to-cycle input jitter
Xilinx Answer #8006 : VirtexE CLKDLL: What are the input clock frequency range for VirtexE CLKDLLs to be locked.
Xilinx Answer #8005 : VirtexE CLKDLL: How to create 4X clock using VirtexE CLKDLLs
Xilinx Answer #7976 : Virtex Configuration: DriveDone polarity is incorrect in XAPP151
Xilinx Answer #7891 : Virtex Configuration: How do you know a device is synchronized (sync word is loaded)?
Xilinx Answer #7852 : Virtex CLKDLL: How to make sure the DONE does not go high until the CLKDLL has been locked
Xilinx Answer #7843 : Virtex: How to pull the IOs to 5V with external Pullups
Xilinx Answer #7821 : Virtex SSO: The power/ground pair numbers for various Virtex devices and packages.
Xilinx Answer #7816 : Virtex CLKDLL: 2 CLKDLLs cascaded together could cause the second CLKDLL's outputs invalid
Xilinx Answer #7803 : Virtex Readback/ XAPP138: New equation for calculating readback bit positions
Xilinx Answer #7792 : Virtex CLKDLL timing simulation in MTI: WARNING[1]:No default binding for component : "x_clkdll". ( Generic "tperiod_clkin" is not on the entity)
Xilinx Answer #7702 : Virtex: What's the factory_JF factor on CLKDLL
Xilinx Answer #7510 : Floorplanner 2.1i; VirtexE: Floorplanner crashes when saving a VirtexE400 or greater
Xilinx Answer #7448 : 2.1i Floorplanner: Virtex - Crashes due to stack overflow (PC only).
Xilinx Answer #7419 : How to set the CLKDV_DIVIDE property for the CLKDLL
Xilinx Answer #7412 : Virtex Configuration: Initialization timing for SelectMap (CS/ assertion)
Xilinx Answer #7402 : Virtex CLKDLL: Will the CLKDLL lock if the input frequency is below 25Mhz, if not, what would the outputs of the CLKDLL be like.
Xilinx Answer #7383 : Virtex Configuration: How many loads can the configuration pin CCLK drive?
Xilinx Answer #7341 : 2.1i Virtex Speed Files - Missing Virtex pin-to-pin timing values cause overly optimistic delays
Xilinx Answer #7333 : Virtex Configuration: How can the users enable the Pullups in the IOs during Virtex Configuration.
Xilinx Answer #7327 : 2.1i - Updated Virtex Speed files are available in 2.1i Service Pack 1.
Xilinx Answer #7188 : 2.1i JTAGProgrammer - Looks for the incorrect bsdl file for the 5215 and V800 HQ240.
Xilinx Answer #7180 : Virtex: Things to be careful with when converting 4K designs to Virtex
Xilinx Answer #7172 : Virtex JTAG - How to perform a Readback Verify on the Virtex devices?
Xilinx Answer #7112 : Virtex SelectMAP configuration: Is D0 pin the MSB or LSB
Xilinx Answer #7034 : Virtex: Is it possible to remove Vccint whilst applying Vcco?
Xilinx Answer #7022 : Virtex: Are there Virtex Development boards available?
Xilinx Answer #6971 : Virtex: Virtex devices have potential high current draw for the engineering samples
Xilinx Answer #6934 : Alliance 2.1i Quickstart Guide: Error in Synopsys Virtex run script
Xilinx Answer #6902 : Virtex SSO: how did we come up with the power/ground pairs in the Select IO application notes
Xilinx Answer #6836 : M1.5i: Timing: BLOCKRAMA not being included in RAMS Timegroup in Virtex Timing Constraints
Xilinx Answer #6774 : Virtex: Virtex decoupling capacitor guide for V300
Xilinx Answer #6768 : Virtex: Are Virtex devices Hot-Swap Compliant?
Xilinx Answer #6766 : Virtex: IOB registers clocked by the CLKDLL still use the delay elements on the data path, this will cause longer SETUP delay.
Xilinx Answer #6713 : Virtex: What is the recommended way of setting or resetting FFs in a Virtex design? Do you still need to use STARTUP_VIRTEX block?
Xilinx Answer #6670 : Virtex: What happens to the I/O pins of the Virtex device during power ramp up.
Xilinx Answer #6600 : 2.1i: FPGA Editor: Excessivly long load time for Virtex 1000
Xilinx Answer #6590 : INSTALL 2.1i: Virtex E / Spartan 2(II) : Why are these families greyed out during installation / How can I enable software support for them ?
Xilinx Answer #6565 : 2.1i: Floorplanner: Area constraints can not be placed over blockram bars in virtex/virtexE
Xilinx Answer #6517 : 2.1i: FPGA Editor - Selecting Virtex switch box pins sometimes highlights the pin next to it
Xilinx Answer #6484 : Virtex Configuration: Can CRC be disabled.
Xilinx Answer #6429 : Virtex timing simulation: DUTY_CYCLE_CORRECTION property on BUFGDLL in UCF file may not be seen by sim model
Xilinx Answer #6413 : 2.1i: Fpga_editor; Adding probes to Virtex, the banking information is required.
Xilinx Answer #6353 : 2.1i: Timing: 4kxl/xla & Virtex Min timing & Prorating for Temperature/Voltage
Xilinx Answer #6267 : 1.5i Virtex Timing - Preliminary -4 speed data is available for Virtex
Xilinx Answer #6198 : M1.5i/2.1i: How to utilize the Virtex secondary global clock routing
Xilinx Answer #6110 : Virtex: What are the differences between Vref(R) and Vref(r) in the package drawings
Xilinx Answer #6106 : Virtex : Where can I find I-V curves for Virtex IO's?
Xilinx Answer #5995 : Virtex clkdll: How to simulate CLKDV_DIVIDE in pre-synthesis functional simulation.
Xilinx Answer #5941 : Virtex: For the IO timing numbers, what capacitive load was used?
Xilinx Answer #5894 : Virtex Timing: What is the CLKA -> CLKB setup time for different ports (Tbccs) timing parameter?
Xilinx Answer #5853 : 1.5i SP2 Virtex Device Representation - PCIIOB model needs a bel to drive the PCI pin
Xilinx Answer #5850 : 1.5i SP2 Virtex Device Representation - pci_ce signal in top right and bot right tiles connects to wrong hexes.
Xilinx Answer #5738 : Virtex: What are the temperature sensing diode pins (DXP and DXN)?
Xilinx Answer #5718 : Virtex JTAG - How to program multiple Virtex devices in a JTAG chain
Xilinx Answer #5693 : Virtex: How to use BlockRams in HDL codes
Xilinx Answer #5675 : Virtex: Virtex doesn't have IFDs and OFDs
Xilinx Answer #5662 : Virtex JTAG - How to configure a Virtex device via JTAG with debugging options
Xilinx Answer #5649 : Virtex: How to instantiate CLKDLL in the HDL code
Xilinx Answer #5609 : M1.5i Virtex VHDL simprim model incorrect for SRL16, SRL16_1, SRL16E, and SRL16E_1 models
Xilinx Answer #5605 : VIRTEX, COREGEN: Can 4K COREGen RAMs and ROMs be targeted to Virtex devices?
Xilinx Answer #5589 : Virtex: What are the empty site IO blocks for virtex in fpga_editor.
Xilinx Answer #5539 : M1.5i Virtex Timing - Timing analysis is missing paths to IOBs when PCI used.
Xilinx Answer #5535 : 1.5i Virtex Timing - Speed numbers for horizontal long lines are being underestimated.
Xilinx Answer #5529 : M1.5i Timing - New Virtex Speed Files are available in the 1.5i Service Pack 2.
Xilinx Answer #5519 : 1.5i Package Files - New Virtex package files are available in addition to those available in 1.5i Service pack 2.
Xilinx Answer #5422 : 15i Virtex DRC - DRC incorrectly flags a CLKDLL that drives both CLK0 and CLK2X offchip.
Xilinx Answer #5381 : Virtex Configuration: Issues on configuring Virtex and 4000X devices in daisy chain
Xilinx Answer #5368 : Virtex Configuration : What valid configuration speeds are available for Virtex master serial configuration?
Xilinx Answer #5304 : Virtex: What is an IBUFG and what can I use it for?
Xilinx Answer #5294 : Virtex IBIS models availability
Xilinx Answer #5179 : Does Virtex support LVPECL voltage standard?
Xilinx Answer #5154 : Virtex Configuration: Is it possible to stop CCLK during configuration?
Xilinx Answer #5147 : Virtex JTAG - TAP Advanced Timing Charecteristics
Xilinx Answer #5133 : Virtex: Are there any power sequencing issues for VCCint Vcco Vref?
Xilinx Answer #5109 : Cable - Can Xchecker cable or Parallel cable be used for downloading to any device? ( Virtex or spartan )
Xilinx Answer #5108 : Virtex Configuration: What is the status of user I/O during configuration?
Xilinx Answer #5033 : Virtex: Libraries Guide for Output Banking Rules and configuration is incorrect
Xilinx Answer #5027 : Virtex: Is Partial Reconfiguration and Partial Readback supported in Virtex devices?
Xilinx Answer #4935 : Virtex XAPP132: CLKDLL Jitter Spec in App. note 132 is not clear
Xilinx Answer #4646 : How to change XC4000XLA, XC4000XV, SpartanXL, and VIRTEX output drive current
Xilinx Answer #777 : Virtex: Bypass Capacitors -- what are the requirements?