Abstract Descriptions of the RASSP E&F Course Modules

These modules and associated labs were developed to provide a unique set of educational material for undergraduate and graduate curricula as well as individual learning.

All modules are copyrighted by the SCRA and may only be used for non-commercial educational purposes. Any other use of this information without the express permission of the SCRA is prohibited. All information contained herein may be used freely for educational use. No warranty of any kind is provided or implied, nor is any liability accepted regardless of use. See the disclaimer for more information.


 

  1. Module 10 -- VHDL Basics
  2. Module 11 -- Structural VHDL
  3. Module 12 -- Behavioral VHDL
  4. Module 13 -- Advanced Concepts in VHDL
  5. Module 14 -- Hardware/Software Codesign Overview
  6. Module 21 -- DSP Architectures for RASSP
  7. Module 22 -- Scheduling & Assignment for DSP
  8. Module 23 -- DSP Algorithm Design
  9. Module 25 -- Communication Protocols
  10. Module 29 -- RASSP Methodology Overview
  11. Module 30 -- Requirements and Specifications Modeling 
  12. Module 32 -- Virtual Prototyping using VHDL
  13. Module 43 -- Test Technology Overview 
  14. Module 57 -- Cost Modeling for Embedded Digital Systems Design
  15. Module 59 -- Performance Modeling using VHDL
  16. Module 60 -- Synthesis Using VHDL
  17. Module 61 -- Basic WAVES
  18. Module 62 -- Advanced WAVES

Module 10 -- VHDL Basics

Full Module (Zip format - 6.7MB)

Abstract: The Basic VHDL module introduces the VHSIC Hardware Description Language and its fundamental concepts. VHDL is a language specifically developed to describe digital electronic hardware and its attributes. VHDL is a flexible language that can be applied to many different design situations. This language has several key advantages, including technology independence and a standard language for communication. The module describes many of the advantages of using VHDL and a short history of the language.

Module 11 -- Structural VHDL

Full Module (Zip format - 3.7MB)

Abstract: The Structural VHDL module describes the use of VHDL for describing models in terms of component instantiations and interconnections. Structural VHDL can be appropriate at any level of design. For example, testbenches for completed components are often described using structural VHDL. Furthermore, structural VHDL supports the use of libraries and component reuse.

Module 12 -- Behavioral VHDL

Full Module (Zip format - 4.6MB)

Abstract: The Behavioral VHDL module describes features of the language that describe the behavior of components in response to signals. Behavioral descriptions of hardware utilize software engineering practices and constructs to achieve a functional model. Timing information is not necessary in a behavioral description, although such information certainly can be added.

Module 13 -- Advanced Concepts in VHDL

Full Module (Zip format - 3.6MB)

Abstract:The Advanced Concepts in VHDL module spans a wide range of topics, including several that may be applied to higher levels of design abstraction. Many of these constructs will have been introduced in the first three VHDL modules in this sequence, but this module covers them more comprehensively. Examples of such constructs include signal assignment statements, and the capabilities and differences when they are used as concurrent VHDL statements or sequential VHDL statements. Similarly, the VHDL process is discussed in more detail than in earlier modules. It should also be noted that TEXTIO and shared variables are introduced in this module.

Module 14 -- Hardware/Software Codesign Overview

Full Module (Zip format - 9MB)

Abstract: The Hardware/Software Codesign Overview module is intended to introduce the hardware/software codesign to the practicing design, software, and systems engineers, and to the senior undergraduate or first year graduate student. The module provides key codesign concepts and attempts to show the benefits of the codesign approach over the current design process.

Module 21 -- DSP Architectures for RASSP

Full Module (Zip format - 10.9MB)

Abstract: This module is intended to provide digital signal processing (DSP) architectures both from an historical and RASSP perspective to system and architecture design engineers or to first year graduate students.

Module 22 -- DSP Architectures for RASSP

Full Module (Zip format - 4.6MB)

Abstract: This module is intended to provide to system engineers or to first year graduate students an understanding of DSP algorithm design.

Module 23 -- DSP Algorithm Design

Full Module (Zip format - 12.1MB)

Abstract: This module is intended to provide to system engineers or to first year graduate students an understanding of DSP algorithm design.

Module 25 -- Communication Protocols

Full Module (Zip format - 7.7MB)

Abstract: This module is intended to provide to system engineers or to first year graduate students an understanding of communications in scalable DSP architectures.

Module 29 -- RASSP Methodology Overview

Full Module (Zip format - 9.9MB)

Abstract: The module provides an introduction to how design practice is studied and how improved methodology is implemented and continuously refined. Definitions are provided so that a consistent terminology is established. The module gives a comparison of the pre-RASSP and current RASSP methodology. It also describes potential process improvements and how they may enable the RASSP program to achieve its cost and life-cycle reduction goals. Examples of key improvements such as hardware/software codesign, integrated product development, enterprise integration, virtual prototyping are described. Finally, the module shows the enterprise integration mechanisms used to control and manage design methodology.

Module 30 -- Requirements and Specifications Modeling

Full Module (Zip format - 11.7MB)

Abstract: The Requirements and Specification (RSM) module provides an introduction to the topic of executable requirements and specifications. Their use leads toward a more formalized listing of requirements and specifications than has been traditionally provided.

Module 32 -- Virtual Prototyping using VHDL 

Full Module (Zip format - 14.9MB)

Abstract:In today's engineering design environment, designers are limited in their ability to maximize reuse by the fact that there is no efficient way to search for, access, and integrate reusable design objects across multiple sources; frequently, these potential sources of reusable design data are uncoupled from the design environment. This paper details an approach for managing reusable design objects in a collaborative engineering environment that enables Rapid Prototyping of Application-Specific Signal Processors (RASSP) and the architecture of the RASSP Reuse Data Manager (RRDM), specifically developed to support this approach. 

Module 43 -- Test Technology Overview 

Full Module (Zip format - 11.6MB)

Abstract: This module is intended to provide an overview of digital systems testing to the general design engineer. The module contains basic information on the fundamentals of testing including motivation, current practice, and basic fault modeling techniques. The basic algorithms for test generation and fault simulation for both combinational and sequential designs are then covered followed by a presentation of the theory of IDDQ testing.

Module 57 -- Cost Modeling for Embedded Digital Systems Design 

Full Module (Zip format - 8.4MB)

Abstract:Designers of high-end embedded systems or large volume consumer products are faced with the challenge of rapidly prototyping designs which meet stringent electrical specifications along with tight physical constraints, under restrictive system engineering constraints such as cost time to market (TTM) and resource limitations. The goal is to design a minimum cost system, with consideration of lifecycle costs, as opposed to a minimum cost hardware system. This module describes a new RASSP design methodology called Cost Modeling and its application to the embedded digital system design process. A detailed case study and a thorough description of hardware and software cost estimators are presented. 

Module 59 -- Performance Modeling using VHDL 

Full Module (Zip format - 18.7MB)

Abstract:This module is intended to present the area of system level performance modeling using VHDL. The first section of the module includes a background of performance modeling including the objectives of performance modeling and definitions of common performance modeling terms. Techniques for performance modeling such a Petri Nets, queueing models, and uninterpreted models are covered along with how simulation based performance modeling is implemented in VHDL.

Module 60 -- Synthesis Using VHDL 

Full Module (Zip format - 13.4MB)

Abstract:This module describes how one can synthesize digital systems using VHDL. It does not teach VHDL, nor does it teach synthesis. The former is the task of earlier modules, while the latter is the task of various synthesis tools that take in an input specification in VHDL and process it.

Module 61 -- Basic WAVES 

Full Module (Zip format - 7.8MB)

Abstract: The Basic WAVES module discusses the basic idea of a VHDL testbench, and its use in the design process. As part of the testbench discussion, the standard for VHDL Waveform and Vector Exchange (WAVES) - IEEE Std 1029.1 1996 - is introduced as a methodology for describing the input stimulus to be applied to the Unit Under Test (UUT) and the expected outputs which are compared to the actual outputs in the testbench. The module covers all the basic WAVES concepts, which include the WAVES libraries and functions, the WAVES test vector file format, and the WAVES test set. 

Module 62 -- Advanced WAVES

Full Module (Zip format - 4.0MB)

Module Objectives:

Abstract: The Advanced WAVES module continues the discussions of the Basic WAVES modules.