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Xilinx Answer #7779 : LogiCORE PCI: Simulating the LogiCORE PCI interface in VHDL causes some back-end signals to go unknown
Xilinx Answer #7511 : LogiCORE PCI: Updating HOT II card from v1 to v2 after accidental erasure of the Configuration Flash Memory
Xilinx Answer #7300 : LogiCORE PCI: Inserting initial latency in a target design
Xilinx Answer #7152 : LogiCORE PCI64 Virtex (v3.x): Plugging a 64-bit card in a 32-bit slot
Xilinx Answer #6809 : LogiCORE PCI: parity lines appear to be in conflict or not driven at all during simulation
Xilinx Answer #6759 : LogiCORE PCI32 Virtex: VHDL version of the core requires more slices than the Verilog version
Xilinx Answer #6696 : LogiCORE PCI: All signals designated s/t/s in the spec must have pull-ups on them during simulation
Xilinx Answer #6691 : LogiCORE PCI 64/66 Virtex: VHDL- 2040 Warnings about unsupported attributes (syn_edif_bit_format, syn_edif_scalar_format, black_box)
Xilinx Answer #6586 : LogiCORE PCI Data book : Incorrect pin description for Spartan/4KXLT devices
Xilinx Answer #6206 : LogiCORE PCI64 Virtex (v3.0): Data bits in the first data phase of a burst transaction may be incorrect
Xilinx Answer #5991 : LogiCORE PCI Virtex (v3.0): Is timing simulation supported for the LogiCORE PCI64 Virtex?
Xilinx Answer #5989 : LogiCORE PCI64 Virtex (v3.0): 66 MHz implementation issues
Xilinx Answer #5988 : LogiCORE PCI64 Virtex (v3.0): What version of Xilinx software is required by the LogiCORE PCI64 Virtex?
Xilinx Answer #5797 : LogiCORE PCI32 Spartan: New UCF files for use with the M1.5i release are now available
Xilinx Answer #5705 : LogiCORE PCI: Can the top-level of hierarchy be modified in a Xilinx PCI design?
Xilinx Answer #5688 : LogiCORE PCI: STOP_IO asserted, S_TERM low, & S_READY is high in target app
Xilinx Answer #5595 : LogiCORE PCI32 4000/Spartan: VHDL synthesis/simulation with PCI LogiCORE v2.0, Synplify 5.0.8, & M1.5i
Xilinx Answer #5442 : LogiCORE PCI32 Spartan: How do you use our Spartan core as a target-only core?
Xilinx Answer #5441 : LogiCORE PCI: What addressing mode is supported during memory burst transactions?
Xilinx Answer #5299 : LogiCORE PCI: What loads should be used when calculating maximum clock-to-out timing?
Xilinx Answer #5291 : LogiCORE PCI32 Spartan: Setup constraints for the PQ208 package relaxed
Xilinx Answer #5290 : LogiCORE PCI32 Spartan: PCI pinout for PQ208 not compatible with 4013XL PQ208
Xilinx Answer #5289 : LogiCORE PCI32 Spartan: Timing simulation may issue errors while simulating ping
Xilinx Answer #5276 : LogiCORE PCI32 4000: The recorder module in compliance testbench does not get bound in the Express Flow
Xilinx Answer #5275 : LogiCORE PCI32 4000: The timespec "USER_PADS" in the UCF files is incorrect for Viewlogic Flow
Xilinx Answer #5272 : LogiCORE PCI32 4000XLT: Incorrect 'MIN' clock delay value used to compute the setup time
Xilinx Answer #5261 : LogiCORE PCI: Implementing CompactPCI HotSwap with Xilinx LogiCORE PCI solution
Xilinx Answer #5254 : LogiCORE PCI32 4000/Spartan: Are the XC4000XLT and Spartan devices 3.3V/5V PCI compliant?
Xilinx Answer #5253 : LogiCORE PCI: Device Resource Utilization summary
Xilinx Answer #5247 : LogiCORE PCI: Xilinx Software & Synthesis tools support
Xilinx Answer #5246 : LogiCORE PCI: Supported Device/Package/Speed Grades
Xilinx Answer #5239 : LogiCORE PCI64 Virtex: Can the PCI64 interface support 32 bit applications?
Xilinx Answer #5229 : LogiCORE PCI: How do the REQ#/GNT#/RST# lines in the LogiCORE interface act?
Xilinx Answer #5227 : LogiCORE PCI: How does the LogiCORE interface handle target abort?
Xilinx Answer #5217 : CORES and IP: availability of VXI bus cores
Xilinx Answer #5214 : LogiCORE PCI: Does the LogiCORE interface support interrupts?
Xilinx Answer #5202 : LogiCORE PCI: How does the LogiCORE interface handle single cycle grants?
Xilinx Answer #5193 : LogiCORE PCI: All about master aborts (abnormal terminations)
Xilinx Answer #5171 : LogiCORE PCI: 0.7 or 0.75 multiplication factor in the UCF files
Xilinx Answer #5160 : LogiCORE PCI: How many BARs does the PCI interface support?
Xilinx Answer #5159 : LogiCORE PCI: Is snooping supported?
Xilinx Answer #5134 : LogiCORE PCI: Harmless warnings during Cadence Verilog-XL simulation
Xilinx Answer #5129 : LogiCORE PCI32: What is the advantage of using the BAR_x_WR/RD signals as refered to in the User Guide?
Xilinx Answer #5128 : LogiCORE PCI: When is the S_WRDN signal valid?
Xilinx Answer #5127 : LogiCORE PCI User/Design Guide: Key to various states depicted in waveforms
Xilinx Answer #5126 : LogiCORE PCI: PCI Bus Configuration Timing Details
Xilinx Answer #5125 : LogiCORE PCI: Can the I/O space in the PCI core be set to greater than 256 bytes?
Xilinx Answer #5094 : LogiCORE PCI: All about Zero and One wait states
Xilinx Answer #5055 : LogiCORE PCI: Guide does not work if M/S_SRC_EN signals are unused
Xilinx Answer #4857 : ***OBSOLETE SOLUTION*** LogiCORE PCI32 4000/Spartan (v2.0): Can the CLKE signal on the PCI CORE be used to drive user logic?
Xilinx Answer #4856 : LogiCORE PCI: Target core behavior when the 1st data phase needs more than 16 clocks?
Xilinx Answer #4836 : LogiCORE PCI: does the core come with a behavioral simulation model?
Xilinx Answer #4835 : LogiCORE PCI: Does the PCI Interface support multi-function (multifunction) capability?
Xilinx Answer #4647 : LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, Exemplar Leonardo v4.2.2 & M1.4.12
Xilinx Answer #3762 : LogiCORE PCI: What is the functionality of latency timer?
Xilinx Answer #3552 : LogiCORE PCI: Power Management - Description of Function Power States
Xilinx Answer #3549 : LogiCORE PCI: Base Address Register attributes
Xilinx Answer #3547 : LogiCORE PCI32 4000: VHDL/Verilog synthesis/simulation with PCI LogiCORE v2.0, Synplify 5.0 & M1.4.12
Xilinx Answer #3544 : LogiCORE PCI32 4000: XC4000XLT Clamp (Vtt) diode specification
Xilinx Answer #3543 : LogiCORE PCI: Why can't an I/O Base Address Register be set to > 256 bytes on an x86 processor?
Xilinx Answer #3414 : LogiCORE PCI32 4000: 4062XLT BG432 -09 Ping example: Timing simulation using VSS causes failure
Xilinx Answer #3268 : LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v2.0.2, & M1.4.12
Xilinx Answer #3267 : LogiCORE PCI32 4000: Verilog synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v2.0.2, & M1.4.12
Xilinx Answer #3108 : LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v1.2, & M1.3.7
Xilinx Answer #3105 : LogiCORE PCI32 4000: Verilog synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v1.2, & M1.3.7
Xilinx Answer #3103 : LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Compiler & VSS v1997.08, and M1.3.7
Xilinx Answer #3099 : LogiCORE PCI32 4000: Verilog synthesis/simulation with PCI LogiCORE v2.0, FPGA Compiler v1997.08, VerilogXL v2.5, and M1.3.7
Xilinx Answer #1369 : LogiCORE PCI: Information on pipelining signals in PCI designs
Xilinx Answer #1229 : LogiCORE PCI32 4000/Spartan: Should i/o's be set to TTL or CMOS for the 4KXLT or Spartan device?
Xilinx Answer #1156 : LogiCORE PCI: Does it support Big or Little Endians?
Xilinx Answer #644 : LogiCORE PCI: How to obtain copies of the PCI specification (from the PCI SIG)