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Xilinx Answer #7095 : Xinfo 2.0: Self Diagnostic Tool to help debug/troubleshoot issues (i.e - Install, Env Variables, GUI's, etc...) - PC ONLY
Xilinx Answer #6733 : Vitex BRAM VHDL simulation: setup violation on CLK A with respect to CLK B, or setup violation on CLKB with respect to CLK A
Xilinx Answer #6535 : MODELSIM VLOG: ERROR: ../../../<design>.v: Port 'OUT' not found in module
Xilinx Answer #6459 : Block Ram simulation show outputs on a read port as 'X', even though doing read only (BRAM)
Xilinx Answer #6443 : Where can I find year 2000 (Y2K) compliancy of Xilinx Software?
Xilinx Answer #6173 : 2.1i: XACT Command "lca2xnf -s" is no longer available, but can be replaced by "speedprint -s" command.
Xilinx Answer #4837 : Floorplanner FAQ: Which users will best benefit from using the Floorplanner
Xilinx Answer #4765 : PC environment variables, license: Environment variables are not set; eg Cannot find license file -1,73:2
Xilinx Answer #4692 : Floorplanner: General Design Flows
Xilinx Answer #4417 : XXACTD: fatal error 1062 :license checkout for feature ppr-hppa failed, expired
Xilinx Answer #4415 : PPR WARNING 7028: How to set Flagblk CLB_Disable_SR_Q on Flops in Xdelay
Xilinx Answer #3982 : FPGA Hardware: Where to get ESD information.
Xilinx Answer #3709 : XC4010E CB196: pin locations for the XC4010E CB196 are incorrect
Xilinx Answer #3416 : Constraints: How to specify a specific CLB to LOC an instance to.
Xilinx Answer #3067 : Migrating XBLOX designs to M1: XBLOX2M1 archive now exists on ftp site
Xilinx Answer #3050 : SIMPRIMS: Why do the models for the X_RAMD16 have only one output port?
Xilinx Answer #2800 : XC3000: XNFPREP 5.2.1: Segmentation Fault(core dumped)
Xilinx Answer #2726 : XBLOX: ACCUM - effects of LOAD on C_OUT and OVFL
Xilinx Answer #2496 : MAKEBITS 5.2.1: Problem with xc5200 devices when Makebits -t option is used.
Xilinx Answer #2459 : PPR error 1476 :error in mxn file:Illegal mxn name on line <> of file <> in data high.pb
Xilinx Answer #2436 : PPR 5.2.1: error 11221: design name 12345 is illegal
Xilinx Answer #2205 : PPR 5.x: Possible cause of ERROR 9929
Xilinx Answer #2203 : Xsimmake reports no license for schematic in Pro Series
Xilinx Answer #2201 : ppr Error 9004: The IOPAD must be placed in a dedicated pad location.
Xilinx Answer #2190 : XDELAY 5.2.1: Doesn't IGNORE the path specify by the TIMESPEC IGNORE attribute
Xilinx Answer #2173 : PPR: FATAL ERROR: The msg set for "msg" does not exist
Xilinx Answer #2153 : FLOORPLANNER-XACT: Cannot see STARTUP, READBACK, of BSCAN symbols in my foorplanner.
Xilinx Answer #2135 : Xmake fails during OrCAD Annotate: program does not support incremental annotation
Xilinx Answer #2094 : PPR 5.2.x: XC5200 design with Readback gives ERROR 9905: NET "$I417/CLK" has no source
Xilinx Answer #2091 : Makebits 5.2.1: XDE, XDM and commandline differences in Default options for a 4000e and a 5200 part
Xilinx Answer #2090 : XNFPREP 5.2.1: error 4572 and error 4573
Xilinx Answer #2083 : XDM: XC4025E part is not displayed, even though partlist.xct is correct
Xilinx Answer #2074 : LCA2XNF 5.2.1: Outputs an Inaccurate .xnf file
Xilinx Answer #2066 : **Obsolete**Foundation Schematic: PPR ERROR 9028 when using COMPMC8 macro in 5200 design
Xilinx Answer #2062 : XBLOX: Running XBLOX on remote Solaris machine gives "UNIX error ENOENT" after loading defaults.qofRunning XBLOX for Sun4 on Solaris on remote machine gives "UNIX error ENOENT" after loading de faults.qof
Xilinx Answer #2051 : XNFPREP 5.2.1: Errors 7822, 7854 from constraints file TIMESPEC
Xilinx Answer #2050 : XNFMERGE 5.2.1: INTERNAL ERROR: 293
Xilinx Answer #2043 : FLOORPLANNER-XACT: Driver problem (macxw4.drv) with Win95
Xilinx Answer #2011 : XSimmake 5.2.1, Workview Office 7.3.0 or newer: check/vsm_ngui fail under XSimmake script
Xilinx Answer #1988 : XC4000E: Creating Synchronous or Dual port RAM for MemGen
Xilinx Answer #1980 : PPR 5.2.x: Relaxing PPR timespecs in xactinit.dat
Xilinx Answer #1970 : XMAKE 5.x: File beltypes.dat not found
Xilinx Answer #1964 : XNF specification: Naming Conventions for nets, buses, components and pins
Xilinx Answer #1963 : PPR: Design not routing (unroutes) because placement is to tightly packed.
Xilinx Answer #1954 : XNFMERGE: how does it recognize what is a primitive vs. what is a macro in an XNF file?
Xilinx Answer #1940 : XNFMERGE : Warning 285. Net names and symbol pin names do not match.
Xilinx Answer #1937 : PPR 5.2.1: Possible Cause of PPR error 9016 if using Floorplanner
Xilinx Answer #1932 : XNFPREP 6.0.1: Error 3525:Symbol `name' (type = INFF, output signal = WS0) has invalid pin CE
Xilinx Answer #1789 : xmake 6.0.1: l.s01.1: /usr/xilinx/bin/sparc/xsifix: fatal: relocation error: symbol not found
Xilinx Answer #1772 : Makeprom: Where can I find a Workstation version of psplit?
Xilinx Answer #1713 : win 95: Simulation Utility fails with "Path/File access error"
Xilinx Answer #1680 : XNFPREP 5.2.1: Error 7859:'C2P' type TS attribute 'TSxx' need an associated TS flag attached to a net or pin.
Xilinx Answer #1676 : PPR 5.2.1: Hangs the machine, doesn't respond
Xilinx Answer #1671 : XDM 5.2: The Translate Menu does not have XEMAKE underneath it
Xilinx Answer #1666 : XABEL,XACT-CPLD: What Xilinx packages come with XABEL(DS371) and XACT-CPLD(DS560)?
Xilinx Answer #1621 : PPR, XDELAY: Why timing/performance results differ in the two report files.
Xilinx Answer #1617 : XCHECKER SOFTWARE: What is the difference between xck88.exe and xchecker.exe?
Xilinx Answer #1615 : XCHECKER SOFTWARE 5.2.1: What are the system memory requirement in order to run?
Xilinx Answer #1585 : UNISIMS/SIMPRIMS: BUFE, BUFT behaves differently for fron-end and back-end simulation for Virtex
Xilinx Answer #1576 : XDE issues messages on non-applicable TNM and Timespecs
Xilinx Answer #1568 : XNFMERGE 5.2.0: FAST, MEDFAST, MEDSLOW properties dropped when attached to OFD/OUTFF/OBUF/OBUFT macros
Xilinx Answer #1567 : XC3000/XC4000/XC52000: XACT 5.2- XNFMERGE: S attribute attached to OBUF output at top level gets dropped
Xilinx Answer #1566 : FLOORPLANNER-XACT: Printing Problems in Windows 95
Xilinx Answer #1557 : XNFBA error 301: Possible workaround
Xilinx Answer #1516 : PPR error 6103: Possible Cause of "The EQN symbol ... has an invalid pin ... "
Xilinx Answer #1506 : XACT: How to LOC (lock) pins and reserve/restrict pins via a constraints file
Xilinx Answer #1476 : PRE-UNIFIED CARRY symbol: Not supported
Xilinx Answer #1469 : FPGA Configuration: XChecker: "ERROR 264: DONE signal did not go high"
Xilinx Answer #1468 : XBLOX 5.x: Possible simulation problems if the labels are missing
Xilinx Answer #1461 : XDE: Why is the INIT value shown for RAM/ROM different than what I specified?
Xilinx Answer #1454 : XC5200: LCA2XNF v5.2.1 writes out 5-input logic gates for XC5200
Xilinx Answer #1435 : Invoking XDM requires to be logged in as root
Xilinx Answer #1419 : PPR error 5812 - Constraint file error
Xilinx Answer #1418 : FLOORPLANNER-XACT: ATI video driver may cause general protection fault
Xilinx Answer #1416 : CHECK or XNFPREP fail because of invalid characters in signal names
Xilinx Answer #1402 : XChecker: "Done did not go high" for 5200 download.
Xilinx Answer #1385 : XCHECKER 5.2.1: Error 265 : INIT signal is low.
Xilinx Answer #1354 : My CBxxx counter is not fast enough for my design
Xilinx Answer #1344 : XC4000: XDE- editlca: find RxCx returns the wrong block in 4013(E) - 4025(E)
Xilinx Answer #1303 : XNFPREP 5.2.x: ERROR 3582 issued because XC5200 does not have IOB registers
Xilinx Answer #1293 : XC5200: UserClk must be enabled in Makebits before CK_DIV will be used.
Xilinx Answer #1287 : XBLOX 5.x: Internal error 20224: representation_error
Xilinx Answer #1269 : XC4000E: MEMGEN always uses the part 4005EPG156 for Synchronous Rams.
Xilinx Answer #1265 : PPR 5.x: ERROR 5812
Xilinx Answer #1239 : Xsimmake (5.2.x) patch needed for Workview Office (Windows 95 and NT)
Xilinx Answer #1199 : LCA2XNF: Warning:23 pins do not have routing delays, PPR shows 0 unroutes
Xilinx Answer #1191 : PPR 5.2.x: abnormal program termination: memory protection fault in Windows95 (Win 95)
Xilinx Answer #1187 : XNFPREP failes due to capital letters in filename
Xilinx Answer #1185 : PPR 5.2.0: ERROR 1582: Error in writing LCA data to memory:
Xilinx Answer #1165 : XPP, HW-112: XPP v5.2.0 does not recognize 4020EHQ240 .bit file
Xilinx Answer #1157 : Powerview 6.0 has a different default VSM option, requires new file
Xilinx Answer #1154 : PPR 5.2: Error 5814: Constraint file block name '[name]' could not be found in net list
Xilinx Answer #1141 : XSIMMAKE creates schematic symbols with double bounded bus pins.
Xilinx Answer #1138 : Amount of memory that is required by XACT/XDE 5.2.1
Xilinx Answer #1134 : FLOORPLANNER-XACT: Unable to invoke the floorplanner from the Design Manager
Xilinx Answer #1117 : XC4000: XACT 5.2- MEMWIN / Memory Generator does not support Dual Port RAMs
Xilinx Answer #1104 : MAKEBITS TIE--Should all designs be tied?
Xilinx Answer #1097 : The DOS based XCHECKER software may not run over a NOVELL network.
Xilinx Answer #1085 : LCA2XNF may use unit delays (functional) in timing simulation flow
Xilinx Answer #1071 : XACTstep Libraries Guide: TS identifier in Mentor NOT limited to 01, 02, etc.
Xilinx Answer #1069 : How to specify TIMESPECs
Xilinx Answer #1066 : XBLOX 5.x: ONE_HOT COUNTER with unconnected UP/DN pin results in DOWN counter
Xilinx Answer #1065 : XC3000/XC4000/XC5200: How to select cmos input thresholds for FPGAs
Xilinx Answer #1051 : XNFPREP: Error 3526: Illegally inverted pin with XBLOX SYNC_RAM symbol
Xilinx Answer #1043 : Foundation: Possible causes of XNFMERGE Warning 285
Xilinx Answer #1033 : XC3000: Place Block syntax for APR is different than for PPR, results in APR Error 213.
Xilinx Answer #1016 : Using MakeTNM and addTNM in order to add TNMS to a .XNF file.
Xilinx Answer #1011 : PPR issues error 9025 on 5k design; FPLAN finds no errors
Xilinx Answer #989 : XCHECKER 5.2.1: Files required for standalone XChecker software (PC or Workstation).
Xilinx Answer #977 : FLOORPLANNER-XACT: Unable to load file <design>.lca / FPLAN : ERROR 1576 : Error in LCA file
Xilinx Answer #974 : ** OBSOLETE ** XNFPREP 5.20: changes "INIT=S" to lower case "init=S", which PPR 5.20 ignores
Xilinx Answer #969 : XSIMMAKE: Check.exe fails while using the simulation utility in Windows.
Xilinx Answer #965 : Place & Route in Flow Engine produces PPR error 5603: "Unable to open .xtf file"
Xilinx Answer #964 : XChecker 5.2.1: Downloading a valid bitstream in DOS produces a frame error - INIT goes low
Xilinx Answer #960 : MAKEBITS, MAKEPROM v5.2: bit file and prom file size may differ from that generated with v5.1/5.0 software.
Xilinx Answer #952 : PPR: Guidelines for using manually edited LCAs as PPR guide files
Xilinx Answer #945 : PPR 5.20: Support for dual phase clocks in 3000A devices
Xilinx Answer #942 : XNFPREP error 3527: possible causes if using Foundation
Xilinx Answer #928 : PPR, XNFPREP: INIT=S property ignored because INIT converted to "init"
Xilinx Answer #915 : PPR : Error 5606 : Unable to create output MXN or PIC cell.
Xilinx Answer #906 : PPR Error #1173 fplan.p file cannot be found when PPR is Run From FloorPlanner.
Xilinx Answer #898 : check -p sdesign.1 fails because of invalid/overlapping nets
Xilinx Answer #883 : XCHECKER cannot pull the DONE pin LOW.
Xilinx Answer #882 : MAKEPROM: INTERNAL PROGRAM ERROR when ran on a xc5200 device.
Xilinx Answer #821 : XC3000/XC4000/XC5200: xde in vesa16 mode requires 800x600x16 color support
Xilinx Answer #808 : XDM 5.x: XC3100A-09 not selectable, gives "-9 is not a valid speed grade"
Xilinx Answer #794 : XDE/EDIT LCA 5.2: INTERNAL PROGRAM ERROR (Please contact support personnel): bprog: 19,6: 10: not a pip
Xilinx Answer #789 : How to simulate with Workview Office and XACTstep 6.0.1
Xilinx Answer #780 : MAKEBITS 5.2.X: length count differs due to new default -lc=aligned_lc
Xilinx Answer #778 : Benchmark. PPR runtime on various machines
Xilinx Answer #761 : POWER.EXE may slow down PPR
Xilinx Answer #757 : PPR ignores timing constraints when invoked from the command line
Xilinx Answer #747 : FLOORPLANNER-XACT: The Floorplanner may cause segmentation faults/core dumps
Xilinx Answer #738 : XBLOX 5.x: internal error 20224, representation_error
Xilinx Answer #734 : SIMPRIMS: What is the usage of the X_SUH cell?
Xilinx Answer #701 : 6.0: Memory requirements for various parts.
Xilinx Answer #694 : PPR 5.2.0 issues error 5846 on designs where the aclk or gclk is fed from a clb and the clb location is constrained
Xilinx Answer #691 : XSimMake: How to modify flows to run user programs, scripts, or batch files
Xilinx Answer #677 : PPR 5.2.0, 4000E: Data read during Dual Port RAM simultaneous read and write is incorrect
Xilinx Answer #662 : FLOORPLANNER-XACT: Saving a file to a write protected floppy results in a system error.
Xilinx Answer #661 : FLOORPLANNER-XACT: Will not load file from directory that only has group write permission.
Xilinx Answer #660 : FLOORPLANNER-XACT: Printing hangs the system if no default printer is selected.
Xilinx Answer #659 : FLOORPLANNER-XACT: Multiple periods are not supported in filenames
Xilinx Answer #658 : FLOORPLANNER-XACT: Warning 12926 : constraints file read that contains wildcards.
Xilinx Answer #657 : FLOORPLANNER-XACT: PPR May Fail Due to Invalid Floorplanner Placement
Xilinx Answer #653 : Program under Windows error: GROWSTUB General Protection Fault, pointer.dll
Xilinx Answer #651 : PPR Error 5802: PGA package pin location "Uxx" assumed to be unbonded
Xilinx Answer #606 : XDELAY 5.2.1: How to make all the TSspecs in -SelectSpec unhighlighted
Xilinx Answer #584 : PPR 5.x guide may leave clock enable on flip-flops where CE was removed (3000A)
Xilinx Answer #530 : PPR 5.0,5.1: Possible cause of bad grouping using statements on TIMEGRP symbol
Xilinx Answer #529 : Possible cause of XSIMMAKE 5.0 ERROR 7 (sh: 17067 Memory fault - core dumped)
Xilinx Answer #527 : PPR 5.1:Possible cause of ERROR 9015 on XC3000 design (placement constraints)
Xilinx Answer #526 : MAKEPROM 5.1: 'Address is greater than 64k' error, using MCS format - what to do
Xilinx Answer #525 : PPR 5.0: produces ERROR 1173, 'can't find .tpm file for the NOTH_PICMAP cell'
Xilinx Answer #524 : PPR 5.1: Use of 5.0 guide file with XBLOX counters causes ERROR 9081
Xilinx Answer #520 : PPR 5.0: PPR 5.0 'HP_anneal' HP-PA version expiration override code
Xilinx Answer #514 : PPR 5.1, XC3000A: PPR Routes 3000A Pip in the Wrong Direction
Xilinx Answer #500 : PPR, WIR2XNF 5.0: Possible cause of PPR error 9016: use of -f option
Xilinx Answer #495 : XSIMMAKE 5.0, 5.1, 5.2: Possible cause of XNFBA error 301.
Xilinx Answer #483 : PPR 5.0: Possible cause of Error 5607: Design has not been flattened
Xilinx Answer #478 : PPR 5.0 and Timespec: How to use the timespec 'ignore' property
Xilinx Answer #466 : PPR 5.0 will not guide correctly with a pre-XACT 5.0 lca file
Xilinx Answer #464 : XSIMMAKE 5.2: XSIMMAKE may run XBLOX on a design even after you remove all XBLOX logic
Xilinx Answer #452 : XNFPREP 5.0 issues error 7859 on a Timespec attribute.
Xilinx Answer #440 : XC2000: XDE 5.0: About "Can't open 2018.spd" message.
Xilinx Answer #437 : PPR 5.0:Possible cause of 'Error 5805: Constraints to mapping symbol conflict'
Xilinx Answer #436 : XPP 5.0: Why does it always ask for the "first" device?
Xilinx Answer #431 : XNFPREP: Possible cause of 'ERROR 1303, comma required' on Orcad designs
Xilinx Answer #420 : PPR 5.0: TNM placed on a net does not get traced forward to all elements
Xilinx Answer #419 : PPR 5.0: Constraining RPMs in a CST file (includes RPMCON instructions)
Xilinx Answer #416 : PPR 5.0: using XDE-EDITLCA colorblk command in guide file may cause error 12205
Xilinx Answer #412 : PPR 5.0: PPR (possibly other programs) gives PHARLAP error when invoked
Xilinx Answer #409 : PPR 5.2: Defining point-to-point timespecs in cst file
Xilinx Answer #400 : XSIMMAKE/XDRAW 5.2: XSIMMAKE seemingly halts exectution during XDRAW
Xilinx Answer #392 : XSIMMAKE 5.2, Viewlogic: Possible cause of ERROR 7
Xilinx Answer #388 : PPR 5.0, 3064APG132 package: Possible cause of Error 5807
Xilinx Answer #377 : XDM 5.0 only allows you to set APR seed value of 0-99
Xilinx Answer #374 : XDELAY 5.0:SelectSpec option setting not saved in template file.
Xilinx Answer #372 : XDM 5.2: Symgen does not appear in menus if XC7200 or XC7300 part is selected
Xilinx Answer #370 : XDELAY 5.2: Correlating delays through TBUFs with data book values
Xilinx Answer #366 : XMAKE 5.2:Error 3515,3516 about mixed libraries when -L used on old design
Xilinx Answer #361 : PPR 5.0: Notplace * constraint with MD0, MD1 pins gives errors 9016, 9034
Xilinx Answer #360 : PPR 5.0: Possible cause of Segmentation or Memory Protection faults (TNMs)
Xilinx Answer #345 : PPR 5.0: Getting report of timespec failed paths BEFORE routing phase
Xilinx Answer #334 : XNFPREP 5.0: IOB primitives w/inverted outputs give PPR ERROR 1305
Xilinx Answer #328 : PPR 5.0: CST file constraints do not override schematic constraints
Xilinx Answer #326 : PPR 5.0: Methods to reduce PPR runtime
Xilinx Answer #316 : Xsimmake 5.2: Error message says to run functional simulation
Xilinx Answer #314 : XBLOX 5.x: Error message regarding CAST (20051, 20141, 20142, 20184, 20177, 20199, 20336)
Xilinx Answer #311 : PPR 5.0: PPR Error 9062: Global Buffer Driven by IO, IBUF
Xilinx Answer #306 : HM2RPM: Running with DFLT_LOGIC=TRUE may cause errors in XNFPREP, PPR
Xilinx Answer #305 : SYMGEN 5.2, XDM 5.2: XDM Appears to hang when SYMGEN is invoked
Xilinx Answer #303 : PPR 5.0: About 'HEAPMGMT - heap error #6' under windows DOS shell
Xilinx Answer #297 : PPR 5.0: Information for users upgrading from APR for 3000A designs
Xilinx Answer #287 : XDM, PPR 5.2: XDM forces the use of invalid default TIMESPEC syntax
Xilinx Answer #285 : PPR 5.2: Memory requirements for various parts
Xilinx Answer #284 : PPR 5.2: What are the SaveSig (S), eXternal (X) netflags?
Xilinx Answer #267 : XPP 5.0.0: -d option programs proms incorrectly if .bit file is split across multiple proms
Xilinx Answer #260 : XBLOX 5.x: Implementing DATA_REG in IOB resources
Xilinx Answer #253 : XSIMMAKE may hang up while running CHECK if viewdraw.ini has invalid library
Xilinx Answer #215 : Prolink may hang after blank check on some pcs