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Xilinx Answer #6862 : 2.1i Install: Design Manager not found after removing 1.5i software
Xilinx Answer #6495 : Design Manager/Flow Engine M1.5i: ERROR:hi1 - No design name specified. Use "hitop -f design.ngd
Xilinx Answer #6223 : 2.1i/1.5 Design Manager (WS ONLY) - Selecting "Browse" dialog hangs application, Flow Engine hangs upon starting.....
Xilinx Answer #5993 : Design Manager F1.5i: Cannot locate fndtn/active/exe/appcn32.dll, suspro32.dll, s95log.dll
Xilinx Answer #5767 : Design Manager M1.5: Unix - Cannot execute binary file when trying to run design manager . . . Exec format error
Xilinx Answer #5602 : Design Manager M1: Failed to create empty document
Xilinx Answer #5549 : M1.5i Virtex Timing - Timing Engine incorrectly propagates PERIOD thru 2 CLKDLLs in Virtex.
Xilinx Answer #5467 : Error Baspp - This design contains logic. . .correlated back annotation is not supported
Xilinx Answer #5314 : F1.5i Project Manager:Cannot find license for constraints editor
Xilinx Answer #5169 : Design Manager M1.4/M1.5/i: MPPR does not create revision directories; revisions don't appear in DM's view
Xilinx Answer #5035 : M1.5 Spartan mapper can not fit design that fit in M1.4.
Xilinx Answer #4890 : DESIGN MANAGER: error:basut:221 - switch "-tf" is not allowed.
Xilinx Answer #4884 : Design Manager M1.5: [windu_registryd] Failed to open logfile windu_reg.log
Xilinx Answer #4743 : Design Manager M1.5: 'Set Guide file(s)' option is greyed out when a project is initially created
Xilinx Answer #4614 : M1.5 LCA2NCD: Error: baslc 30:can't load LCA: bad design record (part_number)
Xilinx Answer #4596 : Design Manager M1.5i: Setting up your Web Browser Preferences so that multiple browsers are not invoked (Workstation ONLY)
Xilinx Answer #4563 : 2.1i/1.5i Design Manager: Wind/U Warning (240): Unknown locale specified locale:C LANGUAGE: UNDEFINED SUBLANGUAGE:
Xilinx Answer #4490 : A1.5 XSI Application Note: Synopsys/Xilinx High Density Design Methodology Using FPGA Compiler
Xilinx Answer #4313 : Timing Summary: What do the design statistics mean, maximum/minimum arrival input/output time
Xilinx Answer #4285 : Design Manager M1: What are the recommended set of files to be archived in order to restore an M1 design?
Xilinx Answer #4252 : Design Manager/Template Manager M1.5: Flow Engine reads incorrect settings if a default template is customized
Xilinx Answer #4147 : Design Manager/Template Manager M1.5: Cannot delete the program/option within Template Manager
Xilinx Answer #4137 : Design Manager M1.5: Multi-pass place and route (MPPR) naming convention has changed (ex - p1_rev_2_3_4)
Xilinx Answer #4131 : Design Manager M1.5: New version is created instead of new revision even though the input design netlist has not changed
Xilinx Answer #4064 : M! Design Manager: What command line options can be used to invoke the Design Manager ?
Xilinx Answer #3986 : Design Manager M1: The specified part is either invalid or not supported (XC95***/XL)
Xilinx Answer #3734 : When using Turns Engine, you are unable to nice the PARs that are spawned off
Xilinx Answer #3669 : Flow Engine M1: Error in reading flow definition file; unable to continue
Xilinx Answer #3610 : Design Manager M1/6.0.1: How to change properties of the default Web Browser/Report Browser/ Editor
Xilinx Answer #3588 : Design Manager/Template Manager M1.4: Customized options not added to template.
Xilinx Answer #3578 : Design Manager M1: eXceed - Invoking the GUI produces wind/u error 192: X-Resource: DefaultGUIFontSpec
Xilinx Answer #3344 : M1.4 Turns Engine: ERROR - PING cannot reach node 'node_name'
Xilinx Answer #3295 : M1.4,F1.5,2.1i Security: How can I get the license manager to run as a service on NT?
Xilinx Answer #3183 : Design Manager 1.5i/2.1i: WS ONLY - Selecting browse button hangs the DM, Flow Engine doesn't appear but is running
Xilinx Answer #3096 : M1: How to convert an existing XACTstep 5.x design to use the M1.x tools
Xilinx Answer #3038 : Design Manager M1.3/M1.4/M1.5 - How to specify a cost table level in the M1 Design Manager GUI (MPPR)
Xilinx Answer #2942 : 2.1i/1.5i Design Manager - My input design netlist has moved locations/drives, how do I transfer/restore my project information ?
Xilinx Answer #2887 : 2.1i/1.5i Design Manager: FPGA Multi-Pass Place and Route (MPPR) greyed out
Xilinx Answer #2872 : WARNING:baspl:291 - The TBUF component "XXX" could not be placed. (How to count the number of TBUF driven nets in a design.)
Xilinx Answer #2851 : M1.4/M1.5: Instructions on how to install and run the license manager standalone on sun/solaris/hp workstations
Xilinx Answer #2850 : M1.3/M1.4/F1.5/F1.5i: Instructions on how to install and run the license manager standalone on win95/winNT4.0
Xilinx Answer #2754 : Design Manager M1.3/M1.4/M1.5/F2.1i: How to open multiple instances of the Design Manager
Xilinx Answer #2669 : M1 and XACT: How to determine device utilization of a design without placement and routing
Xilinx Answer #2630 : M1 : How to change speed grades (faster or slower) of your placed and routed design? How to recreate simulation and static timing models?
Xilinx Answer #2568 : Design Manager M1.5i: Using a User Rules File to add command line switch to netlist reader.
Xilinx Answer #2565 : M1 DESIGN MANAGER: Wind/U Error (188): Cannot load font set from specification: -adobe-helvetica-medium-r-normal-*-14-*
Xilinx Answer #2559 : Design Manager M1.3: fatal relocation error: symbol not found: _ex_keylock
Xilinx Answer #2558 : M1 VERILOG/VHDL: CLB Flip-flops and latches may have zero setup delay in an SDF netlist for a routed design
Xilinx Answer #2525 : M1.2/M1.3 Design Manager: Object has disconnected from its client
Xilinx Answer #2510 : Flow Engine M1: "object disconnected from client" in Flow Engine (RPC Unavailable)
Xilinx Answer #2430 : Design Manager 6.0.1: Screen goes black during Translate. (DOSGRAB in Win95)
Xilinx Answer #2419 : Design Manager/Flow Engine M1: Screen turns black when Flow Engine is invoked on W95/NT
Xilinx Answer #2361 : Flow Engine M1: ERROR: basut -Argument"../xc4000ex.ngd" has an invalid extension.
Xilinx Answer #2360 : Flow Engine M1: ERROR: basut -switch "-l" is excluded or already used
Xilinx Answer #2359 : Flow Engine M1: Multi-Pass Place & Route summary report not shown until completion
Xilinx Answer #2348 : Design Manager M1: Report Browser can't open reports after Design Implement
Xilinx Answer #2329 : M1 Xilinx Design Manager - Abel is not a valid file entry format
Xilinx Answer #2328 : 2.1i/1.5i Design Manager/Template Manager: How to enable Express Mode Configuration Option for the SpartanXL Family
Xilinx Answer #2326 : Flow Engine M1: Can not generate back-annotated XNF files for XC7000 or XC9000 devices
Xilinx Answer #2325 : Design Manager/Flow Engine M1: Crashes during cut and paste
Xilinx Answer #2315 : Timing / Flow Engine M1: Using a user-modified PCF file
Xilinx Answer #2284 : Design Manager M1: Design Manager does not start/come up when I double-click the icon (PC)
Xilinx Answer #2277 : Design Manager M1: How to change background colors from grey to white on workstations
Xilinx Answer #2272 : Flow Engine M1: Flow Engine log (fe.log) area is truncated at the top
Xilinx Answer #2266 : Flow Engine M1: Text in status window flickers during compile
Xilinx Answer #2262 : Design Manager: The difference between "Version" and "Revision"
Xilinx Answer #2257 : Design Manager M1.3/M1.4/M1.5/i: The User Constraint File (design.ucf) is used even if not specified
Xilinx Answer #2248 : Design Manager M1.3/M1.4/M1.5: Configuration Template does not contain option for creating MASK file
Xilinx Answer #2227 : M1: Design Manager help ->ld.so.1:hyperhelp:fatal:libXmu.so.4:can't open file: errno=2
Xilinx Answer #2172 : XDM, Design Manager 5.2.1: Returns " <speed grade> is not a valid speed grade"
Xilinx Answer #2141 : Design Manager M1.3/M1.4/M1.5: "illegal command line for invoking the Flow Engine", produced when spaces are used in the path; basut 215
Xilinx Answer #2092 : Design Manager 6.0.1: OE20 Caused an Invalid Page Fault (Illegal Operation) in Windows 95
Xilinx Answer #2064 : Design Manager 6.0.1: Error "unhandled exception, invalid file name" on startup
Xilinx Answer #2034 : Flow Engine 6.0.1: xnfprep error 7804: CST file doesn't exist
Xilinx Answer #1997 : Design Manager M1: Fails to start (hangs/core dumps/segmentation faults) on UNIX machines
Xilinx Answer #1958 : Flow Engine 6.0.1: How to speed up the Translate step (wir2xnf) in XACT 6.
Xilinx Answer #1931 : Flow Engine 6.0.1: Message "Could not find 2018.spd" during compilation of XC4000 design
Xilinx Answer #1904 : FLow Engine 6.0.1: Error - Command line exceeds allowable limit
Xilinx Answer #1832 : M1: Getting XACT and M1 License Files to use same license manager.
Xilinx Answer #1794 : Design Manager 6.0.1: Translate issues "cannot copy translated netlist"
Xilinx Answer #1732 : Design Manager 6.0.1: Error - "Cannot find input design. Please specify an existing design"
Xilinx Answer #1718 : Diamond Speed Star 64: Translate or Design Manager hanging
Xilinx Answer #1682 : Design Manager 6.0.1: Unfamiliarly named filesystem, ParcPlace Systems, FATFilename
Xilinx Answer #1649 : Design Manager 6.0.1: Translate--> XMAKE: ERROR: Failed to find part type <part> in 'partlist.xct'.
Xilinx Answer #1613 : Design Manager 6.0.1: Out of memory errors with Windows95
Xilinx Answer #1544 : Design Manager 6.0.1: Translate in Win 95 produces a DOSGRAB "DOS mode" message
Xilinx Answer #1353 : Design Manager: Rhdexec.dat does not exist
Xilinx Answer #1321 : Design Manager reports: xmake is inaccessable
Xilinx Answer #1313 : Why does Flow Engine run the XBLOX program on my non-XBLOX design?
Xilinx Answer #1309 : Design Manager : Cannot find data file "xc9500.bos" in the XACT path.
Xilinx Answer #1243 : Flow Engine 6.0.1: DOS 16m error - protected mode requires VCPI within virtual 8086
Xilinx Answer #1235 : Design Manager M1: Translate hangs while attempting to read in a netlist file
Xilinx Answer #1227 : Template Manager M1/XACT : How to specify options not available in the options menu of Design Manager
Xilinx Answer #1206 : NEC VersaGlide Mouse driver causes Flow Engine to crash (Fatal exception at 0D)
Xilinx Answer #1151 : Design Manager: System Error, Unhandled Exception: ERROR_FILE_NOT_FOUND
Xilinx Answer #1150 : Design Manager/Flow Engine: BlackBoxes appear instead of Characters
Xilinx Answer #1054 : design manager : translate general protection fault Wir2xnf TNT 11020
Xilinx Answer #1052 : Design Manager 6.0.x: runtime 6008 not enough space for arguments
Xilinx Answer #1041 : Design Manager 6.0.x: Unhandled exception, xact raw binary interface error
Xilinx Answer #1024 : Selecting New Device in Design manager give Unhandled Exception Error. Message not understood
Xilinx Answer #1014 : Design Manager/Flow Engine 6.0.1: A guide file specified in the Advanced menu may not be used/implemented
Xilinx Answer #917 : Design Manager: Unhandled exception, invalid file name, PCFilename class
Xilinx Answer #908 : Design Manager 6.0: Design Manager doesn't start. Says "Not enough Memory"
Xilinx Answer #805 : Design Manager 6.0 Smalltalk Error
Xilinx Answer #802 : Running XACTStep 6.0 Design Manager on OS/2 is not possible
Xilinx Answer #799 : A Possible Solution for the 'Smalltalk Error' when Design Manager 6.0 is Invoked
Xilinx Answer #783 : FLOW ENGINE 6.0: Hangs or freezes during a compile
Xilinx Answer #776 : Design Manager: PC connected to Novell network hangs when running translate.
Xilinx Answer #754 : Design Manager 6.0.1: Translate process gives memory allocation error
Xilinx Answer #752 : Design Manager: System Error, Unhandled Exception: ERROR_FILE_NOT_FOUND
Xilinx Answer #733 : Design Manager 6.0.1: Guide Data Specified in two Dialogs
Xilinx Answer #732 : Flow Engine 6.0.1: Changes to Options Templates are not used
Xilinx Answer #731 : Design Manager 6.0.1: Report Browser error: The report file is missing
Xilinx Answer #730 : Design Manager 6.0.1: Attempts to Rename the Design Name causes System Error
Xilinx Answer #729 : Design Manager 6.0.1: Manually deleting project data can cause System Error
Xilinx Answer #728 : Design Manager 6.0.1: Unable to create directory for the new revision
Xilinx Answer #727 : Design Manager 6.0.1: Translate fails to creat a Version/Revision
Xilinx Answer #725 : Design Manager 6.0.1: Calling DOS program within a Windows application causes screen to go blank
Xilinx Answer #724 : Design Manager/Flow Engine 6.0: Application Error: Stack Overflow
Xilinx Answer #723 : Design Manager 6.0.1: Target Family cannot be changed after project is created
Xilinx Answer #722 : Design Manager M1.5: Timing Simulation Data (time_sim.*) is not created
Xilinx Answer #721 : Design Manager/Flow Engine 6.0.1: cancel button can cause memory leaks
Xilinx Answer #720 : Design Manager 6.0.1: PC hangs if Virtual Memory is checked while Design Manager is running.
Xilinx Answer #718 : Flow Engine 6.0.1: Optimize Step Must Be Run to Read in XACT-Performance Changes in Constraints File
Xilinx Answer #716 : Design Manager 6.0.1: System Error, Unhandled Exception: Subscript out of bounds.
Xilinx Answer #711 : Design Manager 6.0.1: win32s/WinProbe may cause Design Manager to hang during translate under Windows 3.11
Xilinx Answer #710 : Design Manager 6.0.1: Cannot find input design or work directory
Xilinx Answer #709 : Design Manager/Flow Engine 6.0.1: GROWSTUB General Protection Fault, pointer.dll
Xilinx Answer #706 : 6.0: win32s/WinProbe may cause Design Manager to hang during translate.
Xilinx Answer #704 : 6.0: PC hangs if Virtual Memory is checked while Design Manager is running.
Xilinx Answer #698 : 6.0, Compaq: Design Manager may give Unhandled Exception in 256 Color Mode.
Xilinx Answer #697 : 6.0: About WIN32S and XACTstep 6.0 (Design Manager Hangs)
Xilinx Answer #673 : Design Manager 6.0.1: Unhandled exception in 256 color mode on Compaq QVision boards.
Xilinx Answer #635 : XSIMMAKE/CHECK: Gives Error 7 when run from the Design Manager (PROSERIES)