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Xilinx Answer #8292 : JTAG - Using the TDO pin as a user output on XC4000 based devices (HDL example)
Xilinx Answer #8187 : Virtex-E LVDS: How to use LVDS IOSTANDARD in Virtex-E
Xilinx Answer #7880 : Virtex-E: Are the Virtex-E I/O pins 5V compatible?
Xilinx Answer #7773 : How do I convert a Foundation 1.4 project for use in 2.1i?
Xilinx Answer #7006 : Foundation1.5is2,FPGAExpress3.1: How to get report of synthesis result in Foundation HDL macros
Xilinx Answer #6947 : 1.5isp2 xvkdr:42 signal clock (clk2x) is driving pin in of u4 (bufg)
Xilinx Answer #6745 : 1.5i SpartanXL - Chip Scale package files are available
Xilinx Answer #6743 : VHDL simulation RAM16X1D: Can not perform a write unless all inputs are at a known level
Xilinx Answer #6537 : UNISIMS/SIMPRIMS: How do I use the glbl.v module in a Verilog simulation?
Xilinx Answer #6534 : UNISIMS: Alliance 2.1i (or later) changes from 1.5i (or earlier) for Verilog UNISIMS simulation
Xilinx Answer #6362 : Virtex CLKDLL HDL simulation: LOCKED signal doesn't lock if it's not in ps time resolution.
Xilinx Answer #6326 : UNISIMS: GSR/GTS behavior does not simulate with RAMB4* Verilog models.
Xilinx Answer #6297 : JTAG Programmer 1.5 misunderstands the s20xl TQ144 bit file for s20xlt_Q144.
Xilinx Answer #6254 : Xact to M1.5i conversion documentation: preload_opt and mrinput attribute
Xilinx Answer #6184 : 1.5i: 9500XL: Hitop : BUFT and Clock polarity inverted
Xilinx Answer #6062 : 1.5i/2.1i: Virtex Back Annotation - Incorrect models for OBUF_GTL and OBUFT_GTL
Xilinx Answer #5990 : JTAGPGMR 1.5x: Using parallel port beyond LPT1 and LPT2
Xilinx Answer #5939 : M1.5i/2.1i: When a group gets made and a TIG is placed THRU this group the TIG gets ignored
Xilinx Answer #5923 : 1.5i Service Pack 2 Data File Updates are available.
Xilinx Answer #5887 : Alliance 1.5i Service Pack 2 is now available
Xilinx Answer #5854 : 1.5i SP2 XC4000XV Device Representation - There are 4 bogus PIPs in the lower right corner of 4000xv NPH's
Xilinx Answer #5846 : 1.5i SP2 CPLD Packages - The BG256 package additions for 95288XL and 95288XV
Xilinx Answer #5792 : 1.5i - A new package file is available to correct pinout errors in XC40150XV-BG432.
Xilinx Answer #5625 : Instantiating Xilinx Library elements in Foundation 1.5xx HDL flow: where can you get interface information
Xilinx Answer #5573 : 1.5i CPLD - 9572xlcs48 package availability
Xilinx Answer #5569 : PCILOGIC simulation model missing two inverters
Xilinx Answer #5530 : 1.5i XC400XLA Speed Files - Preliminary Speed Files are avaialble for x4013xla, x4062xla and x4085xla.
Xilinx Answer #5526 : 1.5i Virtex Back Annotation - CLKDV_DIVIDE and DUTY_CYCLE_CORRECTION only in physical netlist
Xilinx Answer #5522 : 1.5i Promgen - ERROR:basbs:262 - 0x19682 bytes loaded up from 0x0 exceeds maximum0xffff..
Xilinx Answer #5437 : VSS with M1.5: "Error: vhdlsim,19: Discrete range is not consistent with corresponding index subtype" in simprim_Vpackage.vhd
Xilinx Answer #5429 : M1.5i/2.1i: Prohibiting multi-purpose configuration pins.
Xilinx Answer #5360 : Libraries Guide 1.5: Input Frequency Range of CLKDLL is incorrect
Xilinx Answer #5270 : SIMPRIMS: The INIT parameter is incorrectly defined for the X_LUT* Verilog models for Alliance 1.5
Xilinx Answer #5163 : Does Xilinx Support LPM's?
Xilinx Answer #5140 : M1.5i/2.1i: Using the Tri-State IOB Flip-Flop in SpartanXL, XC4000XLA, and XC4000XV
Xilinx Answer #5070 : M1.5i/Synopsys VSS: Error when compiling UNISIM library: **Error: vhdlan,1073 unisim_VPKG.vhd(509) on function SLV_TO_INT
Xilinx Answer #5040 : 1.5 Foundation Schematic/Simulator: Simulator does not update when wire being simulated is changed to a different wire.
Xilinx Answer #5009 : UNISIMS/SIMPRIMS: How to drive PRLD, GSR, GR, and GTS in a Verilog simulation?
Xilinx Answer #4982 : MTI, M1.5: ERROR: time_sim.vhd(612): Type error in bit string literal. Type string is not an array of bit.
Xilinx Answer #4826 : M1.5: TAENGINE caused invalid page fault
Xilinx Answer #4809 : A1.5, A1.5i, Synopsys: New Designware libraries availible on the FTP site to fix carry-in problem with add_sub component
Xilinx Answer #4775 : Alliance 1.5 & Foundation 1.5 Service Packs are available.
Xilinx Answer #4773 : FPGA Configuration: SyncToDone must apply to all devices in Daisy-Chain.
Xilinx Answer #4771 : Changes in software security for F2.1i, F1.5, A1.5 (versus v1.4 and previous)
Xilinx Answer #4726 : Fatal Error:x4ema clb.c:1172:1.60 illegal pack config made it to pack_flop CLB:1404 CLB1467
Xilinx Answer #4686 : How to use the VHDL ROC (Reset On Configuration) Component
Xilinx Answer #4685 : UNISIMS: Adding the INIT attribute to VHDL/Verilog based FD models for RTL simulation?
Xilinx Answer #4642 : M1.5,bufg,vhdl: Logic trimmed when all buffers instantiated rather than placed by Express.
Xilinx Answer #4623 : MAP1.5 FATAL_ERROR:x4ema:x4emamerge.c:2994:1.43 - Pin 15 already occupied .....
Xilinx Answer #4570 : A1.4/XSI: XC40125XV XSI synthesis and designware files are available on the Xilinx FTP site
Xilinx Answer #4528 : A1.4/F1.4 Speed Files - Preliminary -08 speed grade data available for xc4000xl
Xilinx Answer #4523 : M1.5, HPUX 10.20: /lib/dld.sl: Unresolved symbol: [Vtable]key:__dt__21__versioned_type_infoFv (data) from $XILINX/bin/hp/libbasut.sl
Xilinx Answer #4520 : HPUX 10.20, M1.5 executables : /usr/lib/aCC/dld.sl: Can't open shared library
Xilinx Answer #4319 : A1.4/F1.4 Speed files - Incorrect speed models on two wires of the Spartan device family.
Xilinx Answer #4311 : A1.4/F1.4 Lca2ncd - ERROR: xildr - netcheck signal "bla" contains invalid routing at...
Xilinx Answer #4301 : INTERNAL_ERROR:baste:bastetspec.c:2325:1.69.14.3 - TE_TS_SIG object associated with NET EVNT_EVEN1 has no associated NC_SIGNAL.
Xilinx Answer #4258 : SIMPRIMS: Alliance 2.1 changes from 1.5i (or older) for Verilog SIMPRIMS simulation
Xilinx Answer #4201 : M1.x: BSCAN pins (TDO, TDI, TCK, TMS) are not reported for a 5200 device.
Xilinx Answer #4181 : M1/Exemplar: How to instantiate Logiblox modules
Xilinx Answer #4088 : M1.4 XC4000XV - Package File Update adds BG432 package to the XC40125XV device.
Xilinx Answer #4072 : M1.4: WARNING:x4edr:21 - Blockcheck: CLB "frfi3_alism_fiCtr_upDown" is configured to use the G LUT as RAM, but the D1 and WE lines use the same pin, which will likely cause a D->WE setup vi olation.
Xilinx Answer #4031 : M1.4 General - XC4000XL speed file upgrade adds -08 speed grade for 4013XL, 4036XL and 4062XL.
Xilinx Answer #3970 : M1.4 Speed files - Pullup res. for x4002xl and wire segment res. for x4085 is incorrect
Xilinx Answer #3940 : M1.4 Speed Files - New Spartan Speed Files are available.
Xilinx Answer #3930 : SIMPRIMS: An X_FF waveform does not look correct and may be mistaken for a latch in Verilog SIMPRIMS simulation
Xilinx Answer #3914 : UNISIMS/SIMPRIMS: Usage of GSR_SIGNAL, GR_SIGNAL, PRLD_SIGNAL, and GTS_SIGNAL text macros in Verilog simulation?
Xilinx Answer #3909 : M1.4: WARNING:basts:75 - TPTHRU "IBUS_PATH" is on NET "IBUS2", which is notconnected to any drivers.
Xilinx Answer #3830 : A1.5: Cadence Concept 9604 and 97a: How to target a Spartan device
Xilinx Answer #3774 : JTAG Cable cannot be used for FPGA configuration with PROG pin connected.
Xilinx Answer #3739 : M1.4 Back Annotation - List of all software updates available for M1.4 back annotation.
Xilinx Answer #3707 : WINDOWS NT: General debugging suggestions on handling Dr. Watson Errors
Xilinx Answer #3692 : M1.4 XC4000XV Speed Files - A Patch is available with new 40125XV speeds files.
Xilinx Answer #3619 : A1.4/F1.4 DC2NCF: set_output_delay command affects following set_max_delay command
Xilinx Answer #3597 : Fatal_error:x3kma:x3kmarmunused.c:120:1.8 remove input sig U9/$Net00047_ from comp U9/$I67 causes empty F func.
Xilinx Answer #3582 : Quick Start Guide for Xilinx Alliance Series 1.4: where to find it on the web?
Xilinx Answer #3532 : A1.4/F1.4 - List of all Software Updates with dependencies
Xilinx Answer #3509 : M1.4 Win95 - A patch is available to address slow runtimes for applications that load/write .ngd files.
Xilinx Answer #3488 : M1: What is in the $XILINX/xc4500e directory?
Xilinx Answer #3458 : core dump on Win95 platform during fplan run
Xilinx Answer #3453 : Alliance 1.4/1.5: Operating system, disk space, memory and swap space requirements
Xilinx Answer #3452 : FATAL_ERROR: baste:bastecomp.c:1943:1.61.9.3 - idx not found.
Xilinx Answer #3411 : M1.4: Spartan devices do not appear in the Part Selector dialog box
Xilinx Answer #3389 : M1 docs., library guide,X74_168: Fig. 12.12, shown cascading counter is wrong.
Xilinx Answer #3386 : M1.4: Fatal error: basnc:basncgrid.c:129:1.5: grid file from xilinx:5200:5210: is corrupted
Xilinx Answer #3374 : M1.5i/2.1i: WARNING:bastw:174- The current connection evalutation limit of 1000 caused ....
Xilinx Answer #3345 : A1.4: What's new in A1.4 XSI
Xilinx Answer #3333 : M1.5i/2.1i TRACE: What to do about tilded values (~46ns) in the report
Xilinx Answer #3331 : Y2K: Xilinx Software YEAR 2000 Compliance (including information about PC / WS Operating Systems and EDA Vendors)
Xilinx Answer #3305 : M1.3/M1.4 ngd2xnf does not support 4000EX/XL/XV
Xilinx Answer #3302 : CPLD: What are negative setup times in CPLD Performance report?
Xilinx Answer #3281 : M1.4 General - A patch is available to add the CB228 package to XC4036XL and XC4062XL devices and BG432 to XC4085XL device..
Xilinx Answer #3271 : M1.4 General - A patch is available to add CB228 package to XC4028EX.
Xilinx Answer #3248 : M1.4 Core Tools - All M1.4 bug fixes available in M1.4 Core Tools Patch on the Xilinx Download Area.
Xilinx Answer #3236 : M1.4 Spartan - A patch is available to provide the PQ208 package for Spartan s20, s30 and s40 devices.
Xilinx Answer #3136 : How does the XILINX_PATHLIMIT environment variable work?
Xilinx Answer #3126 : M1.4 CPLD: A fitter crash may result from properties applied to wrong objects
Xilinx Answer #3119 : Is it possible to run more than one version, multiple versions of lmgrd/flexlm at one time?
Xilinx Answer #3078 : M1.4,Powerview 6: vanlibcreate gives linker error compiling Logiblox VHDL library
Xilinx Answer #3074 : A1.5/1.4: Cadenece Concept and Verilog-XL: Functional simulation with Mode and Boundary Scan pins in schematic
Xilinx Answer #3064 : M1.3 Translate: OPTX error:x4kdr: 7 ---netcheck: Macros instantiated in ABEL.
Xilinx Answer #3055 : M1.3/M1.4 CPLD: Fitter incorrectly trimming pin from macro which is driving multiple outputs
Xilinx Answer #3009 : dsgnmgr: Core dumps using Exceed/W
Xilinx Answer #2980 : M1: Undocumented environment variables for the Xilinx GUIs (XIL_*)
Xilinx Answer #2924 : M1.3/M1.4: Solaris, Powerview/logiblox: lbgui process is left running after exiting ViewDraw
Xilinx Answer #2900 : M1.4: FATAL_ERROR:basut:basutarray.c Element out of range
Xilinx Answer #2863 : FATAL_ERROR:basbd:basbdbool.c:393:1.5 - Signal unassigned to variable encountered. Process will terminate. Please call Xilinx support.
Xilinx Answer #2844 : M1.3 and M1.4: Flexlm - all the files that is associated with flexlm 5.0
Xilinx Answer #2832 : M1.3: Warning: basdp: 52 / basdp: 48
Xilinx Answer #2801 : M1.3 GUIs: "Warning: Can't load Codeset file 'c', using internal fallback" while loading
Xilinx Answer #2788 : --OBS--M1.3.7 Speed Files - New speed files are available for M1.3.7 XC4000XL and XC4000EX.
Xilinx Answer #2742 : How to analyze the delays for a specific path using M1 software?
Xilinx Answer #2710 : How to find the amount of on chip resources used by M1 Implementation software.
Xilinx Answer #2692 : Error: unable to open symbol template file. Logiblox: /sim/datareg0.1
Xilinx Answer #2684 : UNISIMS: Adding the INIT attribute to VHDL/Verilog based RAM models for RTL simulation?
Xilinx Answer #2683 : PROMGEN M1.3: M1 vs XACT 6.0.x bit swapping in HEX files.
Xilinx Answer #2656 : M1.3.7 - XC4000XL package file patch adds new packages.
Xilinx Answer #2655 : M1 CPLD: Synopsys SCAN tutorial test bench does not initialize registers.
Xilinx Answer #2648 : Can I run M1 and XACTstep 6.0 software on the same machine?
Xilinx Answer #2542 : M1: FATAL ERROR BASUT: cname.c:102:1.6 reference count overflow
Xilinx Answer #2501 : M1: NOCLIP, S, NOMERGE, X and KEEP properties
Xilinx Answer #2499 : M1.3/A1.4: UNIX environment setup for SunOS, Solaris, and HP using C-shell (csh) or KornShell (ksh).
Xilinx Answer #2493 : M1: Using the MYXILINX environment variable, correcting ld.so errors
Xilinx Answer #2476 : UNISIMS: GSR/GTS behavior does not simulate with STARTUP_VIRTEX Verilog model.
Xilinx Answer #2341 : M1.3/M1.4 CPLD: Fitter does not recognize the vcc labelled net as a special net name
Xilinx Answer #2302 : M1: How to find the C Vol Serial Number and ethernet address?
Xilinx Answer #2287 : FPGA Express: Opening up Express to an Existing to a User Default Location
Xilinx Answer #2270 : FPGA Express v1.1: Does not allow Verilog parameters used as indices for arrays
Xilinx Answer #2267 : FPGA Express: Deleting Multiple Files from the Express Project Window
Xilinx Answer #2258 : M1.3(FPGA Compiler)-Common issues/solns when re-compiling M1.3 XSI XDW libraries
Xilinx Answer #2202 : LEAPFROG: How to compile the Xilinx Alliance libraries for Cadence's Leapfrog?
Xilinx Answer #2039 : NG2VER, NGD2XNF: Unable to copy temporary file ...
Xilinx Answer #2037 : M1/XSI v1.1.1a: Template runscripts in $XILINX/synopsys/examples are incorrect
Xilinx Answer #1984 : FPGA Configuration: Address Pins A18 - A21 are optional for XC4000EX only
Xilinx Answer #1949 : Are M1 BIT files compatible with XCHECKER 5.x?
Xilinx Answer #1944 : dsgnmgr M1.1.1a: "Cannot find tool definition file..."
Xilinx Answer #1913 : Available patches for M1.1.1a 4KEX Pre-release...
Xilinx Answer #1885 : M1Security is Based on FLEXlm, and Requires Lmgrd v4_1 and Xilinxd
Xilinx Answer #1610 : Report Browser 6.0: File extensions for each report file and their locations.
Xilinx Answer #1558 : Windows 95: help fails with three programs within XACTstep 6.0 program group
Xilinx Answer #1450 : UNISIMS: The pin names for VCC and GND have changed to P and G
Xilinx Answer #1449 : Possible Solution for Unexpected Error Detected. Reference writepif.cc: 871
Xilinx Answer #1363 : Will a Pentium Pro or MMX instruction (P6) speed up Xilinx software?
Xilinx Answer #1358 : JTAG - How to attach a pullup or pulldown resistor on the 4K TDO pin?
Xilinx Answer #1238 : Logitech Mouse driver causes Translate to Hang
Xilinx Answer #1209 : ** OBSOLETE ** CADENCE: How the Cadence/Xilinx schematic Interface software is obtained (DS-CDN, DS-381)
Xilinx Answer #1189 : Analyzing the Synopsys Designware and Simulation Libraries for M1 and XACT 5.2.1
Xilinx Answer #1159 : XEPLD 6.0.1: vm2006:Internal Error and - invalid ID] when taegine is run
Xilinx Answer #1153 : PPR: ERROR 1173: the file \path\dsn.lca associated with the LCA cell \path\dsn could not be found.
Xilinx Answer #1098 : M1: Powerview: User-owned directory/files may be created in Xilinx tree
Xilinx Answer #902 : Information about running XACT 5.2.1/6.0.1 (with WVO) in Windows NT
Xilinx Answer #772 : Translate (& other DOS tools) hang if "Exclusive in Foreground" is checked.
Xilinx Answer #715 : 6.0: "Win32s requires file sharing and locking support. Please execute share.exe before continuing" (vshare.386)
Xilinx Answer #682 : abnormal program termination memory protection (or Page) fault
Xilinx Answer #623 : XACT 5.x/M1 and Mentor compatibility information
Xilinx Answer #140 : XC4000: weight of 4005CB164 in Military B package - 11.5 grams