.lok file extension

Actel headquarters
ACTgen
    CCC
    Clock Conditioning core restrictions
    Clock Conditioning cores
    configure core
    Core view
    Create a new core
    Delete a core
    Fan-in control limitations
    Fan-in control tool
    FIFO
    FlashROM
    import a new core
    Import existing core
    in Libero IDE
    interface
    Log window
    PLL core restrictions
    PLL cores
    PLL signal descriptions
    Port mapping
    Preferences
    ProASIC3E FIFO
    ProASIC3E RAM
    RAM
    Remove a core
    Save workspace
    Variety view
    workspace
ACTgen FROM core
ACTgen/cores, online ref guide
active lists
    copying
    creating
    defined
    deleting
    displaying
    editing
ADB file association
Adding applications
ADL file
AFL file
AFM file
Analyzing Power
Analyzing Timing
Applications, starting from Designer
are_all_source_files_curent
assign_global_clock
   Assign net to global clock constraint
   assign_global_clock
   Promote regular net to global net constraint
assign_local_clock
   Assign net to local clock constraint
   assign_local_clock (ProASIC3 and ProASIC3E only)
assign_net_macros
   Assign net to region constraint
   assign_net_macros
assign_quadrant_clock
assign_region
   Assign macro to region constraint
   assign_region
assigned list box
assigning I/O ports to package pins
assigning pins
Associate stimulus
attributes
    common
    defined
    editing
    editing I/O
    formatting rows and columns of
    I/O
    I/O attributes
    I/O standard
    resetting to default
    sorting
Audit settings
Auxiliary files
    importing
AX layout options
Axcelerator
    I/O attributes
    I/O Banks
    I/O compatibility
    I/O standards
Axcelerator layout

Back-Annotation
backannotate
    Tcl command
bank name
Barrel Shifter (ACTgen macro)
basic concepts
    clock
    I/O attributes
    location
    region
Bi-directional Buffers (ACTgen macro)
BIT file
Bitstream file
   Generating a Bitstream file
   Generating Programming Files
BSDL file
buffer
    schmitt trigger
buffer tree
    deleting
    restore
buffers
    viewing in NetlistViewer MVN
bundling nets

catch
ChipEditor
    about
    ChipView window
    components
    customizing assigned and unassigned list boxes
    Edit menu
    File menu
    Help menu
    Nets menu
    starting and exiting
    starting up
    View menu
    with Silicon Explorer
    with SmartTime
ChipPlanner
    changing an object's color
    colors and symbols
    creating regions
    editing regions
    floorplanning
    overview
    setting properties
    starting
    using with SmartTime
ChipView window
clock
    assigning a net to a local clock
    assigning a net to a quadrant clock
    creating
    defined
Clock Conditioning Circuit
Clock Conditioning Cores
close_design
cluster
    defined
COB file
color
    changing in ChipEditor
    changing in ChipPlanner
    changing in PinEditor MVN
colors and symbols
    ChipPlanner
    PinEditor MVN
command substitution
    in Tcl
commands
    Tcl
Commands, Libero
   Menu Commands (Libero)
   Navigating the work environment
committing
    pin assignments in PinEditor MVN
committing changes
compile
    Tcl commands
Compile Options, GUI
Compile report
Configure a core in ACTgen
Configuring a PLL in ACTgen
Constraint order, default for organizing Designer constraint files
Constraints
   Constraint Entry table
   Constraint file format by family table
   Constraint support by family
   Design constraints in Libero
   Design constraints overview
   Timing Constraints
    assigning a macro to a location
    assigning a macro to a region
    assigning a net to a global
    assigning a net to a local clock
    assigning a net to a quadrant clock
    assigning a net to a region
    assigning an I/O to a pin
    attributes
    configure default set of pins to be VREFs
    configuring a pin to be a VREF
    configuring an I/O bank
    create a clock
    creating a region
    DCF
    DCF constraints
    defined
    deleting a buffer tree
    deleting a region
    demoting a global net to a regular net
    entering
    exporting
    file format by family
    GCF constraints
       Design constraints in Libero
       Types of Constraints
    global resource
    how to enter
    I/O assignment
    importing
    moving a region
    netlist optimization
    overview
    PDC constraints
       About Physical Design Constraints (PDC)
       Design constraints in Libero
    Physical constraints
    promoting a regular net to a global net
    reset attributes on an I/O to their default settings
    resetting a net's criticality to the default level
    resetting an I/O bank to its default settings
    restore a buffer tree
    SDC constraints
       Design constraints in Libero
       SDC Files
    set a net's criticality level
    set load on port
    set max delay exception
    setting a false path
    setting a load on a port
    setting a maximum delay
    setting a multicycle path
    setting an input delay
    setting an output delay
    support by family
    timing and area
    unassigning a macro from a location
    unassigning a macro from a region
    unassigning a macro on a net from a region
control structures
    in Tcl
Core
    Remove
Create new core
create_clock
create_clock (GCF)
create_clock, SDC constraint
cross-probing
   Using ChipPlanner with Timer
   Using NetlistViewer in MVN with ChipPlanner
   Using NetlistViewer in MVN with Timer
    ChipEditor and SmartTime
CRT (file)
customizing
    ChipEditor

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