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Xilinx Answer #8421 : 2.1i Spartan-XL PAR - Router gets poor results on XCS30XL and XCS40XL designs compared to 1.5i.
Xilinx Answer #8093 : 2.1i Virtex PAR - FATAL_ERROR:Utilities:basagconjgradient.c:202:1.1.4.2 - CG SOLVER: residual
Xilinx Answer #7696 : LogiCORE PCI 4000: List of the nets that should be guided by PAR for a 4062XLA
Xilinx Answer #7503 : 2.1i Par:placement pass 2 FATAL_ERROR:Utilities:basagconjgradient.c:202:1.1.4.2 - CG SOLVER: residual after solving
Xilinx Answer #6986 : 2.1i Virtex PAR - Placer can not successfully place DLL configurations that worked in 1.5i.
Xilinx Answer #6789 : 1.5i SpartanXL PAR - Divide by Zero crash
Xilinx Answer #6690 : 2.1i Virtex PAR - FATAL_ERROR:Place:xvkapanal.c:1860:1.1.2.21.2.1
Xilinx Answer #6657 : 1.5i SP2 PAR - Fatal Error bascmpindly .c 256:1.18 config string parse error -- primitive ocemuh is not in clkiob
Xilinx Answer #6633 : 1.5i, 2.1i PAR - High density placer (4085XL+, 4KXV) fails on area constrained TBUFs.
Xilinx Answer #6608 : 1.5iSP2 PAR HP-UX 10.2 : cannot find libCsup.1
Xilinx Answer #6597 : M1.5is2, par - access violation (0xc0000005), address 0x01d03564, invalid page fault in module libx45rt.dll, core dump
Xilinx Answer #6492 : 1.5i Virtex Map/PAR - Clock net LOC constraints may be ignored if IPAD to BUFG connection is used.
Xilinx Answer #6408 : 1.5i, 2.1i Virtex PAR - PAR crashes with Exception: access violation (0xC0000005) Address 0x031335A6
Xilinx Answer #6335 : 1.5i, 2.1i 4KX* PAR - Pad report contains TDO as a reserved pin even when not using boundary scan
Xilinx Answer #6217 : 1.5i PAR - ERROR:baspw:103 - The extension on output file ... is not valid because a PAR -n value greater than one (1) has been specified
Xilinx Answer #6209 : 1.5i SP2 Virtex PAR - Par causes an invalid page fault if all IOBs on a Virtex design are locked.
Xilinx Answer #6089 : 1.5i Virtex PAR - Placer crashes on design with routed hard (.nmc) macros.
Xilinx Answer #5918 : 1.5i Timing - PAR appears to hang due to problem with OFFSET constraint.
Xilinx Answer #5886 : 1.5i SP2 Virtex PAR - FATAL_ERROR:ROUTE:xvkrtexpand:1867:1.17.1.4 - Internal router error.
Xilinx Answer #5852 : 1.5i SP2 Virtex PAR - PAR rips up and reroutes guided nets in PCI design.
Xilinx Answer #5838 : 1.5i SP2 Virtex PAR - PAD report does not report VREF pins correctly
Xilinx Answer #5828 : M1.5i SP2 XC4000XV Timing - PAR doe not route optimally due to speed file problems.
Xilinx Answer #5818 : 1.5i SP2 Virtex PAR - Internal Error : Basnd: basndtiming.c:251:1.25.1.2 - Internal delay calculator failure
Xilinx Answer #5779 : 2.1 Virtex PAR - Guided Par can't match components using guide file created in 1.5i release or earlier.
Xilinx Answer #5757 : 1.5i PAR - Bogus PAR error regarding VREF : ERROR: xvkap:61
Xilinx Answer #5704 : 1.5i 4KXL PAR - 4036xl design unable to place some CLBs clocked by BUFGE
Xilinx Answer #5689 : M1 PAR: How can I access multple processors in a single node using the Turns Engine?
Xilinx Answer #5686 : 1.5i XC4000XL PAR - Router fails to meet timing on TBUF nets, but re-route is successful.
Xilinx Answer #5616 : 1.5i PAR - Virtex design with apparently good RPM fails during placement.
Xilinx Answer #5591 : 1.5i Virtex PAR - PAR terminates abnormally after initial placement if a large percentage of BLKRAMs are being used.
Xilinx Answer #5582 : M1.5i PAR: ERROR:xvkap:50 - Design conataines net <netname> driven by TBUFs that are constrained to different rows
Xilinx Answer #5571 : 1.5i PAR - Performance of 4062xla-09 design is inferior to 4062xl-09.
Xilinx Answer #5556 : 1.5i SP2 XC4000XV PAR - Most of the paths on octal lines in 4000xv are not being represented as being buffered.
Xilinx Answer #5555 : 1.5i PAR - Guide fails to match comps when guiding with identical design.
Xilinx Answer #5554 : 1.5i Virtex PAR - Router is routing backbone net to IOB CLK pins incorrectly.
Xilinx Answer #5546 : 1.5i PAR - A design fails in PAR with ERROR:xvkap:62 - IOB IOBUFAGP is incompatible with SelectIO standards ...
Xilinx Answer #5543 : 1.5i PAR - Placement error related to use of carry logic in guided PAR.
Xilinx Answer #5542 : 1.5i PAR - PAR never completes router resource preassignment
Xilinx Answer #5541 : PAR misreports Virtex PCIIOBs as only inputs instead of bidirs.
Xilinx Answer #5540 : 1.5i Virtex PAR - Placer seg faults when both list and single LOC csts applied to a TBUF set.
Xilinx Answer #5533 : 1.5i PAR - MPPR with Virtex gets poor results after first pass.
Xilinx Answer #5532 : 1.5i PAR - Leveage guided PAR fails with NTERNAL_ERROR:basnd:basndtiming.c:647:1.25.1.2 -...
Xilinx Answer #5528 : M1.5i Virtex Timing - PAR issues warning when trying to create the TIMEGROUP "DLLS"
Xilinx Answer #5521 : 1.5i Virtex PAR -Placer hangs on a virtex design.
Xilinx Answer #5513 : 1.5i Virtex PAR - WARNING:basdp:117 - Ignoring constraint < > because site was not found - Virtex Prohibit syntax
Xilinx Answer #5492 : 1.5i PAR - INTERNAL_ERROR:baspl:basplbscore.c:614:1.21
Xilinx Answer #5374 : 1.5i SP2 Virtex PAR - ABNORMAL PROGRAM TERMINATION when all IOBs in design are locked and the design contains SelectIO IOBs.
Xilinx Answer #5371 : 1.5i Virtex PAR - XCV1000 implementation not progressing after 60 hours on 450MHz PC with 384 MB RAM
Xilinx Answer #5364 : 1.5i XC4000X* PAR - Express designs with non-RLOC'd carry chains and Coregen modules may not place.
Xilinx Answer #5344 : 1.5 XC5200 PAR - WARNING:baspl:325 - IOPLACETASK: No I/O comps to place
Xilinx Answer #5292 : 1.5i Virtex PAR - Incorrect PCF file in PAR causes application error rather than Par warning
Xilinx Answer #5181 : 1.5i PAR - Placer fails on .pcf placement constraint (ERROR:baspl:292/291)
Xilinx Answer #5146 : 1.5i XC4000X* Map/PAR - ERROR:x4kpl:368 - RPM "l***" contains a partial carry logic chain. This is not supported in the current release.
Xilinx Answer #5118 : 1.5i PAR - Route of XC4085XL gives inferior results and takes > 2 times as long with 5_25
Xilinx Answer #5104 : M1 PAR: What is an "antenna" in the context of the place and route program, PAR?
Xilinx Answer #5089 : 1.5i PAR - Some Virtex designs get poor Place and Route results due to premature exit from placer.
Xilinx Answer #5066 : 1.5 4KX* PAR - INTERNAL_ERROR:x4kpl:x4kplanal.c:1730:1.73.3.2 - MACRO TYPE NOT FOUND.
Xilinx Answer #4899 : A1.5/F1.5 - PAR fails due to Map problem related to Floorplanning.
Xilinx Answer #4832 : 1.5i PAR - PAR generates DUP LOCATE HIT warning
Xilinx Answer #4822 : A1.5/F1.5 PAR - PAR_NOGENRAMBLOCK environment variable
Xilinx Answer #4778 : A1.5/F1.5 PAR - PAR ignores constraint in pcf file for IOB placement
Xilinx Answer #4735 : A1.5/F1.5 PAR - MPPR gives reasonable results at first cost table run, but unreasonable results on subsequent cost tables.
Xilinx Answer #4677 : PAR M1.5: Pad report for XC3100A does not report the use of TCLKIN pin
Xilinx Answer #4669 : A1.5/F1.5 PAR - FATAL_ERROR:basnd:basndutils.c:132:1.7 - Internal Error - signal has a loop
Xilinx Answer #4658 : A1.5/F1.5 5200 PAR - Problems with placement of TBUFs when the F5_MUX is used.
Xilinx Answer #4657 : M1.5 MAP : PAR fails to meet timing in M1.5 when it had in M1.4.
Xilinx Answer #4626 : A1.5 Par - Design hangs in PAR after optimization.
Xilinx Answer #4577 : A1.5/F1.5 PAR : bus error (core dumped) after starting constructive placer
Xilinx Answer #4478 : A1.5/F1.5 PAR - Core dump involving PAR using Leveraged Guide.
Xilinx Answer #4457 : LogiCORE PCI32 4000/Spartan: Timing not met due to PAR effort level set to 2 (default)
Xilinx Answer #4312 : A1.4/F1.4 Lca2ncd - Re-entrant par of lca2ncd'd design leave partially configured route-thrus behind.
Xilinx Answer #4308 : LogiCORE PCI32 Spartan (v2.0.3): PAR can not meet timing for the Spartan core
Xilinx Answer #4294 : A1.4/F1.4 PAR - PAR crashes during placement on HP work stations only.
Xilinx Answer #4278 : M1.4 PAR - FPGA Express 2.1.1 designs with incomplete RLOC specifications fail in PAR.
Xilinx Answer #4276 : A1.4/F1.4 PAR - PAR crashed during placement of xc40125xv when using Leveraged Guide.
Xilinx Answer #4266 : A1.4 Par - Use of -m (use multiple nodes) requires that "ping" command be available in path.
Xilinx Answer #4194 : 1.5 4KXL PAR- PAR will not utilize "lone" OFFSET constraints
Xilinx Answer #4113 : A1.4/M1.4 PAR - FATAL ERROR:x45nc:x45ncinfo.c:1307:1.25 - Bel PWR_GND_241 found unpacked...
Xilinx Answer #4074 : M1.4 PAR - DRC incorrectly posts warning about DPRAM D1 pin when it is unused.
Xilinx Answer #3880 : A1.4/F1.4 - PC only PAR crash during placement of high density devices (>= 4085XL).
Xilinx Answer #3814 : A1.4/F1.4 PAR - PAR crashes during placement of XC4000XL device.
Xilinx Answer #3813 : 1.5i, 2.1i XC4000XL PAR - Router duplicates registers for use as output to output route-thrus.
Xilinx Answer #3812 : M1.4 PAR - Nodes list for Turns Engine doesn't accept special characters
Xilinx Answer #3794 : M1.4 PAR: FATAL_ERROR:basnd:basndutils.c:130:1.6 - Internal Error - signal has a loop
Xilinx Answer #3749 : M1 PAR: Multi-Pass Place and Route: The Design Score and what it means
Xilinx Answer #3742 : A1.4/F1.4 PAR - PAR tries to insert bogus route-thru in clock IOB.
Xilinx Answer #3690 : M1 Par or HITOP, ERROR: /usr/lib/dld.sl: Unresolved symbol: seekoff_9streambuf... libbasrw.sl running Xilinx DM through Mentor B.1-B.4
Xilinx Answer #3657 : MAP, PAR: Does Map or PAR insert global buffers on high fanout nets and/or unbuffered clock nets?
Xilinx Answer #3654 : A1.4/F1.4 PAR - Problems with placement of Wide Edge Decoders or associated Pullups.
Xilinx Answer #3585 : M1 PAR: Is there a way to prevent route-thrus?
Xilinx Answer #3570 : A1.4/F1.4 PAR - PAR introduces DRC error: "ERROR:x45dr - netcheck: Signal <net> is routed to the O pin of block <comp> on routing which is not available because the EC pin is using the Logic Ze ro option.
Xilinx Answer #3534 : M1.5i/2.1i: How to preserve the pinout of a previous PAR run (pad2ucf)
Xilinx Answer #3528 : M1.4 PAR - PAR core dumps when trying to place a large xc4000xv design
Xilinx Answer #3499 : M1.4 PAR: ERROR: x45dr - netcheck: / Warning: basrt
Xilinx Answer #3463 : M1.4 PAR - PAR hangs when using a PCF to LOC single component hard macros (.nmc's).
Xilinx Answer #3462 : M1.4 PAR - PAR crashes on a specific xc5200 case.
Xilinx Answer #3461 : M1.4 PAR - PAR runs out of memory during placement of design with hard macros (.nmc's) that contain routing information.
Xilinx Answer #3457 : M1.4 PAR - The xc3000 and xc5200 routers will incorrectly use route-thrus in unused bonded pads.
Xilinx Answer #3456 : M1.4 PAR - Some xc5200 designs core dump.
Xilinx Answer #3431 : M1.4 MAP/PAR: BUFG is not routed properly for 3164Apc84 package.
Xilinx Answer #3396 : M1.4 PAR - XC4000 design crashes after starting the Initial Timing Analysis.
Xilinx Answer #3391 : M1.4, NT, PAR, INTERNAL_ERROR:baspl:basplbscore.c:553:1.17
Xilinx Answer #3378 : PAR M1.4: FATAL_ERROR:basrt:basrtsanity.c:167:1.3 - Process will terminate.
Xilinx Answer #3342 : M1.4 PAR - Mode pins and TDO do not show up in pad report for FPGAs
Xilinx Answer #3317 : M1.4 PAR - PAR core dumps during Initial Timing Analysis.
Xilinx Answer #3316 : M1.4 PAR - PAR fails with Arithmetic Exception on a hard maco design.
Xilinx Answer #3260 : M1.3, PAR, baspw, Error: baspw:97 PAR: Not all timing constraints could be satisfied.
Xilinx Answer #3216 : M1.3.7 PAR: UCF LOC constraint on net does not override conflicting schematic pad constraint.
Xilinx Answer #3209 : M1.4 PAR - PAR does not run any cleanup passes by default in M1.4.
Xilinx Answer #3157 : PAR: Error: baspw: 134 Input design is empty.
Xilinx Answer #3111 : M1.4 PAR - Turns engine requires explicit use of -pl and -rl switches to work.
Xilinx Answer #2915 : M1.4 MAP/PAR: PAR ERROR:baspr - SSLex0105e: Invalid token, Line 13, Offset 38, ,
Xilinx Answer #2891 : PAR: Error: rpc server is unavailable
Xilinx Answer #2889 : PAR: Routing pwr/gnd nets takes an extremely long time to complete
Xilinx Answer #2783 : M1.3/M1.4 PAR: The signal "GLOBAL_LOGIC0" is not completely routed--messages about unrouted nets that are not in the input design
Xilinx Answer #2777 : M1.5 PAR/EPIC: Both say that BEL doesn't exist in the NCD, but it does.
Xilinx Answer #2720 : PAR M1.3: baspl:291,292 - pullup could not be placed
Xilinx Answer #2647 : MAP, PAR, PPR: Constraining signals to unbonded pads in M1 and XACT (naming convention is different)
Xilinx Answer #2583 : PAR 1.4: ERROR: x52ap:111 5200 Design uses to many TBUF's or BUFT's
Xilinx Answer #2578 : PAR/FOUNDATION Beta2/Win95: PAR gives "ERROR: FATAL:basut: basutdtime.c:60:1.5 time failure:
Xilinx Answer #2569 : M1.2/M1.3/M1.4 PAR (MAP): CLB Pin locking is not supported
Xilinx Answer #2504 : PAR: WARNING:basdp - The SITE "pin-out" specified in the .PCF file was not found in desgin
Xilinx Answer #2408 : PAR M1.X - XC4000E designs ported to XC4000XL may have unroutable carry chains.
Xilinx Answer #2407 : PAR M1.X - PAR may crash if guided place and route is mixed with re-entrant routing.
Xilinx Answer #2405 : PAR M1.3 - PAR may fail with segmentation fault processing offset constraints.
Xilinx Answer #2403 : PAR M1.3 - PAR may fail if an RLOC_RANGE overlaps an RLOC.
Xilinx Answer #2399 : PAR M1.3 - PAR placement rules are too strict for comps driven by BUFGE.
Xilinx Answer #2398 : PAR M1.5 - PAR appears to ignore soft range constraints
Xilinx Answer #1861 : M1.3/M1.4 PAR/MAP: TBUFs with RLOC Constraint Must be Part of RPM with RLOC_ORIGIN Constraint
Xilinx Answer #1644 : M1.4: How to setup and debug Multi-Pass Place and Route/Turns Engine/Networked PAR
Xilinx Answer #1312 : XC3000/XC4000/XC5200: PAR ERROR 4kpl:7 - Too many TBUFs (TRISTATEs) driving longline
Xilinx Answer #1073 : PAR: "Number of GCLKS 5 out of 4" with Virtex Synplify netlist
Xilinx Answer #195 : FPGA CONFIGURATION : Which pins are driven during clear/initialization? (master par)