<<
quadrant clock
assigning a net to
Quick Start, Libero
quotes and braces
in Tcl
ratsnest
Ratsnest view
ChipPlanner
read
region
assigning a macro to
assigning a net to
creating
defined
deleting
moving
Region menu
in MVN
regions
assigning a net
assigning macros to
assigning nets to LocalClock regions
ChipPlanner
creating
Creating regions
define_region (rectangular region)
creating logic regions
defined
editing
empty
About regions
Creating regions
Using Empty regions
exclusive
floorplanning
Creating regions
Editing regions
Overview (floorplanning)
hierarchy window
inclusive
LocalClock
About regions
Creating LocalClock regions
Creating regions
logic
About regions
Creating regions
overlapping
About regions
Creating regions
QuadrantClock
unassigning a macro from
regions tab
hierarchy window
Regions, floorplanning
Remove a core
renaming
LocalClock regions
Report, compile
Reports
ACTgen reports
Designer reports
Flip-flop reports
generating with Tcl commands
Pin reports
Power reports (SmartPower)
Saving and printing
Status reports
Timing reports
Reserved keywords
reset_floorplan
reset_io
Reset attributes on an I/O to default settings constraint
reset_io
reset_iobank
Reset an I/O bank to the default settings constraint
reset_iobank
reset_net_critical
Reset net's criticality to default level constraint
reset_net_critical
resistor pull
restore
buffer tree
route view
ChipPlanner
routes
viewing
rows and columns
formatting
RTAX-S prototyping
running scripts
from Designer
from the command line
multiple pass layout
SAIF file
Sales
Save
Design directory
Saving and printing reports
Save Project As
Save Workspace in ACTgen
Schematic
Creating a schematic source file
Opening a schematic source file
printing
Schematic menu
in MVN
schmitt trigger
scripting
basic syntax
command substitution
control structures
exporting scripts
lists and arrays
print statement and return values
quotes and braces
running from command line
running from Designer
running multiple pass layout scripts
sample scripts
Tcl
types of Tcl commands
variables
scripting commands
SDC
SDC commands
syntax conventions
SDC constraints
create_clock
Design object access commands
Importing Auxiliary files
SDC file summary
set_false_path
set_max_delay
set_multicycle_path
syntax conventions
SDF file
Security
Security Key
SEG file
set_auto_global
set_auto_global_fanout
set_critical
set_critical (GCF)
set_critical_ports (GCF)
set_empty_io
set_empty_location
set_false_path
set_false_path (GCF)
set_false_path, SDC constraint
set_global
Assign net to global clock constraint
Promote regular net to global net constraint
set_global
set_initial_io
set_initial_location
set_input_delay
set_input_to_register_delay
set_input_to_register_delay (GCF)
set_io
set_io (GCF)
set_io_region
set_iobank
Configure I/O bank constraint
set_iobank
set_iobank command
set_load
set_location
Assign macro to region constraint
Create region constraint
set_location
set_location (GCF)
Unassign macro from location constraint
set_max_delay
set_max_delay, SDC constraint
set_max_fanout
set_max_path_delay
set_max_path_delay (GCF)
set_memory_region
set_multicycle_path (GCF)
set_multicycle_path, SDC constraint
set_multicycle_paths
set_multitile_location
set_net_critical
Set net's criticality constraint
set_net_critical
set_net_region
Assign net to region constraint
set_net_region
set_noglobal
Demote clock net to regular net constraint
set_noglobal
set_output_delay
set_register_to_output_delay (GCF)
set_vref
Configure pin to be a VREF constraint
set_vref
set_vref_defaults
Configure default set of pins to be VREFs constraint
set_vref_defaults
Silicon Explorer
using with ChipEditor
Silicon Sculptor
Generating a fuse file
Generating programming files
Starting Silicon Sculptor
Simulation
ModelSIM
Options
skew
slew
smartpower_add_pin_in_domain
smartpower_commit
smartpower_create_domain
smartpower_remove_domain
smartpower_remove_pin_frequency
smartpower_remove_pin_of_domain
smartpower_restore
smartpower_set_domain_frequency
smartpower_set_pin_frequency
SmartTime
using with ChipEditor
using with ChipPlanner
Software update
sorting attributes
Source files
importing
specifying an I/O Standard
STAMP file
STAPL file
Starting applications from Designer
status bar
in ChipEditor
MVN
status reports
creating with Tcl
STF file
Stimulus file organization
Stimulus file selection
Summary Tab, Timer
super cluster
defined
Synopsys Design Constraints
syntax
basic Tcl syntax
Tcl commands
syntax conventions
GCF files
PDC files
SDC files
syntax rules
DCF files
Synthesis
Mentor Graphics LeonardoSpectrum
Mentor Graphics Precision RTL
Starting synthesis
Synplicity Synplify
TCL
Exporting Files
Introduction to Tcl scripting
Tcl Command Reference
Tcl Documentation Conventions
Tcl command
layout (advanced options for SX)
Tcl commands
about
backannotate
catch
close_design
compile
documentation conventions
export
export (ProASIC3/E)
export (ProASICPLUS, Axcelerator, ProASIC, MX, eX, and SX/SX-A)
extended_run_shell
get_defvar
get_design_filename
get_design_info
import_aux
import_source
is_design_loaded
is_design_modified
is_design_state_complete
layout
layout (advanced options for Axcelerator)
layout (advanced options for ProASIC/ProASIC PLUS)
new_design
open_design
pin_assign
pin_commit
pin_fix
pin_fix_all
pin_unassign
pin_unassign
pin_unassign_all
pin_unfix
report
smartpower_add_pin_in_domain
smartpower_commit
smartpower_create_domain
smartpower_remove_domain
smartpower_remove_pin_frequency
smartpower_remove_pin_of_domain
smartpower_restore
smartpower_set_domain_frequency
smartpower_set_pin_frequency
timer_add_clock_exception
timer_add_pass
timer_add_stop
timer_commit
timer_get_clock_actuals
timer_get_clock_constraints
timer_get_maxdelay
timer_get_path
timer_get_path_constraints
timer_remove_all_constraints
timer_remove_clock_exception
timer_remove_pass
timer_remove_stop
timer_restore
timer_set_maxdelay
timer_setenv_clock_freq
timer_setenv_clock_period
Tcl files
tcl script files
PDC commands
Tcl scripting
basic syntax
command substitution
control structures
exporting scripts
introduction
lists and arrays
print statement and return values
quotes and braces
running from command line
running from Designer
running multiple pass layout scripts
sample scripts
types of Tcl commands
variables
Technical Support
Testbench
Creating your testbench
Performing Timing Simulation
Selecting a stimulus file
Waveformer Lite
Text editor
threshold level
timer_add_clock_exception
timer_add_pass
timer_add_stop
timer_commit
timer_get_clock_actuals
timer_get_clock_constraints
timer_get_maxdelay
timer_get_path
timer_get_path_constraints
timer_remove_all_constraints
timer_remove_clock_exception
timer_remove_pass
timer_remove_stop
timer_restore
timer_set_maxdelay
timer_setenv_clock_freq
timer_setenv_clock_period
Timing Analysis, Overview
Timing driven layout
timing reports
creating with Tcl
Timing simulation
timing violation reports
creating with Tcl
toolbar buttons
in MVN
Tools menu
in MVN
Tools window
Training
Troubleshooting
types of Tcl commands
>>