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Xilinx Answer #8492 : 2.1i Virtex Map - FATAL_ERROR:baspu:baspupacker.c:313:1.40 - read of floorplanner file ....
Xilinx Answer #8092 : 2.1i Virtex Map - FATAL_ERROR:xvkpu:xvkpulocal.c:246:1.3
Xilinx Answer #7487 : 2.1i SP1 Virtex Map -FATAL_ERROR:xvkpk:xvkpkslice.c:146:1.30
Xilinx Answer #7083 : 1.5i/2.1i 4K Map - ERROR:OldMap:532 - Unable to obey design constraints which require the following symbols into a single CLB. . .
Xilinx Answer #7007 : FPGA Express: MAP ERROR:baste:26 - The TBUFs "X" and "Y" drive the same output signal
Xilinx Answer #6994 : 1.5i/2.1i Map - Xnf (sxnf) file created by FPGA Compiler is processed differently that xnf files from other vendors.
Xilinx Answer #6937 : 1.5i Virtex Map - V300 FG456 -- Map incorrectly uses an unbonded pad.
Xilinx Answer #6880 : 1.5i SpartanXL Map : Exception access violation at :0x0000005 address 0x1002d3f4
Xilinx Answer #6799 : MAP: 1.5i/2.1i, FPGA Express: basnccomp.c:3346:1.1.2.4-cannot find other bel. . .
Xilinx Answer #6794 : 1.5is2 Map : FATAL_ERROR:baste:bastetspec.c:1197:1.87.18.4 - Failed to create DP_PATHDELAY_FROMTO for tspec
Xilinx Answer #6767 : 1.5i SP2 Virtex Map - FATAL_ERROR:basnc:basnccomp.c:3319:1.105 - Cannot find other bel for
Xilinx Answer #6728 : 1.5i SP2 Virtex Map - Crash during map.
Xilinx Answer #6680 : 1.5i Virtex Map - Request for support of map -c (pack factor) option for virtex.
Xilinx Answer #6668 : 1.5i Map - INIT attribute on FDRE leads to DRC error: ERROR:xvkma:135 - Attempt to use INIT=S on RST pin of FF ...
Xilinx Answer #6663 : 1.5i Map - Using the -c switch to achieve the smallest pack of a design may not give the best results
Xilinx Answer #6630 : map 1.5iS2/4062xl: FATAL_ERROR:baste:bastecmpin.c:314:1.27.18.2 - NULL pinhook
Xilinx Answer #6618 : MAP 1.5is2: FATAL_ERROR:basut:basutarray: Sort produced an unsorted list when using PCI Virtex core
Xilinx Answer #6571 : 1.5i Map - ERROR:x4kma:339 - The CY4 symbol has no signal connected to A0.
Xilinx Answer #6563 : 1.5i, 2.1i Map - A .mfp constraint for LOC'd FF is incorrecty overridden by "-pr b"
Xilinx Answer #6562 : 1.5i/2.1i Map - FATAL_ERROR:basnc:basncsignal.c:263:1.67 - Could not find a bel...
Xilinx Answer #6434 : PCI Logicore 3.0: MAP error message "x4kma:387" for SpartanXL and 4000XLA flow
Xilinx Answer #6336 : 1.5i Virtex Map - ERROR:xvkma:125 - PAD encr_tx_clk.PAD does not have at least one IO buffer, possibly due to bad LOC constraint or missing buffer connection. i
Xilinx Answer #6314 : 1.5i, 2.1i Virtex Map - FATAL_ERROR:basmm:basmmfact.c:1349:1.84 - Unknown pad pin type
Xilinx Answer #6289 : 1.5i Virtex Map - Not all instances a timespec are being covered by the resulting .pcf file.
Xilinx Answer #6229 : Map 1.5i, 2.1i Map - FATAL_ERROR:basut:basutcname.c:410:1.8; Utilities:UtilCname.imp.c:400:1.1.2.2: Maximum name length exceeded
Xilinx Answer #6224 : M1 Map - WARNING:x4kma:423: Signals drive closed FMAPs. Set XIL_MAP_OPEN_FMAPS
Xilinx Answer #6212 : 1.5i SP2 Virtex Map - FATAL_ERROR:xvkcm:xvkcmverify.c:47:1.11.1.2 - Mismatched number of primitives...
Xilinx Answer #6201 : 1.5i Virtex Map - ERROR:xvkdr:41 - blockcheck: Improper DLL feedback loop.
Xilinx Answer #6194 : 1.5i, 2.1i Map - A level of logic is used for inverter between IBUF and Register.
Xilinx Answer #6134 : MAP v1.5is2, COREGEN, SDA FIR: x4kma : 339 - The (symname) symbol "xx/xx" has no signal connected to B1. This pin must be connected . . .
Xilinx Answer #6058 : M1.5isp2 Map:Fatal Error:xvkcm:xvkcmverify.c:47:1.11.1.2 - mistmatched number of primitives 52 != 53 for 'PCIIOB'
Xilinx Answer #6057 : M1 Map - ERROR:x4kma:7 - The CY4 symbol "$blah" has no signal connected to CIN
Xilinx Answer #6035 : MAP: 1.5i: ERROR:baste:180 - "RLOC" suffix on. . .
Xilinx Answer #6003 : 1.5i Virtex Map - INTERNAL ERROR: xvkmabel.c: 559:1.21 - XVKMA_BEL_C:: getbelsconntosig(): . . .
Xilinx Answer #5983 : 1.5i Map - Bus error (core dumped) after Merging...
Xilinx Answer #5969 : 1.5i Virtex Map - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.113 - Cannot satisfy LOC/RLOC. . .
Xilinx Answer #5930 : 1.5i Map - WARNING:xvkdr:3 - blockcheck: Dangling CYINIT input. CYINIT of comp
Xilinx Answer #5889 : 1.5i Virtex Map - MAP is dropping some FF paths from Period constraint.
Xilinx Answer #5873 : 1.5i Virtex Map - Virtex macro ADD16 crashes MAP when inputs and outputs are not driven/sourced
Xilinx Answer #5861 : 1.5i Virtex Map - RLOCs cannot be applied to SRL16s
Xilinx Answer #5858 : M1.5is2 MAP:WARNING:xvkdr:3 - blockcheck: Dangling SRMUX input. SRMUX is configured to use pin SR, but pin SR is not connected
Xilinx Answer #5855 : 1.5i SP2 MAP - Application Error has occured (access violation) , MS Studio issue
Xilinx Answer #5844 : 1.5i SP2 Virtex Map - A net splitting feature has been added for multiple fanout IRDY/TRDY nets in PCI.
Xilinx Answer #5842 : 1.5i SP2 Virtex Map - PCILOGIC pins TRDY and IRDY are incorrectly swapped.
Xilinx Answer #5841 : 1.5i SP2 Virtex MAP - Map does not correctly pack FMAPs when using CORE_LUT_CONSTRAINT
Xilinx Answer #5836 : 1.5i SP2 Virtex Map - Enhancements to guide methodology for Virtex PCI designs.
Xilinx Answer #5835 : 1.5i SP2 Virtex Map - Cannot satisfy LOC/RLOC constraint for CC8CE and FDRSE design
Xilinx Answer #5824 : 1.5i Map - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.113 - Cannot satisfy LOC/RLOC constraint
Xilinx Answer #5810 : 1.5i Map - A case has been seen where -pr b option drops an inversion between flop and BUFT.
Xilinx Answer #5808 : 1.5i Virtex Map - Application error: the instruction at address x referenced memory at address x
Xilinx Answer #5781 : 1.5i Virtex Map - Map gives FATAL_ERROR:xvkma:xvkmaslice.c:5862:1.101
Xilinx Answer #5778 : 1.5i, 2.1i 4K Map - Guided map of unchanged design is unable to guide several CLBs.
Xilinx Answer #5750 : 1.5i Map - FATAL_ERROR:xvkma:xvkmaslice.c:4087:1.101 - domergeslices got empty slot for frag comp...
Xilinx Answer #5736 : 1.5i Virtex Map - Bus error (core dumped) on V300 design
Xilinx Answer #5732 : 1.5 XC4000XL Map - ERROR:x4kma:367 - An illegal carry configuration has been detected...
Xilinx Answer #5663 : 1.5i 4KX* MAP - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.113 - Cannot satisfy LOC/RLOC constraint on comp H14/H57/I610/$1I106/$1I64 Process will terminate. Cannot satisfy LOC/RLOC constraint on comp H14/H57/I610/$1I106/$1I64 Process will terminate.
Xilinx Answer #5575 : 1.5i Virtex Map - Segmentation Fault
Xilinx Answer #5568 : 1.5i Virtex Map - FATAL_ERROR xvkma:xvkmapper:c:1691:1.112 - Cannot satisfy LOC/RLOC constraint on
Xilinx Answer #5553 : 1.5i Virtex Back Annotation - Simulation errors during physical back annotation (no .ngm) due to clock renaming by map.
Xilinx Answer #5544 : 1.5i Back Annotation - Muxf6 is not backannotated correctly due to map problem.
Xilinx Answer #5534 : 1.5i Map - run time error - pure virtual call
Xilinx Answer #5498 : 1.5i Virtex Map - Virtex Map crashes after successfully writing output files.
Xilinx Answer #5491 : 1.5i Virtex Map - ERROR:baste:301: The RLOC value of R0C0.S1 on component D creates a macro that is too large for the device
Xilinx Answer #5488 : Design Manager M1.5/i: Map continues to use the "-fp" option even though Set Floorplan Files is set to 'None'
Xilinx Answer #5485 : 1.5i 4KE Map - FATAL_ERROR basutarray.c:207:1.5 - Sort produced an unsorted list
Xilinx Answer #5482 : LOGIBLOX, 4000XLA/SpartanXL Aligned RPM: Map ERROR:baste:190 or OldMap:233 - Bad format for RLOC attribute
Xilinx Answer #5461 : 1_5.19 MAP: Incorrect warning message when ROC is used in VHDL design
Xilinx Answer #5460 : 1.5i Spartan Map - Fatal Error: x4kema:x4kmamerge.c:3879:1.43- Already signals present on this..
Xilinx Answer #5458 : 1.5i Virtex MAP - ERROR:baste:263 - The LOC constraint "M19" (a PCIIOB location) ...
Xilinx Answer #5456 : 1.5i Map - Correlated back-annotation of Virtex carry chain losing some delays.
Xilinx Answer #5434 : 1.5i Map - FATAL_ERROR:basut:basutpak.c:560:1.3 - Bogus offset reading packed data.
Xilinx Answer #5425 : 1.5i Map - Map aborts with ERROR: PAD not a valid type for FMAP symbol
Xilinx Answer #5424 : 1.5i Virtex Map - FATAL_ERROR:xvkma:xvkmap.c:587:1.112. Cannot find IOB attached to IBUFG
Xilinx Answer #5419 : 1.5i Virtex Map - ERROR:xvkma:99 - RLOC has bad suffix. Only valid suffixes are S0 and S1.
Xilinx Answer #5413 : M1.5i Map - FATAL_ERROR:baste:bastencdf: Error in attempt to create BELs
Xilinx Answer #5394 : 1.5i, 2.1i 4KX* Map - Map errors out on carry logic when trimming is disabled.
Xilinx Answer #5363 : 1.5i 4KXL Map - FATAL_ERROR:basnc:basncsignal.c:263:1.67 - Could not find a bel for a signal ...
Xilinx Answer #5329 : 1.5i. MAP - Map may crash on designs with modules containing OPTIMIZE attributes.
Xilinx Answer #5285 : 1.5i 4KXL Map: FATAL_ERROR:baste:bastegrp.c:477:1.21 - No output pin for group
Xilinx Answer #5208 : MAP: "ERROR:xvkma:120 - LUT* symbol has an equation that has no connected signal" with Synplify 5.0.x
Xilinx Answer #5201 : 1.5i Map - Virtex mapper fails to pack 2 FMAPs and 2 MUXCY_Ls into one slice.
Xilinx Answer #5174 : A1.5i (M1.5.25) map: FATAL_ERROR:xvkma:xvkmaslice.c:4041:1.97 - domergeslices got empty slot for frag
Xilinx Answer #5170 : Map 1.5i caused an invalid page fault, LIBBASUT.DLL
Xilinx Answer #5153 : A1.5i/F1.5i MAP/HITOP - application error: <program.exe> the instruction at 0x780017## referenced at memory 0x########. The memory could not be written (msvcrt.dll)
Xilinx Answer #5152 : M1.5i Map - Map fails physical design DRC: ERROR:xvkdr:36 - blockcheck: RAMCONFIG not used.
Xilinx Answer #5151 : M1.5i Map - FATAL_ERROR:x4ema:x4emamerge.c:3810:1.43 - Illegal CLB configuration for c2
Xilinx Answer #5150 : M1.5i Map - Map drops Flop load from signal with multiple loads in Synopsys design.
Xilinx Answer #5120 : 1.5 Map - Error xvkma - specialize_xor() being called for invalid XOR gate -----
Xilinx Answer #5113 : 1.5i Virtex Map - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.112 - Cannot satisfy LOC/RLOC constraint
Xilinx Answer #5075 : M1.5 Map - Map fatal error when IFDX output is fed back to OFDTX loc'd to same pad.
Xilinx Answer #5058 : Map: Hard macro pin locking from ucf not supported
Xilinx Answer #5053 : A1.5/F1.5 Map - Map drops connection internal to CLB corrupting logic
Xilinx Answer #5031 : 2.1i 4KX* MAP - FATAL_ERROR:x4ema:x4emamerge.c:3535:1.43 - Pin 8 already in use. moveflopinpin() for CLB: [3793] Process will terminate.
Xilinx Answer #4991 : 1.5i, 2.1i Map - 4KXLA design seg faults in Map after "Removing unused logic..."
Xilinx Answer #4989 : 1.5i Virtex Map - ERROR:xvkma:xvkmamapper.c:1397:1.97
Xilinx Answer #4974 : 1.5i 4KE Map - Map may incorrectly trim OUTFFTs that are pemanently active.
Xilinx Answer #4970 : M1.5: Map errors on empty time group created by Constraints Editor. (ERROR:baste - Time group)
Xilinx Answer #4959 : A1.5/F1.5 Map caused an invalid page fault in libbasut.dll
Xilinx Answer #4954 : Map 1.5 - Fatal_error:xvkma:xvkmaslice.c:2620:1.78 - mergefsumxor: destination slice
Xilinx Answer #4952 : M1.5. MAP: Dr Watson error on NT machines
Xilinx Answer #4927 : A1.5/F1.5 MAP/Hitop - application error: <program.exe> the instruction at 0x780017## referenced at memory 0x########. The memory could not be written (msvcrt.dll). Due to Microsoft Visual Studi o 6.0 combatibility issue.
Xilinx Answer #4914 : A1.5/F1.5 Map - FATAL_ERROR:baste:bastencdf - Error in attempt to create BELs.
Xilinx Answer #4911 : 1.5 Map - Fatal_error: baspm:c:190:1.21 dll open of lib4krt.dll (this also applies for other DLLs)
Xilinx Answer #4908 : 1.5i Map - "ERROR:baspr:41 - Unable to parse ..." Map writes syntactically incorrect PCF when a USER timegrp is completely trimmed.
Xilinx Answer #4902 : A1.5/F1.5 MAP - Core Dumps with "PROGRAM ABNORMALLY TERMINATED" message on Virtex design.
Xilinx Answer #4900 : A1.5/F1.5 Map - INTERNAL_ERROR:xvkma:xvkmabel.c:566:1.16 seen with Synplify 5.0.7
Xilinx Answer #4895 : A1.5/F1.5 Map - FATAL_ERROR:x4ema:x4emamerge.c:3810:1.43 - Illegal CLB configuration for c2
Xilinx Answer #4886 : A1.5/F1.5 MAP - Map will not put two SRL16 instances into a single Virtex CLB
Xilinx Answer #4863 : A1.5/F1.5 MAP - Map ignores macros which use RLOCs on BUFEs
Xilinx Answer #4862 : A1.5/F1.5 Map - RLOCs on BUFEs do not work correctly
Xilinx Answer #4852 : A1.5/M1.5 MAP - FATAL_ERROR:baste:bastehint.c:318:1.10 - boundname(...) contains NAME_DELIM() Process will terminate.
Xilinx Answer #4847 : A1.5/F1.5 Map - Fatal Error:xvkma:xvkmaslice.c:2620 for Virtex after Service Pack 1.
Xilinx Answer #4845 : M1.5/M1.5i Map FATAL_ERROR:x4kma:x4kmacarry.c:3129:1.142 - never found an empty G pin
Xilinx Answer #4843 : 1.5i Map - FATAL_ERROR:x4kma:x4kmamerge.c:2867:1.158
Xilinx Answer #4827 : A1.5/F1.5 Map - WARNING:x4kma - Signal ` ' on pin 4 9
Xilinx Answer #4798 : Map 1.5i - Prohibit constraints in .ucf file are being ignored by map and are not written to .pcf file.
Xilinx Answer #4777 : 1.5i Map - Map crashes on floorplanned design.
Xilinx Answer #4760 : A1.5/F1.5 XC4000E MAP: BUFG must be LOC'd before map to control whether BUFGP or BUFGS is used.
Xilinx Answer #4695 : A1.5/F1.5 - Fatal Error in map, xvkma:xvkmapper.c:955:1.77 - Can't Satisfy LOC/RLOC constraint.
Xilinx Answer #4694 : A1.5/F1.5 Map - Map segmentation faults in x1_5.19. Ran okay in x1_4.12p.
Xilinx Answer #4679 : A1.5/F1.5 Virtex Map reports that an output is not connected, but does not trim the logic: Warning:xvkdr - blockcheck
Xilinx Answer #4678 : map 1.4:ERROR:baste:263 - The LOC constraint "P21" (a IOB location) is not valid..
Xilinx Answer #4606 : 1.5i 4K MAP: ERROR:x4kma:387 - Unable to obey design constraints
Xilinx Answer #4561 : M1.5 Map - M1.5 optimization performance decreases compared to M1.4 (CLB count increases in 1.5).
Xilinx Answer #4546 : MAP: Error x4kma:195 Problems were found processing RPMs in the design.
Xilinx Answer #4542 : A1.5/F1.5 Map - Map may crash when RLOCs specificy rows and columns greater than the maximum nuber available.
Xilinx Answer #4536 : A1.5/F1.5 Map - SET set_name rloc_origin = R3C4 constraint is not applied correctly by map.
Xilinx Answer #4493 : A1.5/F1.5 X3KA Map - ERROR:baspw:96 - The physical constraint resolution process is unable to resolve all placement constraints
Xilinx Answer #4466 : A1.4/F1.4 Map - FATAL_ERROR :baste:bastephook.c:159:1.8 - cannot copy pinhook to itself Process will terminate. Please call Xilinx support.
Xilinx Answer #4463 : M1.5: Map gives "invalid target architecture"
Xilinx Answer #4459 : A1.4/F1.4 Map - FATAL_ERROR:x4kma:x4kmagrclapse.c:1001:1.90.12.8 - No route-thru available ...
Xilinx Answer #4437 : M1.4 XC3000 Map - When using pack IOB flops option, the CE net is removed.
Xilinx Answer #4419 : M1.4: Map FATAL_ERROR:baste:bastetspec.c:2402:1.69.14.3 - NET OFFSET 'IN1 IN : 20000.00 pS : BEFORE : CLK' has no data IOBCOMP.
Xilinx Answer #4416 : A1.5/F1.5 MAP - Design Summary report includes Avg insigs,outsigs, and lambda. What are they?
Xilinx Answer #4410 : A1.4/F1.4 Map - ERROR:baste:312 - Multiple signals named "GND" detected.
Xilinx Answer #4408 : A1.4/F1.4 MAP - 3K mapper incorrectly reports unconnected inputs to IFDs and then trims the component.
Xilinx Answer #4406 : 2.1i, M1.5, M1.4 MAP, LOGIBLOX: Map:ERROR:x4kma:179 - <symbolname> symbol "instance" cannot be packed into an IOB
Xilinx Answer #4374 : A1.4/F1.4 Map - Map terminates abnormally on an XC4000XL design.
Xilinx Answer #4373 : A1.4/F1.4 - An environment variable has been added to 3k mapper to make map ignore invalid CLBMAPs rather than fatal error.
Xilinx Answer #4299 : A1.5/F1.5 XC3000 Map - FATAL_ERROR:x3kma:x3kmabel.c:752:1.15 - Didn't find out signal on bel 10 of comp A0_1
Xilinx Answer #4260 : A1.4/F1.4 Map - FATAL_ERROR:x4kma:x4kmacarry.c:1134:1.122.12.11
Xilinx Answer #4248 : A1.4/F1.4 Map - Map drops internal CLB connection, corrupting logic.
Xilinx Answer #4240 : A1.4/F1.4 MAP - Connection to TDO pad lost when signal is merged (WARNING::x4kdr:23 - Blockcheck: The comp (mapped physical logic cell) "DIA_RSCI" does not have any pins that are being used)
Xilinx Answer #4211 : A1.4/F1.4 MAP - FATAL_ERROR:x4kma:x4kmagrclapse.c:1001:1.90.12.8 - No route-thru available in pack_lutflop() to swap with H input pin 8
Xilinx Answer #4184 : A1.5/F1.5 XC3000 Map - GCLK is connected to non clock pin error - ERROR:x3kma:192
Xilinx Answer #4165 : A1.4/F1.4 MAP - ERROR: x4kma:312 - Following symbols could not be constrained
Xilinx Answer #4146 : M1.4/M1.5 Map - FATAL_ERROR:x4kma:x4kmaaclk.c:145:1.16.12.2 - More than one driver on clock net.
Xilinx Answer #4129 : MAP: baste:263- The LOC contraint is not valid for IPAD symbol, which is being mapped to the following site types: CLKIOB
Xilinx Answer #4112 : M1.4 Map - FATAL_ERROR:x4kma:x4kmagrclapse.c:1001:1.90.12.8 - No route-thru available in pack_lutflop() to swap with H input pin 8:
Xilinx Answer #4082 : M1.4 Map - Input signal driving two paths is corrupted.
Xilinx Answer #4081 : 1.5i, 2.1i Map- FATAL_ERROR:x4kma:x4kmaclkinfo.c:786:1.24 - Clkinfo: sitearray overrun: page1$1p/page1$i135.
Xilinx Answer #4080 : M1.4 Map - FATAL_ERROR:x4kma:x4kmacarry.c:2842:1.122.12.8 - Illegal call to swap
Xilinx Answer #4061 : M1.4 Map - Unable to RLOC tbufs to column 0: ERROR:baste:117 - RLOC_ORIGIN value ...
Xilinx Answer #4060 : M1.4 Map - Map creates TIMEGRPs in PCF file that are incorrect.
Xilinx Answer #4026 : M1.5, M1.4 MAP, COREGEN - ERROR:x4kma:387 - Unable to obey design constraints which require the combination of the following symbols into a single CLB: on RLOC'd Coregen RAM, FIFO's
Xilinx Answer #4025 : M1.4 Map - FATAL_ERROR:x4kma:x4kmawritengd.c:82:1.17 - F-LUT in map
Xilinx Answer #3988 : M1.4/M1.5 Map - Error: x4kma:215-the component AAA is a synchronous RAM, which is not available in the xc4000 architecture
Xilinx Answer #3943 : M1.4 map:ERROR:x52ap:13 - The comp (mapped physical logic cell) "blah" is not placed.
Xilinx Answer #3939 : M1.4 Map - WARNING:baspl:291 - The IOB component "io<0>" could not be placed.
Xilinx Answer #3933 : F1.4,M1.4,Map,license,Error: basse ... No such feature exists (-5,116)
Xilinx Answer #3903 : M1.4 Map - FATAL ERROR: Too many signals to move and not enough slots on comp
Xilinx Answer #3879 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:982:1.69.14.2 - NC_BEL ...
Xilinx Answer #3877 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...
Xilinx Answer #3876 : A1.4/F1.4 5200 Map - FATAL_ERROR:baste:basteparse.c:333:1.1
Xilinx Answer #3875 : A1.4/F1.4 Map - Map connects wrong LUT output to FFY D input
Xilinx Answer #3868 : M1.4 Map - FATAL_ERROR:baspm:baspmdevkey.c - Unable to load file or override file "mapl2ppins.acd"
Xilinx Answer #3867 : M1.5i/2.1i: Timing Analyzer: No default physical constraints file "\...\map.pcf" was found.
Xilinx Answer #3843 : A1.4/F1.4 Map - FATAL_ERROR:x4kmamerge.c:2858:1.145.12.11 - Too many signals to move..
Xilinx Answer #3831 : M1.4 LOGIBLOX: MAP may convert 5K Logiblox adder CY_MUX's to FG muxes and leaves buffers in.
Xilinx Answer #3822 : A1.4/F1.4 Map - Guided map crashes
Xilinx Answer #3821 : Foundation, MAP: Excessive logic removed (trimmed) from a design captured in Foundation schematic.
Xilinx Answer #3811 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:1333:1.69
Xilinx Answer #3810 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...
Xilinx Answer #3798 : MAP WARNING:x4kma:78 - STARTUP symbol "$I1" (output signal=<none>) conflicts with other symbol connections on the clock signal
Xilinx Answer #3786 : M1.4 Map - How to produce map reports with full details.
Xilinx Answer #3772 : A1.4/F1.4 Map - Map connects xc5200 readback symbol incorrectly.
Xilinx Answer #3768 : MAP M1.4: ABEL blocks in FPGA not optimized, result in high utilization (ERROR:x4kma:253 - The design is too large for the given device...)
Xilinx Answer #3766 : MAP M1.4: x4kma:312 - The following symbols could not be constrained to a single CLB (Two F-LUT's, an H-LUT, and carry logic).
Xilinx Answer #3761 : A1.4/F1.4 Map - MAP introduces DRC problem: WARNING:x4kdr:82 - Blockcheck: The pin "F1"...
Xilinx Answer #3760 : A1.4/F1.4 Map - FATAL_ERROR:basnc:basncsignal.c:262:1.62 - Could not find a
Xilinx Answer #3757 : Map: Removes logic that is tied to pads locked to Unbonded pins.
Xilinx Answer #3726 : A1.4/F1.4 MAP: Map corruption during logic replication loses HLUT connection.
Xilinx Answer #3725 : A1.4/F1.4 Map - FATAL_ERROR:x4kma:x4kmamerge.c:1561:1.145.12.7 - No flop rt available.
Xilinx Answer #3724 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...
Xilinx Answer #3723 : A1.4/F1.4 Map - Map crashes with segmentation fault for a particular case.
Xilinx Answer #3722 : A1.4/F1.4 Map - XC5200 combinatorial latch implemented wrong in a f5_mux.
Xilinx Answer #3706 : Foundation 1.4, MAP: ERROR:basnu:93 - logical block <instance number> of type "OBUF" is unexpanded... when OMUX2 is used in XNF netlist
Xilinx Answer #3665 : fatal error in map on a 4052xl design.
Xilinx Answer #3664 : M1.3/M1.4 Map: FATAL_ERROR:baste:bastetspec.c:1737:1.69
Xilinx Answer #3662 : M1.4, map, Fatal_Error:x4kma:x4kmacarry.c:2946:1.130 - Illegal call to swap...
Xilinx Answer #3661 : M1.4, map, Readback, NT, Dr.Watson: Exception: access violation...
Xilinx Answer #3655 : M1.4 MAP: FATAL_ERROR:x4kma:x4kmamerge.c:4429:1.145.12.5 - Missing signal on pin 10
Xilinx Answer #3618 : A1.4/F1.4 Map - Map enhancement to add support for guiding BUFGP/S for floorplanning
Xilinx Answer #3617 : A1.4/F1.4 Map - Map causes an invalid page fault inmodule libbaste.dll at...
Xilinx Answer #3616 : A1.4/F1.4 Map - Map runs out of memory on designs containing more than 64K logic primitives.
Xilinx Answer #3615 : MAP M1.4.12: FATAL_ERROR:x4kma:x4kmaclkbuf.c:591:1.25 - No input sig on CLKBUF inst_name.
Xilinx Answer #3563 : XC3000A: Map ignores LOC on pads driving BUFG
Xilinx Answer #3553 : LogiCORE PCI32 4000: MAP ERROR:x4kma:312 or x4kma:387- the following symbols could not be constrained to a single CLB
Xilinx Answer #3527 : M1.4 Map - FATAL_ERROR:basnc:basncsignal.c:262:1.62 - Could not find a bel for a signal...
Xilinx Answer #3526 : MAP M1.4 - Application error on XC4000E design during the "Optimizing" phase.
Xilinx Answer #3525 : M1.4 Map - 5200: Map is not trimming global reset signals
Xilinx Answer #3524 : M1.4 Map - Map creates an illegal IOB configuration with conflicting EC pin and OMUX usage.
Xilinx Answer #3508 : MAP: CY4 Symbol Errors. FPGA Express: Reading xnf or edf netlists into project.
Xilinx Answer #3474 : M1.3/M1.4 Map FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL U3/N1304 belong
Xilinx Answer #3451 : M1.4 Map - If mapper has errors, the map report (.mrp) doesn't contain trim information.
Xilinx Answer #3450 : MAP M1.4: ERROR:x4kma:312 - The following symbols could not be constrained...
Xilinx Answer #3449 : M1.4 MAP:FATAL_ERROR:basnc:basncsignal.c:262:1.62
Xilinx Answer #3448 : M1.4 Map - Map crashes for a specific case. A patch is available.
Xilinx Answer #3447 : MAP FATAL ERROR: Illegal situation for H1 pack.
Xilinx Answer #3440 : Map M1.4.12 ERROR:basut:162 - This Xilinx application has run out of memory
Xilinx Answer #3427 : M1.4 MAP: ERROR:x52ma:250 This type of signal is not supported by the XC5200 ...
Xilinx Answer #3421 : M1.4 MAP: ERROR: x4kma:111 -- Design is empty
Xilinx Answer #3407 : M1.4 MAP:ERROR:x4kma:371 - IBUF symbol "symbol_name" is unable to combine with ...
Xilinx Answer #3405 : M1.4 Map - Map will sometimes run FLUT to Flop connection through an HLUT routethru.
Xilinx Answer #3392 : M1.3 Map - FATAL ERROR:x4kma:x4kmacarry.c:681:1.96.10.4 - COUTO...
Xilinx Answer #3385 : M1.4,NT,Map,FATAL_ERROR:x4kma:x4kmagrclapse.c:1953:1.90.12.2 - No pin for sig...
Xilinx Answer #3381 : M1.4 Map - FATAL_ERROR:x4ema:x4emaclb.c:663:1.44:5.2 - Flop in Y found
Xilinx Answer #3379 : M1.4, Map, Error: FATAL_ERROR:x4kma:x4kmamerge.c:2460:1.145...
Xilinx Answer #3357 : M1.4 Map - Incorrect mapping leads to DRC warning about component pin with no signal attached.
Xilinx Answer #3314 : M1.4 Map - Map crashes trying to push buffer/inverter into hard macro (.nmc).
Xilinx Answer #3312 : M1.4 Map - ERROR:baste:262 - Bad format for LOC constraint
Xilinx Answer #3311 : M1.4 Map - Optimization of OFDT symbol results in dangling tri-state control pin
Xilinx Answer #3293 : MAP terminates abnormally after successfully writing output files (.ncd and .mrp).
Xilinx Answer #3269 : M1.4 MAP: NMC hard macro cannot be LOC'd from the UCF file
Xilinx Answer #3259 : Foundation/F1.3, MAP, baste Error: baste 164:components with same name...uniquifying.
Xilinx Answer #3251 : M1.4 Map - Mapper fails with Application Fault on EX and XL Devices on PC only.
Xilinx Answer #3250 : M1.4 Map - FATAL_ERROR:x4kma:x4kmacarry.c:2703:1.122 - Illegal call to swap.
Xilinx Answer #3247 : M1.4 Map - FATAL_ERROR:baste:bastecomp.c:564:1.72 - Moving BEL from U7451 to occupied belsite ...
Xilinx Answer #3246 : M1.4 Map - FATAL_ERROR:x4kma:x4kmamerge.c:2585:1.145.12.2 - Too many signals to move..
Xilinx Answer #3245 : M1.4 Map - Mapper unable to merge a RAM and Flop with opposite clock polarities
Xilinx Answer #3244 : M1.4 Map - FATAL_ERROR:x4kma:x4kmamerge.c:1879:1.145
Xilinx Answer #3243 : M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.
Xilinx Answer #3217 : M1.3/M1.4 MAP - Map crashes due to an illegal pad configuration.
Xilinx Answer #3204 : M1.4, Map, 5200,-r ,-pr , basut: Error:basut - Switch "-r" is not allowed.
Xilinx Answer #3196 : M1 MAP: What is an MDF file?
Xilinx Answer #3135 : M1.4 GUI: 'Optimize & Map' tab for 5k implementation template has an incorrect option
Xilinx Answer #3086 : M1.3 MAP:x4kma:x4kmagrclapse.c illegal situation for H1 pack:<block>
Xilinx Answer #3083 : M1 Map - ERROR - No more route-throughs available
Xilinx Answer #3062 : M1.3/1.4 - Fatal Error:basnp:basnpdevice.c:533.1.17 bad nph file (from map and other applications)
Xilinx Answer #3036 : M1.3 Map - Map will not push buffer (or logic optimized to buffer) forward into closed FMAP (MAP=PUC or PLC)
Xilinx Answer #2993 : M1.3 MAP: OPTX error -- ERROR: x4kdr: 7 (Foundation F1.3 specific)
Xilinx Answer #2930 : MAP M1.3/M1.4: "MAP = PUO" is ignored on HMAPs (HMAPs are always closed)
Xilinx Answer #2921 : MAP: BUFG net attached to a BUF with an X attribute gets distributed using local routing instead of being driven directly by a BUFG
Xilinx Answer #2914 : ** DUPLICATE of 2337 ** M1.2/M1.3/M1.4 MAP: Map complains about incompatible site types when expanding wildcard constraints--ERROR:x4kma - IBUF symbol `$1I89' is unable to combine with IO RESET
Xilinx Answer #2893 : M1.4 Map: DROP_SPEC property takes priority over other TIMESPECs regardless of where it is specified in the flow
Xilinx Answer #2892 : M1.4: TIMESPEC paths originating from .NMC macros (physical macros) do not get written by Map to the .PCF file
Xilinx Answer #2884 : ** OBSOLETE ** M1.3: Map removes IBUF along with unused OBUFT in a bidirectional I/O
Xilinx Answer #2827 : M1.3.7 Map - Map incorrectly trims an INFF that is combined with unused OFDT
Xilinx Answer #2826 : M1.3.7 Map - Map writes bad data to .ngm file corupting simulation results
Xilinx Answer #2825 : M1.3.7 Map - Map doesn't pass a TPTHRU consraint to .pcf file to relax constraint
Xilinx Answer #2824 : M1.3.7 Map - Map seg faults on a particular design
Xilinx Answer #2822 : M1.3.7 Map - FATAL_ERROR:basnc:basnccomp.c:3221:1.90.14.3 - Cannot find other bel...
Xilinx Answer #2821 : M1.3.7 Map - Guided map operation fails with core dump
Xilinx Answer #2820 : M1.3.7 - Map swaps two bits of a bus corrupting logic
Xilinx Answer #2819 : M1.3.7 Map - Map doesn't preserve the logic for Logiblox 4-bit binary down counter.
Xilinx Answer #2818 : M1.3.7 Map - FATAL_ERROR:x4kma:x4kmacarry.c:2456:1.96 - Illegal call to swap.
Xilinx Answer #2817 : M1.3 Map - Map incorrectly handles CLB latches from Logiblox
Xilinx Answer #2816 : M1.3.7 Map - Map incorrectly optimizes FDC to VCC.
Xilinx Answer #2815 : M1.3.7 Map - Map incorrectly configures a CIN net.
Xilinx Answer #2814 : M1.3.7 Map - FATAL_ERROR:x4kma:x4kmamerge.c:2371:1.120 Too many signals to move...
Xilinx Answer #2813 : M1.3.7 Map - Map incorrectly complains about .FFX RLOC property in coregen multiplier
Xilinx Answer #2812 : Map M1.3.7 - Map fails with page fault when run from Design Manager for a paticular design
Xilinx Answer #2811 : M1.3.7 Map - Map fails with seg fault on a particular design
Xilinx Answer #2810 : M1.3.7 Map - FATAL_ERROR:baste:bastetspec.c:946:1.64 - No NC_SIGNAL for TECHMAP_SIG on BEL...
Xilinx Answer #2809 : M1.3.7 Map - Wrong LUT is connected to FF resulting in corrupt logic.
Xilinx Answer #2808 : M1.3.7 Map - Inverter is incorrectly pushed into a closed FMAP.
Xilinx Answer #2758 : M1.3/M1.4 MAP: unclear messages about FDCEs being "covered by optimization" in the MAP .mrp file when the -os option is specified
Xilinx Answer #2753 : M1.3 MAP: On a bidirectional I/O, the INFF and pad are also trimmed even though only the OUTFF is dangling
Xilinx Answer #2714 : M1.3.7-pc: map FATAL_ERROR:basnc:basncsignal.c:262:1.61 - could not find a bel for a signal on pin G2
Xilinx Answer #2700 : 1.5i MAP ERROR:basnu - logical block "core/data" of type "INC_DEC_TWO_COMP_6" is unexpanded.
Xilinx Answer #2680 : M1.3/M1.4: MAP -os and -oe optimization options: When to use them (XABEL, Metamor designs), why results may not improve
Xilinx Answer #2666 : MAP: The meaning of the Map packing strategy options
Xilinx Answer #2641 : M1.2 MAP: Problems with map3_nt.zip patch when installed in MYXILINX directory on Windows NT and Win95 systems: FATAL_ERROR:baspm:baspmdlm.c fail to open libx4kma.dll
Xilinx Answer #2492 : MAP Error: ld.so.1: map: fatal: relocation error: symbol not found:
Xilinx Answer #2483 : M1.2/M1.3/M1.4 MAP: Refsite is unavailable / Constraining overlapping RPMs to the same CLB range (RPM "zippering") is not supported
Xilinx Answer #2474 : M1 LOGIBLOX: How to estimate CLB,/area/resource utilization for LogiBLOX modules with Map
Xilinx Answer #2457 : M1.2 MAP: Input flip-flops in a bidirectional I/O get removed due to optimization of an output flip-flop whose input is tied to GND.
Xilinx Answer #2418 : M1: MAP->"FATAL_ERROR:baste:bastetspec.c:908:1.64 - No pins of NC_SIGNAL ... NC_BEL
Xilinx Answer #2417 : SYNOPSYS: Logical Library does not map to a host directory.
Xilinx Answer #2413 : MAP: "ERROR:x4kma-Unable to obey design constraints" with Synplify netlist
Xilinx Answer #2397 : M1.3 MAP: User-defined TIMESPEC constraints added outside the "SCHEMATIC" section of the .PCF file are commented out by MAP
Xilinx Answer #2367 : M1.3 MAP: MAP DRC does not check the validity of RLOC and LOC location constraints on fast carry logic
Xilinx Answer #2366 : 1.5i 4K* Map - ERROR: BLKNM parameter not supported on WAND symbol (4K family)
Xilinx Answer #2364 : 1.5i 4K* Map - "ERROR 0 - FMAP symbol - RLOC parameter suffix doesn't match block type" on single-flip-flop macros
Xilinx Answer #2363 : 1.5i MAP: How can I estimate the total number of packed CLBs in my design?
Xilinx Answer #2362 : M1.3 MAP: What do "Clock IOBs" mean in the MAP report ?
Xilinx Answer #2345 : M1.3 MAP: "Unable to obey design constraints" errors / Unsupported CLB combinations involving dual output logical components (DPRAM, RAM16x2)
Xilinx Answer #2337 : 1.5i, 2.1i Map - "place instance *" constraint causes ERROR:x4kma:148 - IBUF symbol cannot be merged, incompatible site types
Xilinx Answer #2332 : 1.5i Map: How to ignore RLOCs / Map does not have a built-in ability to ignore RLOCs completely (or, the meaning of the MAP "-ir" option)
Xilinx Answer #2319 : ** OBSOLETE ** M1.3 MAP gives misleading error: ERROR:0 - BLKNM parameter not supported on WAND symbol
Xilinx Answer #2317 : ** OBSOLETE ** M1.3 MAP: The design summary section of the map report file (.mrp) is ambiguous.
Xilinx Answer #2312 : 1.5i, 2.1i 4K* Map - 'ERROR: baste:125 - The RLOC value of "R62C2.FFY" on CLB .... in RPM ....'. The design is too large for the given device and package (can't fit design).
Xilinx Answer #2309 : 1.5i Map - MAP does not report which TIMESPEC is used when there are duplicate TIMESPECs
Xilinx Answer #2308 : M1.3 MAP: Map doesn't validate PROHIBIT constraints before writing them out.
Xilinx Answer #2301 : M1.3 MAP: ERROR:x4kma:312 - Unable to obey design constraints which require the combination...
Xilinx Answer #2298 : M1.3/M1.4 MAP may generate Wide Decoder groups that cannot be placed/routed.
Xilinx Answer #2295 : M1.3 MAP: Version number of Mapper is not reported in the .MRP report file
Xilinx Answer #2291 : M1.3 MAP: Unable to pack CLB driven by 2 external signals with DFFs sharing an SR signal.
Xilinx Answer #2289 : 1.5i MAP, XC4000E/L/EX/XL: Map cannot use the DI input to source an HMAP (xc4000e/ex/xl)
Xilinx Answer #2288 : M1.5/M1.4/M1.3 MAP: BEL-level PROHIBIT constraints are not supported
Xilinx Answer #2281 : M1.5/M1.4/M1.3 MAP: Automatic insertion of GSR/GR is not supported in M1.
Xilinx Answer #2280 : M1.3/M1.4 Map: Map fails to pack RLOC'd carry logic in RPMs (Relationally Placed Macros) with LOC'd DFFs.
Xilinx Answer #2274 : M1 MAP: Designs which fit a target XC4000/E/L device in XACT may not fit when mapped with the M1 Mapper due to register ordering
Xilinx Answer #2260 : M1 MAP: Running map with -os area may yield a larger implementation than with -oe normal
Xilinx Answer #2249 : M1 MAP, XC4000EX CCxxCLE counter library macros: WARNING:x4kma - Signal xxx on pin G4 of CY4 symbol is not required by carry mode INC-F-CI
Xilinx Answer #2232 : M1.2.11 MAP: FATAL_ERROR:x4kma:x4kmabel.c:161:1.37 - Didn't find out signal on bel G
Xilinx Answer #2207 : M1 Map: What are the rules for merging FFs into an IOB with the MAP -pr b switch?
Xilinx Answer #2193 : M1 Map - Warning:baste:102 - Logic enclosed by Fmap symbol '..' has too many inputs
Xilinx Answer #2191 : M1 Map - FATAL_ERROR:baste:bastetspec.c:2317:1.62 - NET OFFSET...
Xilinx Answer #2072 : M1 Map - A parsing error has occurred at line 2, token 'P124'.
Xilinx Answer #1972 : Foundation Express 2.0.x: multiple modules in Foundation schematic can cause RLOC error:x4kma:312 in MAP
Xilinx Answer #1818 : M1.2/M1.3/M1.4 MAP: Exact Guide Mode May Not Recreate All COMPs from Initial Design Even When the Source Design Has Not Changed
Xilinx Answer #1810 : M1.3 MAP: BLKNM, HBLKNM, RLOC and LOC Properties May Not be Respected by MAP in Some Instances
Xilinx Answer #1778 : Design Summary is Located at the End of the MRP (Map Report) File
Xilinx Answer #1777 : Problems with Back-Annotation of Designs Containing Single CLB Replication Groups which are Not Eliminated by MAP
Xilinx Answer #1637 : M1-Pre: How to get MAP to report number of flip-flops, LUTs used
Xilinx Answer #1633 : XEPLD, XC7318, XC7336: nd100:[Error] (nd105, hi317) Could not map '<instance>' into a fast function block. (Fast Output Enables, FOE)
Xilinx Answer #1632 : XEPLD, XC7318, XC7336: nd100:[Error] (nd104, hi317) Could not map '<instance>' into a fast function block. (Fast Clocks)
Xilinx Answer #1101 : Men2XNF8/ENWrite error: "Pin does not map to a net in model" due to incorrect COMPMC16 macro
Xilinx Answer #382 : PPR 5.0: May ignore MAP=PLC on XC3000A CLBMAP symbols
Xilinx Answer #198 : SYN2XNF: issues ERROR 220: 'can't find &__logic_1__.map'