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Xilinx Answer #8324 : FPGA Compiler 2, version 3.3.1: Bidirectional pads may cause multiple driver error in Translate (NgdHelpers:336)
Xilinx Answer #8254 : FPGA Compiler, Design Compiler: How do I pass the IOSTANDARD constraint for Virtex designs?
Xilinx Answer #8202 : Virtex-E FPGA Express 3.3: How to instantiate special Virtex-E I/O standards (LVDS, LVPECL)
Xilinx Answer #8137 : FPGA Express 3.3: Converting Constraints (.EXC) to ASCII or TCL and adding Constraints to the FE_SHELL
Xilinx Answer #8067 : FPGA Express: Can not create chip - Unknown error
Xilinx Answer #8048 : FPGA Express 3.x: Can't see feslw30.dll in path on Windows NT
Xilinx Answer #7994 : 2.1i: VHDL simulation of XDW module COMP_LT_UBIN_x gives wrong results
Xilinx Answer #7812 : FPGA Express 3.x: Address lines unconnected when SRL16 components are instantiated (FPGA-CHECK-7)
Xilinx Answer #7758 : FPGA Express 3.3, NCF: ERROR:TSDatabase:19 ...No TNM, TPSYNC or user group named "nco1_N214" is defined
Xilinx Answer #7623 : Foundation Express 2.1i, SpartanXL: The CS144 and CS280 packages are missing in the device list
Xilinx Answer #7497 : FPGA Express 3.x: Express inverting load/clock signal for 4000/Spartan input latches
Xilinx Answer #7470 : XSI Libraries 2.1i: Bidirectional I/O has extra inversion inferred (IOBUF_N)
Xilinx Answer #7427 : FPGA Express 3.x: NCF file will not work with XNF files and "Preserve Hierarchy" (NgdHelpers:14)
Xilinx Answer #7411 : FPGA Express: Express does not know about dedicated clock pads
Xilinx Answer #7407 : FPGA Express 3.2: Crashes (Dr. Watson) after "Force Update" project or chip
Xilinx Answer #7382 : FPGA Express 3.2: Synopsys Internal Error, Abort at 219
Xilinx Answer #7353 : Foundation 2.1i: Can not load Xilinx license dll
Xilinx Answer #7339 : 2.1i Virtex Libraries - Updated Virtex XSI libraries with preliminary speeds -4 -5 will become available in 2.1i SP2.
Xilinx Answer #7323 : FPGA Express 3.x: Global Clock Buffer is inserted, ignoring DONT USE in Express Constraints Editor
Xilinx Answer #7291 : FPGA Express: BSCAN_VIRTEX is removed from the design without warning
Xilinx Answer #7271 : Synopsys Design Compiler / FPGA Compiler: Can't make an adder in Synopsys bigger than 48-bits
Xilinx Answer #7267 : Foundation 2.1i Installer: setup.exe failed with error code 15
Xilinx Answer #7240 : Foundation 2.1i, FPGA Express 3.2: Is it possible to infer signed arithmetic modules in VHDL or Verilog?
Xilinx Answer #7160 : FPGA Compiler, FPGA Express: What netlist formats are supported for Xilinx devices?
Xilinx Answer #7097 : FPGA Express 3.x: Virtex/E flip flops are not merged into the IOB
Xilinx Answer #7000 : A2.1i: Synopsys Designware libraries compiled for 1998.02 and 1997.08
Xilinx Answer #6958 : Synopsys Design/FPGA Compiler: Cannot find a valid implementation for module 'xdw_comp_uns'. (SYNH-14)
Xilinx Answer #6879 : Foundation Express F2.1i: When will the "zero-one-hot" synthesis option be supported?
Xilinx Answer #6808 : FPGA Express 3.2: Pullup/pulldown/keeper for Virtex are incorrectly written to the netlist
Xilinx Answer #6669 : FPGA Express: STARTBUF is not recognized as STARTUP block
Xilinx Answer #6655 : FPGA Express 3.2: LOC attribute not passed from HDL source
Xilinx Answer #6648 : Foundation Express: How to access the version information of Synopsys FPGA Express
Xilinx Answer #6607 : FPGA Express 2.x,3.x: Express hangs while checking syntax (Abort at 1704)
Xilinx Answer #6588 : Synopsys FPGA Compiler 1998.08/1999.05: Slew rate specifications on Virtex IOBs are ignored during synthesis.
Xilinx Answer #6539 : Foundation Express 2.1i: "CONV: line X Wrong number of fields BUS" when creating HDL macro
Xilinx Answer #6533 : Foundation Express: Cannot send "Create Version" window to the background during synthesis
Xilinx Answer #6436 : Foundation Express 2.1i: FPGA Express 3.3 is available in Service Pack 2
Xilinx Answer #6431 : FPGA Express 3.3: The "dont_touch" attribute is now available
Xilinx Answer #6298 : FPGA Compiler II, FPGA Express: FST scripting tool: Compiler directives for using pullups/pulldowns
Xilinx Answer #6282 : Logic Modelling: smartccn fails when using back-annotated EDIF created with .NGM file (error 11032: no package pin connected)
Xilinx Answer #6236 : FPGA Express 3.1: Virtex: May not always infer the MUXF5 / MUXF6
Xilinx Answer #6192 : Synopsys FPGA Compiler: writes out absolete timing constrains in XNF (basnu:179)
Xilinx Answer #6165 : FPGA Express: Signal or port name expected as actual in association element (VSS-806)
Xilinx Answer #6085 : FPGA Express: How to instantiate I/O pads in your HDL code
Xilinx Answer #6080 : Foundation F1.5i: Upgrading your Foundation Express license to 3.1
Xilinx Answer #6013 : FPGA Express: Verilog keyword "tri" causes Express to crash (Cannot create chip in Synopsys project) (Abort at 470)
Xilinx Answer #5972 : FPGA Express 3.1: unexpected errors, access violation (0xc0000005), Dr. Watson
Xilinx Answer #5959 : FPGA Express 3.1: VHDL syntax error on "alias" statement VSS-1081 (not supported)
Xilinx Answer #5958 : FPGA Compiler / Design Compiler: LUT programming information dropped for Virtex designs (NgdHelpers:406)
Xilinx Answer #5952 : FPGA / Design Compiler 1999.10: Synthesizing with Synopsys version 1999.10 may give UISN-27 error
Xilinx Answer #5800 : FPGA Express 3.3: Inferring SRL16 and SRL16E components for Virtex/E devices
Xilinx Answer #5791 : FPGA Express 3.2: Verilog pre-processor available to allow 'ifdef, 'else, and 'endif
Xilinx Answer #5777 : A1.5i: XC4000XV Synopsys synthesis and designware files are available
Xilinx Answer #5751 : 2.1i Design Compiler - Typo in template .synopsys_dc.setup file (PARSE-1)
Xilinx Answer #5706 : FPGA / Design Compiler 1999.05: Using SYNLIBS settings produces warning UISN-26
Xilinx Answer #5698 : FPGA Express 3.x: Error: Target 'L' is incompatible with assigned value in routine "=" line 490 when using IEEE.numeric_std (HDL-40)
Xilinx Answer #5690 : Foundation Express: VHDL files for user libraries are not found if project is moved
Xilinx Answer #5683 : F1.5is1, Express 3.1: Incorrect speed grades listed for XC4000XLA family
Xilinx Answer #5682 : FPGA Express: Inserts OBUF when instantiating OBUFE in HDL design
Xilinx Answer #5650 : F1.5 Express: Warning: The pin from <A> of <B> has no corresponding port <C> on the design. FE-LINK-7
Xilinx Answer #5633 : FPGA Express: Syntax error at or near token 'bxx (VE-0)
Xilinx Answer #5631 : Foundation Express v3.1 available in F1.5i Service Pack 1 via Web
Xilinx Answer #5612 : Foundation Express: Cannot find license file (-1,73:2) after installing 1.5i Service Pack
Xilinx Answer #5601 : Foundation Express: Cannot create chip in Synopsys project
Xilinx Answer #5506 : FPGA Express: out of virtual memory error. synopsys internal error 217
Xilinx Answer #5432 : FPGA Express 3.1: NUMERIC_STD package available for Express 3.0 or 3.1
Xilinx Answer #5405 : F1.5 Express: INOUT port declaration synthesized as an output only (FE-PMAP-18)
Xilinx Answer #5390 : FPGA Express: Warning: No global set/reset (GSR) net can be used in the design .. (FE-GSRMAP-8)
Xilinx Answer #5388 : FPGA Express: Unlinked modules when black box modules are instantiated. (FE-LINK-2)
Xilinx Answer #5382 : Foundation Express: How to access the schematic viewer (Vista)
Xilinx Answer #5359 : FPGA Express 3.x: error: can't find type information (.typ file) for filename (HDL-353)
Xilinx Answer #5334 : FPGA Express 3.x: Instantiating LUTs for Virtex/E designs
Xilinx Answer #5325 : FPGA Express: Information about the Duplicate Register Merge feature
Xilinx Answer #5301 : FPGA Express: Error L-1/C0 : #0 Not enough storage is available to complete this operation.
Xilinx Answer #5257 : Foundation Express F1.5/i: Synopsys Internal error - Abort at 1548 : Server threw an exception (1546, 124)
Xilinx Answer #5252 : M1.5/1.5i: Methods to reduce simulation time in VSS
Xilinx Answer #5114 : FPGA Express 3.3: Abort at 59 occurs when parallel logic is coded
Xilinx Answer #5063 : M1.5/Synopsys: FPGA designs containing STARUP/STARTBUF component may not configure properly when using FPGA/Design Compiler for design entry
Xilinx Answer #5048 : Synopsys, Virtex: replace_fpga and uniquify should not be used during synthesis using FPGA/Design Compiler (NGDHelpers 406)
Xilinx Answer #5043 : FPGA Express: DPM: error: tried to use synchronized value in routine
Xilinx Answer #5008 : FPGA Express: modules for black boxes (LogiBLOX, CoreGen) must be declared in Verilog designs; clock pins missing
Xilinx Answer #4995 : F1.5,2.1i security: When does FPGA Express check out a floating license?
Xilinx Answer #4981 : FPGA Express: How to access Carry-In when building arithmetic functions
Xilinx Answer #4972 : FPGA Express: Inferred latches always use LD_1 component instead of other primitives (LDCE, LDC)
Xilinx Answer #4969 : F1.5 Express/VHDL: multiple architectures for a single entity is not supported
Xilinx Answer #4967 : Foundation F1.5: Foundation HDL tabs do not allow local menu options to save Express messages
Xilinx Answer #4963 : FPGA Express 3.x: How to access special IOB components for Virtex/E
Xilinx Answer #4949 : FPGA Express: Implementing efficient multipliers in VHDL or Verilog
Xilinx Answer #4945 : Synopsys FPGA/Design Compiler: How to use the TRANSLATE_OFF and TRANSLATE_ON pragmas
Xilinx Answer #4930 : FPGA Express 2.1.3 - Cannot allocate CLK to BUFG using Constraints Editor
Xilinx Answer #4923 : Foundation Express F1.5i/2.1i: HDL macros cannot have hierarchy or user VHDL libraries
Xilinx Answer #4880 : Foundation Express F1.5: When are constraints applied from the Express Constraints Editor?
Xilinx Answer #4867 : FPGA Express: all combinatorial logic is mapped by Express
Xilinx Answer #4812 : FPGA Express: Entity depends on std_logic_1164 which has been analyzed more recently. LBR-28
Xilinx Answer #4805 : FPGA Express 2.x, 3.x - Cannot Export netlist from Synopsys - For unknown reasons the operation could not be completed.
Xilinx Answer #4803 : Foundation 1.5, FPGA Express 2.1.x: Express Constraints GUI is missing Xilinx Options tab
Xilinx Answer #4791 : FPGA Express: Clock buffers cannot be assigned on INOUT ports in Express Constraints Editor
Xilinx Answer #4787 : F1.5 Foundation Express: Error cannot open the <path>/workdirs/WORK/<file>.sim for writing. Directory does not exist vss-77 fe-dm-hdlc-unknown.
Xilinx Answer #4714 : FPGA Express: Can I change the HDL text editor to an editor other than the default Synopsys editor?
Xilinx Answer #4708 : Foundation F1.5i/2.1i: Cannot initialize Automation - cannot find Synopsys registry
Xilinx Answer #4689 : FPGA Express 2.x, HDL-178: Bus slices are not supported in sensitivity list
Xilinx Answer #4688 : Foundation Express: Warning during synthesis: L0/C0 another process already started. Operation cancelled.
Xilinx Answer #4671 : A1.5, XSI, Virtex: Error: Either a NOR, or an AND and an OR gate (two-input) is required for mapping.
Xilinx Answer #4666 : XSI_LIBS A1.5: Updated Virtex libraries availible for Synopsys FPGA/Design Compiler availible on FTP site
Xilinx Answer #4644 : FPGA Express: CONV_STD_LOGIC_VECTOR converts integers to signed values only (HDL-71)
Xilinx Answer #4629 : FPGA Express 2.1.3: Error: Clock variable is being used as data (HDL-175).
Xilinx Answer #4592 : FPGA Express: Using don't cares in VHDL
Xilinx Answer #4588 : FPGA Express 2.x: Express ignores SRL instantiations for Virtex designs.
Xilinx Answer #4587 : Foundation F1.5: Upgrading your Foundation Express license to 2.1.x
Xilinx Answer #4492 : FPGA Express: Cannot have complex expression in always block sensitivity list (VE-92)
Xilinx Answer #4489 : A1.5/XSI: Updated XC4000XLA-09 XSI synthesis and simulation files are available on the Xilinx FTP site 12/8/98
Xilinx Answer #4443 : Foundation Express F1.5: Instantiation of output cell with non-LVTTL voltage standard crashes Express
Xilinx Answer #4435 : F1.4, Express, security: Error$: Feature license file format or misspelling...(-90,313)
Xilinx Answer #4407 : FPGA Express: leaving pins open on VHDL component instantiations (VSS-538, VSS-544)
Xilinx Answer #4403 : Synopsys 1998.02: compile_fix_multiple_port_nets variable is obsoleted.
Xilinx Answer #4395 : Express does not preserve instantiated FMAP / HMAP / LUT primitives
Xilinx Answer #4394 : Foundation F1.5: Selecting the default FSM encoding scheme for Express HDL designs
Xilinx Answer #4392 : Foundation Express: Attribute passing is available beginning with version 3.0
Xilinx Answer #4385 : FPGA Express: How to instantiate Xilinx Library elements (primitives or macros) in your HDL
Xilinx Answer #4377 : FPGA Express VHDL: Which libraries are needed for std_logic_vector addition/subtraction?
Xilinx Answer #4376 : FPGA Express: How to assign standard logic vectors as Hex or Octal values
Xilinx Answer #4345 : FPGA Compiler Verilog: Example of how to infer "set" flip-flop when GSR is asserted
Xilinx Answer #4335 : FPGA Express: Use of predefined attributes with non-static alias range is not supported
Xilinx Answer #4304 : FPGA Express v2.0.3: Express reports that "Export of Chip Failed" or similar message when trying to export XNF netlist
Xilinx Answer #4291 : FPGA Express 2.x: fatal error may occur when modifying existing project in newer version of Express
Xilinx Answer #4281 : Foundation F1.5: Changing Synthesis Options gives ambiguous "force updated" message
Xilinx Answer #4239 : A 1.4 UNISIM XDW : INC_DEC_UBIN_6 does not simulate correctly
Xilinx Answer #4200 : FPGA Express 2.x, 3.x: Constraints Editor will not allow assignment of more than 4 BUFGs
Xilinx Answer #4185 : FPGA Express: How to disable clock period specification
Xilinx Answer #4122 : FPGA Express: Subpaths containing pads grouping incorrectly written by Express
Xilinx Answer #4047 : FPGA Express: Constraints GUI uses lower level heirarchical clock name
Xilinx Answer #3999 : FPGA Express 2.0.x: Instantiating I/O in Verilog.
Xilinx Answer #3993 : A1.4/A1.5 XSI: What to do when insert_pads fails in FPGA Compiler
Xilinx Answer #3992 : FPGA Express: How to implement a Synchronous Reset in VHDL or Verilog
Xilinx Answer #3980 : FPGA Express: Instantiating I/O in VHDL.
Xilinx Answer #3900 : FPGA Express VHDL: Type mismatch on left and/or righ operand of binary operator. (VSS-523)
Xilinx Answer #3781 : FPGA Express: "XNF Bus style" checkbox in Synthesis->Options->Project defined
Xilinx Answer #3735 : FPGA Express: Concatenating select bits of mux causes error VSS-1029
Xilinx Answer #3705 : Foundation Express, XC9500: Recommended synthesis and fitter options for CPLDs
Xilinx Answer #3679 : FPGA Express 2.0/Synopsys: RISING_EDGE vhdl syntax not supported. (VHDL-2204)
Xilinx Answer #3624 : FPGA Express v2.x (Foundation & Alliance): How to install FPGA Express v2.x for use on a PC network
Xilinx Answer #3583 : FPGA Express: How to avoid latch inferences
Xilinx Answer #3566 : FPGA Express 2.0, Foundation Express 1.4: Patch version 2.0.3 available
Xilinx Answer #3564 : FPGA Express 2.0: Selecting Synthesis->Options causes Express to crash
Xilinx Answer #3541 : F1.4, Demo License, Docs, Features: Demo license prevents use of Constraints GUI in Express
Xilinx Answer #3506 : Foundation\FPGA Express: Adding new libraries for Express projects
Xilinx Answer #3480 : Foundation F1.4: Upgrading your Foundation Express license to 2.0.x
Xilinx Answer #3477 : Foundation Express 2.0: Module compile inserts STARTUP and clock buffers (BUFG)
Xilinx Answer #3436 : FPGA Express: Instantiations in HDL are UNLINKED (FE-CHECK-4) (FE-LINK-2)
Xilinx Answer #3402 : FPGA Express 1.2/2.0/F1.5 : clock buffer not inserted if clock net sources RAMs or Black Boxes
Xilinx Answer #3308 : FPGA Express 2.0: Turbo Mode may cause Alliance version of FPGA Express to crash
Xilinx Answer #3301 : FPGA Express 2.0/Foundation 1.4: Creating HDL Macros with FPGA Express 2.0 for Placement on a Foundation 1.4 Top-Level Schematic
Xilinx Answer #3300 : FPGA Express 2.0: Errors/Warnings/Messages window does not always work correctly
Xilinx Answer #3296 : FPGA Express 2.x/3.x: Optimization gives FE-PADMAP-3 error
Xilinx Answer #3235 : F1.4, FPGA Express 2.0: Inverting Pin on HDL instantiation does not work
Xilinx Answer #3224 : FPGA Express 2.x/3.0: Comparators may not infer carry logic
Xilinx Answer #3018 : FPGA Express v1.2/Foundation 1.3: Simulating with FPGA Express v1.2 HDL and F1.3 Logic Simulator
Xilinx Answer #3013 : FPGA Express 1.2/Foundation 1.3: Creating HDL Macros with FPGA Express 1.2 for Placement on a Foundation 1.3 Top-Level Schematic
Xilinx Answer #3010 : FPGA Express: Instantiating an EDIF from a Foundation Schematic into a top-level FPGA Express Verilog or VHDL Design
Xilinx Answer #3003 : Synopsys FPGA Compiler: Error code "VE-0" from analyze command in dc_shell
Xilinx Answer #2996 : dc2ncf: How do you use the set_max_delay as a substitute for the set_multicycle_path command?
Xilinx Answer #2968 : FPGA Express: Where the IEEE and SYNOPSYS VHDL Libraries are located
Xilinx Answer #2888 : FPGA Express 1.2, 2.0: XC4000 Global Buffer constraints: ERROR:baste:263
Xilinx Answer #2865 : FPGA/Design Compiler: How to instantiate LogiBLOX in the Synopsys VHDL or Verilog Flow
Xilinx Answer #2843 : FPGA Express v1.2: Script to convert EXT records to SIG records for module generation
Xilinx Answer #2738 : M1.3/FPGA Express v1.2: Modular (Black-Box) Instantiation in Express
Xilinx Answer #2735 : M1.3/1.4 and FPGA Express: M1 Constraints, LogiBLOX, and modules within FPGA Express
Xilinx Answer #2734 : FPGA Express/M1.3: HDL Simulation of HDL only designs synthesized with FPGA Express
Xilinx Answer #2723 : FPGA Express: Program does not start after double-clicking on icon
Xilinx Answer #2657 : Synopsys FPGA/Design Compiler: Error: The entity 'add_sub_ub' depends on the package 'std_logic_arith' which has been analyzed more recently.
Xilinx Answer #2500 : SYNOPSYS FPGA/Design Compiler: How to constrain I/O pins in Synopsys designs (I/O pin locking)
Xilinx Answer #2495 : FPGA Express 3.x: No MUX_OP inferred for the case (HDL-380)
Xilinx Answer #2415 : FPGA Express v1.2: LogiBLOX in the FPGA Express v1.2 Verilog or VHDL M1.3 Flow
Xilinx Answer #2387 : vhdldbx: Error vhdlsim, 259 sdf file line ##: instance xsim4 not found.
Xilinx Answer #2311 : Synopsys vhdlan: Common issues/solutions re-compiling the M1.3/M1.4 XSI simulation libraries
Xilinx Answer #2282 : FPGA Express: Individual bits of a bus cannot be used as clock signals
Xilinx Answer #2275 : FPGA Express 2.x: Undefined macro 'ifdef, VE-0
Xilinx Answer #2254 : FPGA Express: warning given: "'xxx/GC' (or /GS) is not connect to any net..."
Xilinx Answer #2245 : M1 (FPGA/Design Compiler): Versions of Synopsys compatible with the Xilinx Alliance software
Xilinx Answer #2230 : FPGA Express: Using RLOC_ORIGIN with Express RPMs
Xilinx Answer #2220 : Foundation Express: Edit Constraints option greyed out; cannot access Constraints GUI
Xilinx Answer #2197 : What are the differences between Synopsys FPGA Compiler and Design Compiler?
Xilinx Answer #2167 : Synopsys: How to specify slew rates in Synopsys FPGA Compiler or Design Compiler?
Xilinx Answer #2089 : M1/FPGA Compiler: Sometimes set_false_path/set_max_delay not translated by write_script
Xilinx Answer #2080 : SYNOPSYS 3.x: Set_max_delay attribute is not passed on to .sxnf
Xilinx Answer #2061 : FPGA Express, FPGA Compiler II: How to obtain information on shell commands (FST)
Xilinx Answer #1947 : FPGA Express v1.xx: App note available on FPGA Express XACT 5.2.x flow and M1 flow
Xilinx Answer #1802 : Synopsys FPGA Compiler: Error OPT-101: The target library does not contain inverter.
Xilinx Answer #1785 : SYNOPSYS: How to force a IOB NODELAY latch or flip-flop?
Xilinx Answer #1784 : Synopsys Design Compiler: insert_pads->"This site is not licensed for FPGA compiler"
Xilinx Answer #1709 : XC3000 Synopsys Libraries: XC3100A -1 and -09 .db files available for users of XSI 5.2.1 & Synopsys 3.3b
Xilinx Answer #1708 : XC4000E Synopsys Libraries: XC4000E -2 .db files available for users of XSI 5.2.1 & Synopsys 3.3b and above
Xilinx Answer #1670 : SYNOPSYS : The output of replace_fpga still contains CLB element/write command fails in FPGA Compiler
Xilinx Answer #1521 : syn2xnf : ERROR 220: Can't open file '__ffgen__.xnf'
Xilinx Answer #1500 : FPGA Express: Does FPGA Express have any 'scripting' capability?
Xilinx Answer #1483 : FPGA Express: How do you specify slew rate in FPGA Express?
Xilinx Answer #1481 : FGPA Express: How do you use pullups or pulldowns?
Xilinx Answer #1477 : FPGA Express/Compiler: Possible Incorrect Logic with downto Range Integer Comparison in VHDL
Xilinx Answer #1459 : How to get the pin order of a XSI Library Cell in Synopsys or How to get the pins names for a XSI library cell
Xilinx Answer #1458 : Synopsys: Where can I get a list of all components I am able to instantiate? How can I get a listing of all library cell names in a XSI Library?
Xilinx Answer #1455 : XACT/SYNOPSYS: XSI 5.2.1 .db files for synthesizing 5210-4, 5215-5, and 5215-6
Xilinx Answer #1325 : FPGA Express: Cannot find type information (.typ) for IEEE.STD_LOGIC_1164.STD_LOGIC (HDL-353)
Xilinx Answer #1323 : FPGA Express: What Xilinx software is needed if FPGA Express is the design entry tool
Xilinx Answer #1166 : XSI Libraries: Synopsys libraries (pre- A2.1i) analyzed for older versions of Synopsys
Xilinx Answer #1127 : SYNOPSYS: The entity .. depends on the package std_logic_arith. Reanalyze the source
Xilinx Answer #857 : Synopsys: XC5200: clock inversion is implemented in a function generator, not at the flip-flop.
Xilinx Answer #640 : FPGA Express 3.x: Expression is ambiguous (VSS-501)
Xilinx Answer #630 : SYNOPSYS: How to tell what version of XSI (Xilinx-Synopsys Interface) you have.
Xilinx Answer #564 : FPGA COMPILER: PULLUPs/PULLDOWNs must be instantiated when using Synopsys.
Xilinx Answer #549 : SYNOPSYS: How to invert the reset (GSR/GR) pin on the STARTUP block?
Xilinx Answer #542 : XSI/SYNOPSYS: Constraining I/O pin locations from within Synopsys.
Xilinx Answer #538 : Obsolete: XC7000, SYNOPSYS FPGA/Design Compiler: Example .synopsys_dc.setup file
Xilinx Answer #537 : Obsolete: XC3000, SYNOPSYS Design Compiler: Example .synopsys_dc.setup file
Xilinx Answer #534 : Obsolete: XC4000, SYNOPSYS Design Compiler: Example .synopsys_dc.setup file
Xilinx Answer #515 : SYNOPSYS FPGA COMPILER: Problems reading an XNF file back into Synopsys.
Xilinx Answer #488 : SYNOPSYS: How to instantiate BSCAN in the 4k/5k in Verilog/VHDL in Synopsys (FPGA Compiler, Design Compiler, FPGA Express)
Xilinx Answer #453 : SYN2XNF: Use of -s option causes creation of EXT records, XNFPREP Error 3527
Xilinx Answer #445 : SYN2XNF pre-3.5.0: About 'ERROR 220: Can't open file 'vcc_.xnf'.'
Xilinx Answer #438 : SYNOPSYS: XNFPREP issues ERROR 3673 due to multiple clock buffers inserted.
Xilinx Answer #433 : FPGA COMPILER 3.1a and XSI 3.01: About 'cannot read library version'
Xilinx Answer #427 : SYNOPSYS FPGA COMPILER: To prevent Timespecs from apprearing in the XNF file.
Xilinx Answer #358 : SYN2XNF 3.4 / XACT 5.0: about XNFMERGE error 221 (processing hard macros)
Xilinx Answer #226 : VHDL: Implementing the XC3000/XC4000 readback function.
Xilinx Answer #220 : Obsolete: SYNOPSYS 3.1a: XBLOX synthetic library for needs to be re-analyzed.
Xilinx Answer #206 : Obsolete: Synopsys Design Compiler: report_timing asks for Design Time, technology license.
Xilinx Answer #174 : SYNOPSYS/XSI: Using an Input Latch (ILD_1) with No Delay