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Xilinx Answer #7820 : FPGA Configuration: What is the maximum time PROG can be held low to delay configuration?
Xilinx Answer #7193 : Foundation Schematic - Macro created with incorrect pins from VHDL code
Xilinx Answer #7015 : Foundation 1.5is2 - error : cannot find pcmdos.pif make sure this file exists...
Xilinx Answer #6987 : Foundation Express: Virtex unified library macros/primitives not recognized in HDL flow
Xilinx Answer #6926 : Foundation 1.5isp2 Simulator: What is the difference between .des (simulation) and .tve (waveform) files?
Xilinx Answer #6718 : A1.5/F1.5 RAM16X1D Dual port RAM: Doing a read on the dpra port reads an 'X' when the clock not defined, even though this is an async read RAM
Xilinx Answer #6679 : F1.5i Simulator: Driving a bus in CC Mode get overwritten
Xilinx Answer #6673 : Foundation Project Manager - How to add command line options to Templates for Implementing programs
Xilinx Answer #6650 : F1.5iS2 Sim: Warning 9204: Cannot find corresponding block pin for terminal Q15.
Xilinx Answer #6592 : F1.5i Foundation:Btrieve incompatibilty with Macola 7.5
Xilinx Answer #6569 : Foundation Schematic 1.5is2- Conv: Netlist [objectname].alb(0):seek 0x##, invalid char 0x0
Xilinx Answer #6401 : Simulator M1.5is2 : CLKDLL fails to function properly using offchip synchronization
Xilinx Answer #6395 : Project manager: lists bg352 package for 95288xl when only a bg256 exists
Xilinx Answer #6310 : F1.5i: XABEL: Syntax Error 1039: Identifier name <signal>.c is already defined, Syntax Error 1030, Syntax Error 1029...
Xilinx Answer #6268 : F1.5i and A1.5i install: invalid part or library not available for a part. How to install a part from the CD?
Xilinx Answer #6211 : F1.5is2 - macroed.exe Exception:access violation (0xc0000005), address 0x75b315af
Xilinx Answer #6126 : F1.5is2: The XC9572XL CS48 is missing from the part selector for the front-end tools
Xilinx Answer #6113 : F1.5i: Functional/Gate level Simulation on flatten EDN give 'Warning 9199: Unknown component - U1, sym_name.
Xilinx Answer #6091 : Foundation Schematic: Macro - Not updating when 'create netlist from current sheet'
Xilinx Answer #6028 : Foundation F1.5i Service Pack 2: How to add new CPLD/FPGA devices into the Foundation parts selector
Xilinx Answer #6026 : F1.5i Install:Installed devices are not written in fileset.txt for Base package install
Xilinx Answer #6014 : Foundation 1.5is1: Archive utility does not include underlying files....
Xilinx Answer #5975 : F1.5iS1 Simulation: Error opening file <name>.cmd in project manager's console
Xilinx Answer #5974 : Foundation schematic F1.5is1 - resets synthesis options when you push into a HDL macro
Xilinx Answer #5936 : Foundation F1.5i Service Pack 2 available via Web
Xilinx Answer #5703 : F1.5i Service Pack 1 Install: "Corrupt Cabinet File" when extracting fpgaexp.ico from express_31.exe
Xilinx Answer #5695 : f1.5isp1: When ABEL synthesis engine is run in NT 4.0 SP3, tkwdog process freezes computer (opening project, syntax check, synthesize, add to project)
Xilinx Answer #5691 : F1.5is1: Foundation Schematic Editor: Error Reading File/ Error Writing File/ Reading file [filename] failed/ Writing file [filename] failed.
Xilinx Answer #5677 : Project Manager M1: Project Manager (PCM) disappears when opening/invoking a project
Xilinx Answer #5670 : F1.5i Service Pack 1 Install: An error occurred during the move data process: -113
Xilinx Answer #5668 : F1.5i Service Pack 1 Install: An Error occurred during the move data process: -115
Xilinx Answer #5667 : F1.5i Service Pack Install: "Cannot Find Program Location" when installing Design Entry Tools Update
Xilinx Answer #5651 : Foundation Schematic: Do not use the Power Symbols (VCC, GND) from the Schematic Editor Toolbar
Xilinx Answer #5645 : Foundation F1.5/F1.5i: When trying to execute the Project Manager, nothing happens
Xilinx Answer #5597 : F1.5i, Project Manager: Project Manager buttons grayed out
Xilinx Answer #5472 : F1.5/F1.5i Project Manager: Automation failed, exit with error code 80080005
Xilinx Answer #5454 : F1.5/F1.5i Library Manager: When attaching a library to another project, unexpanded block errors occur in Implementation Tools
Xilinx Answer #5447 : F1.5/F1.5i Project Manager: Pcm: Cannot initialize automation: could not get interfaces to Synopsys server
Xilinx Answer #5443 : F1.5i: Virtex -6 speed grade not available in Project Manager.
Xilinx Answer #5420 : Alliance/Foundation 1.5i: Icons in start menu do not bring up the software. Can't find execuatble.
Xilinx Answer #5393 : F1.5/F1.5i: How do you access the extended message referred by Foundation HDL editor
Xilinx Answer #5392 : F1.5i Project Manager: Cannot create directory. Long Path Name problems.
Xilinx Answer #5378 : F1.5/F1.5i HDL Editor: Lines >116 characters truncated when printing
Xilinx Answer #5333 : F1.5,2.1i Security. Debugging a Floating License.
Xilinx Answer #5323 : F1.4/F1.5/F1.5i HDL editor : Cannot print more than 56 lines a page
Xilinx Answer #5319 : Foundation Installer overwrites license file on every install
Xilinx Answer #5308 : F1.5/F1.5i/F2.1i Foundation Express: Information about "Abort" errors (1709, 1704, 1564, 67, etc.)
Xilinx Answer #5305 : F1.5i install: Is it required to install F1.5 first?
Xilinx Answer #5303 : F1.5i watch tutorial wtut_vhd does not contain .hdr, .dir, .blk, ...; library directory access error
Xilinx Answer #5281 : F1.5/F1.5i Project Manager: Checking Implementation reports gives "Template Engine" error box.
Xilinx Answer #5237 : Simulator: How to simulate a ramp or counter on a bus
Xilinx Answer #5228 : Foundation Schematic Capture: Are references required to end with a digit?
Xilinx Answer #5225 : F1.5/F1.5i Schematic Editor, Virtex: Do not use BUFGIO library component
Xilinx Answer #5188 : General Setup Initialization Errors - General Protection Fault (GPF) or "illegal operation" dialog
Xilinx Answer #5144 : Metamor to Foundation Express 1.5 (Synopsys) VHDL Conversion Guide
Xilinx Answer #5124 : F1.5i Simulator, Virtex: Cannot simulate CLKDLL component in a Timing Simulation.
Xilinx Answer #5117 : F1.5i: Simul caused a General Protection Fault in module <unknown> when saving simulation state
Xilinx Answer #5112 : Foundation Schematic Editor: What do green net labels mean?
Xilinx Answer #5110 : Foundation F1.5: Lmacs:58 The compression buffer length is too short, btrieve
Xilinx Answer #5099 : F1.5, Xilinx Constraints Editor: How to use the Xilinx Constraints Editor with Foundation F1.5
Xilinx Answer #5093 : Foundation F1.5 Project Manager: Implementation Status not properly updated when a project is on a network drive
Xilinx Answer #5057 : Foundation F1.5, Timing Simulator: Metastable operation not accurately simulated
Xilinx Answer #5047 : F1.5 FOUNDATION Simulator: "Simul :MACRO: illegal macro format - line is too long"
Xilinx Answer #5045 : F1.5 Symbol Editor, XBLOX: Illegal bus format [0:0]
Xilinx Answer #5038 : Simulation function of State Editor does not work
Xilinx Answer #5019 : Foundation F1.5 State Editor: Incorrect ABEL code generation when you have two state machines (L109/C15)
Xilinx Answer #4934 : Foundation F1.5i, Virtex: Virtex schematic library update for F1.5i
Xilinx Answer #4925 : Implementation: part <part name> is either invalid or not supported
Xilinx Answer #4901 : A1.5/F1.5 - Synopsys design has multiple loads on net with some loads are not getting driven.
Xilinx Answer #4898 : F1.5, Schematic Editor: Issues involving complex buses; removal of Bus Pin Connection function
Xilinx Answer #4892 : Foundation Simulator: Cannot Find Free Formula Stimulator when running command (script) file
Xilinx Answer #4876 : Foundation 1.5 HDL Editor: Language Assistant for Verilog tri-state buffer is wrong.
Xilinx Answer #4871 : F1.5, State Editor: Synthesis -> Options to set encoding scheme has no effect
Xilinx Answer #4859 : F1.5, Active-VHDL3.2, synopsys: How to add packages to the Active-VHDL precompiled libraries.
Xilinx Answer #4824 : Foundation F1.5: Automation Caused an Exception; Exit Code 80010105
Xilinx Answer #4819 : Foundation Schematic Editor: Hotkeys for zooming in and out in Schematic Editor
Xilinx Answer #4818 : F1.5/F1.5i, Calc3ka: F1.5 calc3ka sample project has incorrect design flow type
Xilinx Answer #4816 : Foundation F1.5 Simulator: Page setup print options not being saved/used
Xilinx Answer #4814 : F1.5: SC caused a general protection fault in module conv_acs.all when importing Synplicity EDIF files
Xilinx Answer #4785 : F1.5, HDL Editor: Symbol is not created for a synthesized HDL macro
Xilinx Answer #4784 : Foundation F1.5: Simulation template forced to Foundation EDIF
Xilinx Answer #4776 : Foundation F1.5i: Incorrect speed grades listed for XC4000XLA, XC4000XV, SpartanXL and Virtex
Xilinx Answer #4769 : F1.x State Editor - How do you specify registered or combinatorial outputs?
Xilinx Answer #4767 : Foundation F1.5: Automation Caused an Exception; Exit Code 80010104, 800706ba
Xilinx Answer #4755 : Foundation F1.5: HDL source files must reside in Foundation project directory
Xilinx Answer #4731 : HDL Design Changes do not appear to get saved when upgrading from Foundation 6 to Foundation F1.x.
Xilinx Answer #4730 : Foundation1.5,Coregen,Logiblox,Checkpoint Simulation: How simulate an HDL or mixed design with Coregen or Logiblox?
Xilinx Answer #4727 : F1.5 Schematic Editor: Net attributes parameter names multiply with each installation
Xilinx Answer #4715 : Foundation F1.4, F1.5: Constraints in UCF appear to be ignored after copying project in Foundation
Xilinx Answer #4700 : Foundation F1.5: SC caused a GPF in module SC_LIBR.DLL when saving symbol
Xilinx Answer #4697 : F1.4, XVHDL: Assigning power mode to output signals in VHDL
Xilinx Answer #4663 : F1.5 Schematic Editor: Is it possible to cut and paste schematics into other applications?
Xilinx Answer #4653 : Foundation F1.5: Cannot show 'Create Version' dialog -- automation caused exception, exit code 80010105
Xilinx Answer #4643 : Foundation F1.5: CPLD update available on FTP site
Xilinx Answer #4622 : Foundation: Is there a workstation version of Foundation available?
Xilinx Answer #4599 : F1.5: State Editor generates incorrect one-hot encoded VHDL with a trap state exit logic
Xilinx Answer #4583 : F1.5, Install: How to add support for additional devices or families.
Xilinx Answer #4579 : F1.5, XABEL: Problem with functional simulation of ABEL designs following CPLD Quick Install.
Xilinx Answer #4578 : F1.5 Install: Uninstall of Docs uninstalls entire Foundation environment
Xilinx Answer #4557 : Foundation F1.5: Simulation of HDL tutorials (Stopwatch) requires manually toggling Global Reset
Xilinx Answer #4545 : Foundation F1.5: Important information about source and revision control in HDL projects
Xilinx Answer #4540 : Foundation F1.4 Symbol Editor: Symbol Editor caused general protection fault (GPF) in module SCLM_BIN.DLL
Xilinx Answer #4514 : F1.5 Answers Book: Answers Book must be installed to be used (cannot run from CD)
Xilinx Answer #4502 : Foundation F1.5: Where can I find a list of Foundation file types' extensions?
Xilinx Answer #4501 : Foundation F1.5: HDL macro compilation uses 4000e part when checking syntax
Xilinx Answer #4480 : F1.5 Schematic Capture: How to create a macro from a netlist
Xilinx Answer #4473 : Foundation F1.4 Simulator, Coregen1.4: Simulator gives Page Fault with large bus Sine/Cosine core.
Xilinx Answer #4468 : F1.5, XVHDL: Using Metamor (XVHDL) with Foundation F1.5
Xilinx Answer #4467 : Foundation F1.5: When opening F1.4-type HDL projects in F1.5, device and Simprims libraries not shown
Xilinx Answer #4456 : Foundation Schematic Editor Help v1.4: Importing Netlist help refers to invalid menu pick
Xilinx Answer #4440 : F1.5, JTAG Programmer: JTAG Programmer for FPGAs must be invoked stand-alone
Xilinx Answer #4434 : Foundation, Spartan: Why can MD1 be placed in schematic, but causes error in implementation?
Xilinx Answer #4431 : Foundation Simulator: How to copy waveforms as bitmaps to other applications like MS Word
Xilinx Answer #4430 : Foundation F1.4 Simulator: Error 9523: Incorrect EDIF file. Cannot find top level netlist data.
Xilinx Answer #4402 : Foundation F1.5, State Editor: After migrating design from F1.4 to F1.5, incorrect VHDL libraries used
Xilinx Answer #4401 : Foundation F1.5: Standalone Design Manager doesn't show current project status
Xilinx Answer #4399 : Foundation F1.5: Default Simulation Template set to "Generic EDIF"
Xilinx Answer #4398 : Foundation F1.5 Simulator, Virtex: Virtex simulation with Foundation Simulator not fully operational.
Xilinx Answer #4396 : F1.4/1.5: Modifying libraries when moving from Metamor (XVHDL) to Express
Xilinx Answer #4391 : F1.5: Virtex Configuration Stage - Project Manager reports Implementation Errors
Xilinx Answer #4388 : F1.4 Schematic Capture: Valid characters for signal and instance names
Xilinx Answer #4372 : Foundation F1.5: How to run Multi-Pass P&R and how to use Guide files with F1.5
Xilinx Answer #4368 : F1.5: Project Manager appears to hang when invoking Implementation
Xilinx Answer #4366 : Foundation Express F1.5: Migrating Express projects from 1.4 to 1.5
Xilinx Answer #4365 : Foundation F1.5, HDL Editor: Can't synthesize top-level VHDL or Verilog file from HDL Editor
Xilinx Answer #4363 : Foundation F1.5: Upgrading/migrating a pre-F1.5 project to F1.5
Xilinx Answer #4360 : F1.4 Project Manager: On starting Foundation, the mesage "cannot find c:\fndtn\bin\nt\command.com" appears.
Xilinx Answer #4359 : F1.4 Project Manager: Netlist creation failed. Try exporting netlist to edif in schematic editor.
Xilinx Answer #4355 : Foundation F1.5: "Cannot copy Xilinx project with different name" when copying Foundation project
Xilinx Answer #4354 : Foundation F1.5, ABEL: Can't synthesize or add ABEL file to HDL project
Xilinx Answer #4353 : Foundation F1.5, ABEL: Use" Schematic" Project Flow for top-level ABEL designs
Xilinx Answer #4350 : Foundation F1.5, Project Manager: Automation Caused an Exception; Exit Code 0.
Xilinx Answer #4349 : Foundation F1.5: Windows NT Service Pack 3 required. (Automation caused exception, exit code 0)
Xilinx Answer #4347 : Foundation F1.5 Simulation, Coregen: Must create Foundation Schematic Symbol in Coregen to Functionally Simulate
Xilinx Answer #4344 : Foundation F1.5 Project Manager: Green checkmark for Implementation requires BIT file be present
Xilinx Answer #4300 : F1.4,F1.5 Simulator: Possible System Oscillations; please wait or press stop button.
Xilinx Answer #4292 : Foundation F2.1i, F1.5i: Adding Schematics to HDL Flow Projects
Xilinx Answer #4283 : F1.4 Simulator: Simulating FPGA Express Netlist returns Warning 9218: unknown pin name
Xilinx Answer #4267 : F1.5 Project Archive: Archive may take a few minutes to begin on Windows NT
Xilinx Answer #4263 : F1.4, F1.5 Schematic: Hierarchy Descent in Annotation is disabled
Xilinx Answer #4261 : F1.4, F1.5: Preference changes are carried over to other projects as well
Xilinx Answer #4257 : Foundation F1.4: 5200 design with xact give xnfprep error 3701: INIT parameter not supported
Xilinx Answer #4233 : F1.4 Simulator: Deletes Formulae when "Simulate Single Component" option is selected
Xilinx Answer #4216 : F1.4, F1.5 Timing Simulation: Preserving Hierarchy for Foundation timing simulation
Xilinx Answer #4198 : F1.4 State Editor: Copying and pasting detaches the condition/action text
Xilinx Answer #4187 : Foundation Schematic Editor: LMACS: The chunk offset is too big
Xilinx Answer #4127 : F1.4, F1.5 State Editor: Referencing the same state multiple times by name
Xilinx Answer #4092 : F1.4, F1.5 Simulation: How to create an LED (7 seg) drawing on the schematic that lights during simulation.
Xilinx Answer #4063 : F1.4 Schematic: "Create schematic from netlist" loses INV from symbols in XNF file
Xilinx Answer #4062 : F1.4, F1.5 Simulator: Not all signals are listed in Component Selection window; how to show all signals
Xilinx Answer #4046 : Foundation Schematic Editor: Does Schematic Editor have multiple Undo capability?
Xilinx Answer #4016 : F1.4: How to add parameters to Foundation Symbols Parameters list
Xilinx Answer #3996 : Foundation F1.4 LogiBLOX: Invoking LogiBLOX through Foundation F1.4 for 4000XL designs uses 4000EX family.
Xilinx Answer #3959 : Foundation 1.4: Logiblox will not open from Schematic Editor or Project Manager
Xilinx Answer #3955 : F1.4, Simulator: Probes from schematic macro don't appear in Simulator.
Xilinx Answer #3953 : Foundation XVHDL: mmvhdl.exe not found when synthesizing
Xilinx Answer #3946 : Foundation F1.4 Schematic Editor: 'Print all macros' command does not print correctly
Xilinx Answer #3938 : F1.4, F1.5, Timing Simulator: '-' in signal names converted to '_'
Xilinx Answer #3932 : Foundation F1.4 Simulator: Explanations of Functional and Timing modes in Simulator
Xilinx Answer #3931 : F1.4,docs,base,device_support: Incorrect list of supported devices in F1.4 Release Document
Xilinx Answer #3928 : Foundation F1.4 XVHDL: Using JTAG pins (TDI, TDO, TCK, TMS) for general I/O
Xilinx Answer #3923 : Aldec Active-VHDL: Key inactivates Foundation install (puts into evaluation mode)
Xilinx Answer #3912 : F1.4, F1.5 Project Manager: After unarchiving (restoring) project, design changes are not reflected in the implementation.
Xilinx Answer #3897 : Foundation F1.4, XC95144-20: XC95144-20 device is available from Design Entry but not Implementation
Xilinx Answer #3895 : Foundation F1.4, Translate: Where does the &__A__ net name in my warning come from?
Xilinx Answer #3874 : Foundation Schematic F1.4 : Options->Replace Symbol replaces all instances of symbol
Xilinx Answer #3860 : Foundation Simulator: How to fit more simulation time in one page when printing it.
Xilinx Answer #3833 : F1.4 Schematic: How to import and edit a macro without affecting the original source file
Xilinx Answer #3818 : F1.4 General - Chinese, Korean and Japanese encodings corrupted by US Foundation Design Entry CD
Xilinx Answer #3793 : Foundation 1.4: Timing violation message in foundation timing simulation for 9500
Xilinx Answer #3782 : Foundation F1.4: Moving pin on a logiblox symbol in Symbol Editor does not update symbol.
Xilinx Answer #3756 : FSM Editor F1.4: Vhdl code synthesis errors, Enum_encoding not declared
Xilinx Answer #3721 : Foundation F1.4: Symbol references conflict assigned to same symbol
Xilinx Answer #3717 : How to import Synplify's XNF netlist into the Foundation schematic?
Xilinx Answer #3716 : Foundation F1.4 Project Manager: Restore Project returns a blank window under Win95
Xilinx Answer #3711 : Foundation F1.3/F1.4: Cannot select 4000EX/4000XL, Spartan devices when creating new project
Xilinx Answer #3682 : Foundation F1.4: Error when opening: "pcm:file timecore.cpp, line 58"
Xilinx Answer #3678 : Foundation F1.4: Project Manager slow to open in Windows NT
Xilinx Answer #3649 : Foundation F1.4: Incorrect pin name in symbol editor
Xilinx Answer #3641 : A1.4, F1.4, MTI: VHDL Timing Simulation produces "Error: a positive value of WIDTH must be specified"
Xilinx Answer #3606 : Foundation F1.4: PDF versions of Quickstart Guide, Express User Guide, Release Notes (docs)
Xilinx Answer #3604 : HDL Editor: Saving file opens Real Player
Xilinx Answer #3599 : Foundation F1.x HDL Editor: Bus pins not created for ABEL macros
Xilinx Answer #3590 : Foundation XVHDL, CPLD: How to set global signals (tristate, set/reset, clock)
Xilinx Answer #3580 : Foundation F1.5: Is it year 2000 compliant?
Xilinx Answer #3568 : Foundation Simulator F1.4: Keyboard toggle may not work
Xilinx Answer #3560 : Foundation F1.4: Xilinx Online Books (Dynatext) not installed by default
Xilinx Answer #3540 : Foundation Simulator, Logiblox, F1.4: Async_Val not simulated at power-up or GSR.
Xilinx Answer #3535 : Foundation Logic Simulator: WARNING: More than one normal (Totem_Pole) output in the folloing node...
Xilinx Answer #3531 : Foundation F1.4 Install: Not all 4000XL devices installed by default
Xilinx Answer #3497 : F1.x State Machine Editor: Syntax Error 1031: Undefined identifier name 'SREG0'
Xilinx Answer #3465 : Foundation Schematic Editor F1.x: How to print all black schematics (instead of grey scale).
Xilinx Answer #3454 : Foundation F1.3/F1.4, XVHDL, Synthesis, grayed, Error: Hde: Foundation option in xilinx, Keylock not found. (Sentinel driver)
Xilinx Answer #3409 : Foundation Simulator: End of time error
Xilinx Answer #3395 : Foundation F1.x: LMACS, Btrieve and Library Access errors
Xilinx Answer #3365 : Foundation F1.3/F1.4 XVHDL: How to use the numeric_std package
Xilinx Answer #3364 : Foundation BASE package: Dynatext browser not installed by default
Xilinx Answer #3339 : Foundation XVHDL: Instantiating OSC52 in a 5200 design
Xilinx Answer #3330 : Foundation F1.3, FPGA Express: Functionality incorrect for Express modules on Schematics
Xilinx Answer #3313 : XVHDL F1.3: XVHDL caused an invalid page fault in module XVHDL.EXE
Xilinx Answer #3299 : F1.3: SIMUL caused a general protection fault, will shut down.
Xilinx Answer #3292 : Foundation PCM reports JEDEC-to-ABEL conversion failed after normal completion
Xilinx Answer #3279 : Foundation F1.4 Simulator, XC5200: Outputs are undefined in Timing Simulation
Xilinx Answer #3234 : Foundation XVHDL: Using mode pins (MD0, MD1, MD2) for general I/O
Xilinx Answer #3231 : Foundation F1.4: Uninstall program will preserve user projects, but remove sample projects
Xilinx Answer #3228 : Foundation F1.x State Editor: Logical Error 1002: Source line length exceeds 150 character
Xilinx Answer #3227 : Foundation F1.x: Project cannot have same name as macro (circular reference)
Xilinx Answer #3225 : Foundation F1.4 Schematic Editor: Library symbol SR8RLED is different size in 3k library
Xilinx Answer #3223 : Foundation F1.4 Simulator: Last line ignored inside a command/script file
Xilinx Answer #3221 : Foundation F1.4 Project Manager: Netlist creation error if path has a dot (.) character
Xilinx Answer #3219 : Foundation F1.4 Simulator, XC3000: Outputs are undefined in Timing Simulation
Xilinx Answer #3206 : Foundation F1.4 Project Manager: "Update HDL Macros" option in Project Manager Document menu not found
Xilinx Answer #3205 : Foundation F1.4, F1.5. Logic simulator: Bus ordering reversed after bus has been flattened, then combined
Xilinx Answer #3202 : Foundation F1.4: Foundation Library format issues
Xilinx Answer #3197 : M1 Logiblox: Error - Bus Conflicts during Foundation simulation
Xilinx Answer #3187 : Foundation F1.3 XABEL: Heavily constrained designs may cause fitter to core dump
Xilinx Answer #3186 : Foundation F1.3 XABEL: BLIF2OPT hangs or gives virtual memory overflow error
Xilinx Answer #3176 : Foundation F1.3, 3K/5K Early Access Libraries
Xilinx Answer #3175 : Foundation F1.3, Logic Simulator: Simulator will hang if status line has been deselected
Xilinx Answer #3174 : Foundation F1.3, XVHDL 3.0.2/3.0.3: Using a dedicated input pad for an instantiated global buffer (bufg)
Xilinx Answer #3161 : Foundation F1.x Simulator: How much memory does a simulation require?
Xilinx Answer #3152 : XABEL, Foundation F1.x: ref_2_inst: dangling port (message during synthesis)
Xilinx Answer #3151 : Foundation State Editor F1.x, XABEL: One-hot state machine is created "Cold"
Xilinx Answer #3150 : Foundation F1.3 State Editor, XABEL: Error APP_95 "<file>.edf does not exist" when creating macro
Xilinx Answer #3138 : Foundation F1.x Logic Simulator: ASCII test vector, cannot use u or p option for timing
Xilinx Answer #3124 : Foundation F1.x Simulator: Selective preset feature may disrupt the operation of counters, state machines
Xilinx Answer #3120 : Foundation Simulation seems to hang, or takes a long time before showing the waveform
Xilinx Answer #3100 : Foundation Project Manager, WinNT: "lmacs: ...unable to access transaction control file" in WINNT
Xilinx Answer #3092 : Foundation F1.3 State Editor: when selecting HOLD for Unsatisfied Conditions, selection not kept.
Xilinx Answer #3091 : Foundation F1.x, Timing Simulator: Same bus name with different indices gives 'X' outputs
Xilinx Answer #3076 : Foundation F1.3/F1.4, XC9500, XVHDL: Macro pass-through signals trimmed away or tied to VCC/GND.
Xilinx Answer #3073 : Foundation F1.x/F2.x, XABEL: Error: Could not find the file xxx.jhd, xxx.bl0
Xilinx Answer #3048 : Foundation F1.x, Design Manager, XABEL: DM doesn't read PLD (Plusasm) or EDN file if flow is changed
Xilinx Answer #3043 : Foundation F1.3, Logiblox: TNM attributes on Logiblox in schematic do not pass to EDIF file
Xilinx Answer #3041 : Foundation F1.3, F1.4: How to add Generic Project Type for Board Level Simulation
Xilinx Answer #3034 : Foundation Simulator: How to print a specific range of the simulation waveform
Xilinx Answer #3030 : Foundation XVHDL, XC9500: How to set an output to high impedance (Hi-Z)
Xilinx Answer #3023 : Foundation State Editor: How to modify encoding scheme for State Machines (ie, one-hot)?
Xilinx Answer #3002 : Foundation F1.x Project Manager: Very slow when launching under Win95
Xilinx Answer #3001 : Foundation F1.3, XVHDL: XVHDL (Metamor) v3.0.3 Upgrade available on Web Answers page
Xilinx Answer #2989 : Foundation F1.3, XVHDL 3.0.2: Error L20/CO: The Xilinx 4ke library does not contain a latch (#480 Constraint)
Xilinx Answer #2984 : **Obsolete**Foundation F1.3, XC5200: Incorrect polarity of pins in AND2B1, etc components
Xilinx Answer #2962 : Foundation F1.3/F1.4 XVHDL: Using Input/Output latches
Xilinx Answer #2959 : Foundation Project Manager: Hierarchical, Error xr57 - Input signal drives more than one input buffer.
Xilinx Answer #2958 : Foundation F1.x, XABEL: DIOEDA errors involving abl2edif
Xilinx Answer #2954 : Foundation F1.3/F1.4 XVHDL : I/O flip-flops (IFDX1) instantiation
Xilinx Answer #2951 : XABEL/Foundation F1.3/Alliance: Using F1.3's XABEL with Alliance packages (mentor, viewlogic)
Xilinx Answer #2895 : Foundation F1.x Schematic: How to lock down I/O pins for IPAD4/8/16, OPAD4/8/16, IOPAD/4/8/16
Xilinx Answer #2890 : Foundation F1.x Schematic: Symbols are removed or disappear after adding symbols. PM message symbol not added, not enough memory to complete this operation
Xilinx Answer #2873 : Foundation/Viewlogic simulator does not properly simulate the CK_DIV or OSC52 symbols Error 8030 or 8031
Xilinx Answer #2807 : Foundation F1.3: Lmacs: the record has a key field containing a duplicate key value -- Sc: LM_Put_Symbol - error #5
Xilinx Answer #2806 : Foundation F1.3: Lmacs cannot find <project_name>.id file -- SC: LM_Put_Symbol - error #702
Xilinx Answer #2759 : Foundation F1.x, Logiblox: Invalid Vendor 'fndtn' on command line. Unable to continue execution
Xilinx Answer #2756 : Foundation XVHDL: How to keep internal signal name so it appears in simulator
Xilinx Answer #2747 : Foundation Schematic: Can I add my own company logo to a Foundation schematic onto the border or table?
Xilinx Answer #2746 : Foundation XVHDL: Synthesis error "Wrong number of fields bus on line #__ in .xas file"
Xilinx Answer #2737 : Foundation F1.3/F1.4, XVHDL: How to simulate VHDL designs with instantiated XNF files
Xilinx Answer #2722 : Foundation F1.3/F1.4, XVHDL: I/O flip-flops not inferred by VHDL synthesizer
Xilinx Answer #2621 : Foundation State Editor: E:#002 Syntax error near "<="
Xilinx Answer #2620 : Foundation Simulator: How can I use a Formula to assign Z to a bus?
Xilinx Answer #2606 : Foundation XVHDL F1.3/F1.4: VHDL compiler synthesizes design twice
Xilinx Answer #2603 : F1.x Logiblox: Do not change Logiblox symbol parameters on Foundation schematic
Xilinx Answer #2602 : Foundation F1.x: Bus pin names are not visible on Logiblox components
Xilinx Answer #2600 : Foundation: Where to find old Foundation 6.x libraries
Xilinx Answer #2599 : Foundation: How to use both XACT6-based and M1-based flows with Foundation
Xilinx Answer #2596 : Foundation XVHDL, F1.3/F1.4: Hardware key required for XVHDL feature (Programmable C Key)
Xilinx Answer #2595 : Foundation XVHDL, F1.3/F1.4: How to instantiate Logiblox components
Xilinx Answer #2594 : Foundation XVHDL, F1.3/F1.4: Do not use 'Macrocell' attribute when instantiating Logiblox
Xilinx Answer #2591 : Foundation XVHDL, F1.3/F1.4: Bidirectional pins must be described in top-level entity
Xilinx Answer #2574 : Foundation XVHDL: How to use READBACK in a VHDL design
Xilinx Answer #2537 : Foundation: Can not load/open Foundation after renaming drive, susie.ini
Xilinx Answer #2509 : Foundation XVHDL: Cannot instantiate the XBlox TRISTATE component without pullups.
Xilinx Answer #2484 : Foundaton Simulator: 'assign' in command file gives incorrect state value.
Xilinx Answer #2426 : Foundation Simulator: high impedence on output of OSC4
Xilinx Answer #2390 : Foundation: Btrieve 12 : Lmacs, cannot find the specified file (*.HDR)
Xilinx Answer #2161 : Foundation Project Manager: How to copy a user created macro from one project to another?
Xilinx Answer #2152 : Foundation: BTRIEVE error 88 - incompatible mode error
Xilinx Answer #2140 : Foundation: Difference between I/O Pads and I/O Terminals
Xilinx Answer #2110 : Foundation HDL Editor: ABEL state diagram template gives grounded outputs.
Xilinx Answer #2097 : **Obsolete**Foundation Simulator: Greek fonts appear in the Waveform Editor
Xilinx Answer #2081 : **Obsolete**Foundation Schematic: How to replace a symbol without deleting nets
Xilinx Answer #2010 : Foundation XVHDL: message "No entity bound to this instance"
Xilinx Answer #1986 : Foundation: After copying a project, some files are missing
Xilinx Answer #1978 : Foundation XABEL: "XABEL is not installed" error when synthesizing ABEL code
Xilinx Answer #1952 : **Obsolete**Foundation: Service Pack Install - Setup will not run
Xilinx Answer #1950 : Foundation: "File specified in $FILE parameter is missing" when pushing into macro
Xilinx Answer #1938 : Foundation Schematic: Adding Attributes - LOC, X, etc.
Xilinx Answer #1934 : Foundation Simulator: Can I prevent my design from being flattened for functional simulation?
Xilinx Answer #1905 : Foundation HDL Editor: Code isn't highlighted with different colors properly.
Xilinx Answer #1903 : **Obsolete**Foundation Simulator: Unknown outputs on XBLOX or VHDL design
Xilinx Answer #1840 : Foundation XVHDL: Setting NODELAY property on inputs
Xilinx Answer #1839 : Foundation XVHDL: How to use Wide-Edge Decoders
Xilinx Answer #1838 : Foundation: Netlist Conversion Error Missing pin <pin> of <symbol> or library error
Xilinx Answer #1835 : Foundation: After unzipping archived project, errors updating xnf netlist
Xilinx Answer #1798 : Foundation Simulator: Where are custom Formulas stored?
Xilinx Answer #1792 : Foundation Schematic: How to control output slew rate
Xilinx Answer #1706 : XABEL: How to get test vectors (.TMV file) into an XC9500 JEDEC file
Xilinx Answer #1693 : Foundation HDL Editor: Performing a text search causes PC to lock up.
Xilinx Answer #1689 : Foundation XVHDL: missing TNM attribute will cause XNFPREP Error 7845
Xilinx Answer #1657 : Foundation: How to use a library macro as a template for a user-defined macro
Xilinx Answer #1626 : Foundation Simulator: Unknown outputs on 3K VHDL/ABEL/schematic design
Xilinx Answer #1623 : Foundation Simulator: How to assign a value to a bus using Formulas
Xilinx Answer #1620 : Esperan VHDL tutorial: Where are the example VHDL labs/files?
Xilinx Answer #1619 : Esperan VHDL Tutorial: Who to contact for more information.
Xilinx Answer #1601 : Foundation: Importing OrCAD Schematics to Foundation
Xilinx Answer #1586 : Foundation: How to generate a schematic from an XNF file
Xilinx Answer #1583 : Foundation Schematic: Viewlogic Import error - cannot connect wire to symbol
Xilinx Answer #1556 : Foundation XVHDL: how to use the OSC4 oscillator
Xilinx Answer #1549 : Foundation: Selecting Using Help gives "not enough memory"
Xilinx Answer #1547 : Foundation: Trying to open Project Manager exits Windows
Xilinx Answer #1545 : Foundation Schematic: How to quickly locate nets in a schematic
Xilinx Answer #1542 : Foundation Install: shadow caused segment load failure lm_acs.dll
Xilinx Answer #1525 : Foundation Install: Hangs or give Fatal Exception while "Attaching Libraries"
Xilinx Answer #1518 : Foundation Schematic: Changing table (title block) information or date on schematics
Xilinx Answer #1509 : Foundation XVHDL: Win32s Error, Unhandled Exception Detected
Xilinx Answer #1507 : Foundation: Adding parts and speed grades to the selection menus
Xilinx Answer #1502 : Foundation: BTRIEVE error 11: specified file name is invalid.
Xilinx Answer #1501 : Foundation: Connecting a symbol bus pin to a bus of different width
Xilinx Answer #1498 : Foundation XVHDL: How to access a user-created VHDL library
Xilinx Answer #1487 : Foundation XVHDL: Using Timespecs
Xilinx Answer #1486 : Foundation XVHDL: Using CLB Latches
Xilinx Answer #1485 : Foundation XVHDL: Using RAM and ROM in XC4000 devices
Xilinx Answer #1484 : Foundation XVHDL: Using XBLOX
Xilinx Answer #1473 : Foundation XVHDL: How to control the # of BUFGs which are automatically inserted.
Xilinx Answer #1463 : Foundation: Importing Viewlogic designs with multi-page macros
Xilinx Answer #1396 : Foundation: Can you put LOCs on IPAD4/8/16 or OPAD4/8/16?
Xilinx Answer #1388 : XABEL/FOUNDATION: What is needed to compile a design containing XABEL blocks
Xilinx Answer #1382 : PPR/Foundation: Duplicate name errors when guiding designs entered in Foundation
Xilinx Answer #1377 : Foundation XVHDL: How to specify FAST Slew rate
Xilinx Answer #1376 : Foundation XVHDL: Using Global Set/Reset and STARTUP
Xilinx Answer #1375 : Foundation XVHDL: Using Global Buffers
Xilinx Answer #1374 : Foundation XVHDL: How to use Bidirectional I/O
Xilinx Answer #1373 : Foundation XVHDL: How to use I/O Flip-Flops
Xilinx Answer #1372 : Foundation XVHDL: How to lock down I/O pins
Xilinx Answer #1366 : Foundation XVHDL: Using pullups and pulldowns
Xilinx Answer #1362 : Foundation XVHDL, JTAG: How to instantiate the BSCAN symbol for Boundary Scan
Xilinx Answer #1355 : Foundation: Can't print schematics to network printer under Windows 95
Xilinx Answer #1346 : XNFMERGE: Warning Unrecognized Property 'HDL_SOURCE' on symbol 'sym_name'
Xilinx Answer #1342 : Foundation: XC4000 CD4CLE macro counts independent of clock enable
Xilinx Answer #1317 : F1.4, F1.5 Simulator: Saving simulation probes and I/O signals
Xilinx Answer #1304 : Foundation/XABEL: "Synthesis Failed" when synthesizing ABEL file.
Xilinx Answer #1291 : Foundation: Keylock (Sentinel driver) must be upgraded after an upgrade from Win3.1 to Win95
Xilinx Answer #1286 : Foundation Simulator: simulating bi-directional signals
Xilinx Answer #1256 : Foundation HDL Editor: "Unhandled Exception" during VHDL synthesis
Xilinx Answer #1241 : Foundation: How long can Net Names and Pin Names be?
Xilinx Answer #1236 : **Obsolete**Foundation: BTRIEVE 1002 or memory allocation error on XC4000E project
Xilinx Answer #1184 : **Obsolete**Foundation Timing simulation : BAX file <design> does not exist XACT6 Design Manager process ?
Xilinx Answer #1155 : Foundation: Pins on Abel symbol not matched to any signal in <abel_file>.xnf
Xilinx Answer #1132 : **Obsolete**Foundation Simulator: 'Invalid chip descriptor' error while loading netlist
Xilinx Answer #1118 : Foundation XVHDL: Synthesis of VHDL causes message: No entity selected.
Xilinx Answer #1068 : Foundation: Importing a Viewlogic design with a user library
Xilinx Answer #1063 : **Obsolete**Foundation: Key stops working on BAS and BSV packages
Xilinx Answer #1056 : Foundation: How to move a project around
Xilinx Answer #1045 : Foundation Simulator: XC7300/XC9500 flip-flop outputs unknown (PRLD signal)
Xilinx Answer #1034 : **Obsolete**Foundation: SC Symbols list is empty when adding a component in Schematic Capture
Xilinx Answer #1028 : Foundation HDL Editor: Compiling an ABEL file as a stand-alone CPLD design.
Xilinx Answer #1027 : Foundation Simulator: PRINT command described incorrectly in documentation
Xilinx Answer #994 : Foundation: Improper Netlist error while loading functional simulation
Xilinx Answer #986 : Foundation: How to delete a component from a user library
Xilinx Answer #984 : Foundation: VHDL entry option is not selectable
Xilinx Answer #980 : Foundation: BTRIEVE error messages reported in Project Manager message window
Xilinx Answer #954 : Foundation XVHDL, F6.x: Instantiating I/O buffers causes XNFPREP error 3530
Xilinx Answer #939 : Foundation Simulator: macro outputs always 'Z' during simulation
Xilinx Answer #912 : **Obsolete**Foundation HDL Editor: editor will not start
Xilinx Answer #910 : Foundation 6.x: is there Windows 95, Windows NT, OS/2 support?