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Xilinx Answer #8556 : Virtex Configuration: INIT goes low
Xilinx Answer #8552 : Modelsim (MTI) VHDL Coregen: Using a Generate Statment I can not get my simulation to run (Configuration)
Xilinx Answer #8520 : Virtex Configuration: What is an ABORT? How do I cause one?
Xilinx Answer #8518 : Parallel Cable: How is it possible to power the parallel cable with 3.3V and 5V without an adaptor?
Xilinx Answer #8514 : Virtex: Will Vref pin draw any power if the IO standard is CTT
Xilinx Answer #8508 : Virtex: How many DLLs can be cascaded together?
Xilinx Answer #8483 : Virtex: VHDL code for select link application
Xilinx Answer #8432 : Virtex-E: Can we tie Vcco to 2.5 V for LVDS, and have LVTTL inputs?
Xilinx Answer #8427 : JTAG Programmer - '<design_name>(Device1)': Programming terminated due to errors.
Xilinx Answer #8415 : Foundation State Editor/Abel: Syntax Error when //diagramm actions are used
Xilinx Answer #8383 : Virtex: Can Virtex Inputs be driven by input voltages lower that -500mV?
Xilinx Answer #8350 : JTAG BSDL - General Description of BSDL and how to read a BSDL file
Xilinx Answer #8342 : FPGA Configuration: Why doesn't the parallel cable have an INIT pin?
Xilinx Answer #8341 : Virtex-E datasheet: What are the pins for LVDS global clocks?
Xilinx Answer #8325 : Foundation Base Package: Synopsys Constraints editor license file not found, will load without it!
Xilinx Answer #8289 : Virtex Configuration: Device hasn't started configuration
Xilinx Answer #8265 : JTAG BSDL - What is the format of the IDCODE for Xilinx devices?
Xilinx Answer #8241 : FPGA Configuration : DONE pin is being held low externally
Xilinx Answer #8238 : FPGA Configuration : LengthCount match has not been met
Xilinx Answer #8225 : Is there a Utility which converts ABEL or AHDL designs to Verilog or VHDL format
Xilinx Answer #8219 : Virtex: Pin AD26 of FG676 package should be in Bank 4 for Virtex.
Xilinx Answer #8209 : JTAG BSDL: Missing pins in BSDL file for Virtex BG packages
Xilinx Answer #8198 : FPGA Configuration: Configuration memory is not full (Express Mode 4000XLA/XV/SpartanXL)
Xilinx Answer #8197 : FPGA Configuration: Configuration data is incorrect
Xilinx Answer #8196 : FPGA Configuration: Startup sequence has not yet completed
Xilinx Answer #8156 : Virtex: Are the internal Tristate outputs pullup, pulldown or high-Z?
Xilinx Answer #8123 : PROM XC18V00: How should I connect the CF# pin?
Xilinx Answer #8110 : Virtex Configuration: Using LOUT writes for debugging purposes in Serial Modes
Xilinx Answer #8098 : Cable - MultiLINX Cable Drive strength capabilities and specifications
Xilinx Answer #8097 : Cable - Support of software combinations, devices, readback, and other features
Xilinx Answer #8096 : Cable - Voltage Interface Capabilities of the MultiLINX, Parallel cable III, and XChecker cables
Xilinx Answer #8076 : Mentor: pld_men2edif gives: Error: An instance in a model references part $LCA/spartanxl/vcc/part interface vcc... General 18
Xilinx Answer #8075 : Mentor: Check Design gives Error: Out of date reference; Version 1 of symbol "gnd", or of symbol "vcc"
Xilinx Answer #8045 : Where can I find documentation on metastability issues for Xilinx devices?
Xilinx Answer #7963 : Virtex Configuration: Is it possible to abort readback of a device?
Xilinx Answer #7949 : FPGA Express 3.3: FPGA-buffermap-25 occurs when clock signal is connected to non-clock loads
Xilinx Answer #7844 : Virtex-E IBIS models -- Can Virtex IBIS models be used?
Xilinx Answer #7832 : PROM XC18V00: Pins not described in the datasheet are no connects
Xilinx Answer #7771 : Virtex Configuration: Virtex devices do not pass anything out on DOUT pin during configuration
Xilinx Answer #7770 : PROM XC18V00: How to program an 1800 series prom with the JTAG programmer
Xilinx Answer #7738 : Virtex-E JTAG - IO bank voltages in Virtex and Virtex-E JTAG pins act differently
Xilinx Answer #7732 : Virtex Configuration: Can devices be daisy-chained in SelectMAP mode?
Xilinx Answer #7727 : FPGA Express 3.3: Instantiated IFDX/IFDXI or OFDX/OFDXI get written to netlist as IFD or OFD
Xilinx Answer #7517 : 2.1i Documentation - How to read Docscan off the CD
Xilinx Answer #7473 : XC1800: The use of the CF# pin in SO20 and PC20 package is limited
Xilinx Answer #7472 : PROM XC18V00: What is the function of the CF# pin.
Xilinx Answer #7436 : LogiCORE PCI: XPCI Core Generator Server transaction failed. Failure cause: 1097
Xilinx Answer #7426 : Virtex: Configuration -- DONE goes high, but IO never goes active
Xilinx Answer #7417 : Foundation 2.1: LMACS Errors when attempting to open a new project
Xilinx Answer #7413 : LogiCORE PCI: The PCI master may stop bursting data after 2 clocks during simulation
Xilinx Answer #7406 : Foundation 2.1: Unexpected error when installing 2.1
Xilinx Answer #7379 : EXEMPLAR 1999.1x: How do I set a slow slew rate when 'Fast Output Buffers' is selected?
Xilinx Answer #7348 : 2.1i ChipViewer - Long invocation time of ChipViewer causes confusion to the users.
Xilinx Answer #7313 : Cable - Is it possible to use an extension on the Xilinx cables?
Xilinx Answer #7270 : JTAG - Mixed voltage JTAG chain considerations among E, XL, XV or 5V, 3.3V, 2.5V devices
Xilinx Answer #7262 : FPGA Express: Is there an option to disable carry logic?
Xilinx Answer #7242 : FPGA Express inserts ILD for ILDX_1 instantiation
Xilinx Answer #7197 : Timespec constraints: UCF/NCF PERIOD constraints are not written correctly in the PCF file
Xilinx Answer #7176 : LogiCORE PCI: Base Address Registers (BAR's) and configuration accesses in a PCI system
Xilinx Answer #7158 : FPGA Express: VHDL Error: Range 'U' to 'X' (or 'Z' to '-') not covered by choices. (VSS-838)
Xilinx Answer #7140 : FPGA Express 3.3: How to infer ROM for Virtex
Xilinx Answer #7108 : LogiCORE PCI Virtex (v3.x): Are the Virtex Devices PCI compliant?
Xilinx Answer #7066 : ngdbuil: basts:167 could not find clk net ... referred to by timegroup
Xilinx Answer #7051 : FlexLM/Security - floating license for Computer names with spaces in them will not work,"Not a valid server host name"
Xilinx Answer #7040 : COREGEN: How to cascade the Serial and Parallel ROM-based Correlators
Xilinx Answer #6985 : Foundation Simulator: Schematic - Problem when a hierarchy tap drives logic internal of a macro
Xilinx Answer #6977 : Virtex: Why is there no option to TIE unused interconnect?
Xilinx Answer #6873 : Libraries Guide: CB2CLED, CB4CLED, CB8CLED, CB16CLED truth table is incorrect for TC and CEO outputs
Xilinx Answer #6859 : PROM XC18V00: How to select between SelectMAP, Express, and Serial Modes of configuration
Xilinx Answer #6858 : PROM XC18V00: What is the Security option and how is it selected?
Xilinx Answer #6845 : PROM: XC18V00: What is the method used to program the 1800 PROM devices?
Xilinx Answer #6749 : Virtex Configuration: DONE does not go high, INIT does not go low
Xilinx Answer #6709 : FPGA Configuration: Done goes not high, STARTUP block used
Xilinx Answer #6698 : LogiCORE PCI: Why does the top level PCI wrapper instantiate the PCI core wrapper instead of the core itself?
Xilinx Answer #6676 : JTAG - How to instantiate the BSCAN symbol to use JTAG in xc4000 and Spartan devices using HDL?
Xilinx Answer #6664 : JTAG BSDL - Does Xilinx provide configured BSDL files for post configured parts?
Xilinx Answer #6639 : ChipViewer 2.1i: The input path is not shown when you click on a input pin in the ChipViewer
Xilinx Answer #6635 : JTAG BSDL - What are the Boundary Scan IDCODES for Virtex FPGAs?
Xilinx Answer #6579 : Workview Office: Who to contact for Workview Office license update? Required License file not found (Errror 8030)
Xilinx Answer #6548 : Hardware Debugger 2.1: Opening a design file with a long path name may cause page fault.
Xilinx Answer #6502 : LogiCORE PCI: What is the comply directory in the downloaded files?
Xilinx Answer #6422 : Setting up/install a printer for Xilinx workstation tools.
Xilinx Answer #6214 : Virtex IOFF: How to use the registers/FFS in the IOB?
Xilinx Answer #6172 : XABEL: Can't find file x.bl0; BLIF2EQN can only translate projects with 4 or fewer functional_block (hierarchy) statements
Xilinx Answer #6152 : PROMs: Migration Guide for XC1700 and XC1800 devices
Xilinx Answer #6102 : Programmers : What programmers can I use to configure my Xilinx PROM?
Xilinx Answer #6087 : Documentation: Product Prefix Definition (AL, AM, DO, DS, UO, US, etc)
Xilinx Answer #5967 : Foundation Express: Feature has expired (-10, 32) when starting the program
Xilinx Answer #5961 : LogiCORE PCI Synplicity flow: xcmap.c: Error: primitive view:PrimLib.z(prim) not handled yet
Xilinx Answer #5926 : LogiCORE PCI docs: Not clear on how to drive S_READY and S_TERM
Xilinx Answer #5865 : Virtex Configuration: Done goes High, but device does not startup
Xilinx Answer #5819 : Hardwire JTAG - Does Hardwire support JTAG?
Xilinx Answer #5770 : CPLD 9500XL: How much current can the I/O sink/source?
Xilinx Answer #5760 : LogiCORE PCI: Are we free to use any BAR desired for I/O or Memory space?
Xilinx Answer #5742 : Virtex: What is the minimum pulse width for the PROGRAM pin?
Xilinx Answer #5666 : Virtex Configuration: Configuring Multiple Virtex Devices in SelectMAP mode.
Xilinx Answer #5624 : know
Xilinx Answer #5501 : Cable - When powering a cable with 5 volts and using a 3.3 volt xl part, what voltage are the control signals?
Xilinx Answer #5500 : Spartan XL - How to estimate power in Spartan XL. What is the K factor ?
Xilinx Answer #5499 : JTAG - Configuring multiple devices in a JTAG chain, do you need to buffer the TMS and TCK?
Xilinx Answer #5474 : NC-VERILOG: Running simulation
Xilinx Answer #5451 : CPLD XC9500/XL: Where to find decoupling capacitors for 9500/XL chips?
Xilinx Answer #5444 : Libraries Guide contains typo error in Global Clock Buffer Location for Virtex
Xilinx Answer #5421 : Are virtex devices compatible with PC100 class SDRAM?
Xilinx Answer #5391 : JTAG - What is the JTAG CLAMP instruction?
Xilinx Answer #5204 : FPGA Express: Can I run more than one version of FPGA Express on my PC?
Xilinx Answer #5155 : FPGA Configuration: Configuration Problem Solver on web.
Xilinx Answer #5136 : Concept2xil: Programmer Error: Failed Assertion at line 710
Xilinx Answer #5073 : FPGA Express produces XNF with lines greater than 2048 characters, ERROR:basxn:53 - Line number 30788: maximum field length exceeded
Xilinx Answer #5024 : FPGA Configuration: DONE is High, device doesn't operate.
Xilinx Answer #5021 : JTAG - Is a bitsream generated for JTAG configuration the same as a bitsream for other configuration modes?
Xilinx Answer #4988 : FPGA Configuration: Mode Pin Setup for Express Mode in the XC4000XLA.
Xilinx Answer #4942 : kmode_exception_not_handled in file win32k.sys
Xilinx Answer #4931 : Windows NT Service Pack 4 may cause problems for Xilinx Software
Xilinx Answer #4881 : Accessing Xilinx FTP site using MS Internet Explorer
Xilinx Answer #4872 : VERILOG-XL: SDFA Error: Failed to find HOLD timingcheck.
Xilinx Answer #4855 : LogiCORE PCI: How does the PCI CORE handle wait states between data phases?
Xilinx Answer #4842 : VERILOG-XL: Warning! no matching timing check SETUP in Veritool for instance ... - skipping annotation
Xilinx Answer #4709 : Virtex JTAG - Dedicated JTAG Pins do not need external pullups.
Xilinx Answer #4672 : What is the composition of the BGA solder balls? What is their diameter?
Xilinx Answer #4661 : M1.5 Release Document Error: CAE libraries CD cannot be installed on the PC
Xilinx Answer #4627 : Program latency (Tpl) Time between Program going high and INIT going high
Xilinx Answer #4595 : Synopsys Design Compiler: How to specify the INIT attribute on instantiated ROM/RAM primitives
Xilinx Answer #4564 : LogiCORE PCI Virtex: What is the LPCILOGIC and RPCILOGIC?
Xilinx Answer #4483 : Foundation Express: How to instantiate OSC4 in HDL (XC4000E/EX/XL, Spartan/XL)
Xilinx Answer #4462 : Cable - Software package VS download cable (jtag, xchecker)
Xilinx Answer #4423 : JTAG - Testing support in Xilinx software & third party JTAG software suppliers
Xilinx Answer #4327 : JTAG - Can I configure FPGAs and CPLDs in a mixed JTAG chain?
Xilinx Answer #4307 : valid identifier in an edif file for xilinx
Xilinx Answer #4296 : Configuration: FPGA controlling their own reconfiguration
Xilinx Answer #4255 : HW-112: Which devices were supported on this Xilinx programmer?
Xilinx Answer #4204 : 4000ex/xl : Can bufge and bufclk be driven in parallel?
Xilinx Answer #4190 : FPGA Configuration: State of Dout pin before configuration.
Xilinx Answer #4168 : Spartan data sheet missing page 41
Xilinx Answer #4117 : Mentor, pld_edif2tim: error line 2 illegal identifier "15 encountered from synthesis
Xilinx Answer #4090 : ERROR:time_sim.vhd(132):Cannot assign to object with mode IN:ce. MTI timing simulation
Xilinx Answer #4086 : CONCEPT-HDL: Is Cadence's PE 13.x Concept-HDL supported?
Xilinx Answer #4066 : EZTAG help:Help file is not installed or not installed properly
Xilinx Answer #4043 : Foundation Schematic: Why does the Date in Table Setup always change when you use UNDO
Xilinx Answer #3957 : The readback bitstream in Dynatext is unclear.
Xilinx Answer #3935 : WEBLINX: Problems with Xilinx WebLINX or CoreLINX passwords, logging on, or registering on WebLINX
Xilinx Answer #3934 : FlexLM,security,network: How setup floating license on dummy ethernet card?
Xilinx Answer #3916 : Cable - What is the part number for Parallel cable III
Xilinx Answer #3892 : How to start the license manager automatically at boot time (Unix workstation)?
Xilinx Answer #3859 : M1.4 Flexlm license manager: Auto-start does not work on Win95 PC
Xilinx Answer #3856 : HW-130: 1701/17512 programming problem with the 4.30 version of the algorithm
Xilinx Answer #3851 : Foundation, Esperan VHDL Tutorial: Cannot be installed/used over a networked CD ROM drive
Xilinx Answer #3848 : Cannot Read 1998 Q1 Applinx CD on Workstations running Solaris. <file> not found
Xilinx Answer #3845 : BG-432 package pinout info error
Xilinx Answer #3712 : Foundation F1.4: Sentinal Driver Causes Conflict with Printer Driver
Xilinx Answer #3710 : M1.4:Setting Up Dynatext Browser or OnLine Books if not installed (PC)
Xilinx Answer #3699 : Flexlm, security, TCP/IP, modem, ISP: License server only works when ISP is connected to through a modem.
Xilinx Answer #3630 : Cable - Can I use the Parallel Cable III (JTAG Cable) to configure an FPGA?
Xilinx Answer #3581 : EZTAG 6.0.1: How to Program without Erasing from the command line.
Xilinx Answer #3575 : M1.4 : Dynatext gives Dynatext 3.0 Config Error 5055
Xilinx Answer #3487 : The HW-112 Programmer is also known as the PP1 (and PP2)
Xilinx Answer #3483 : floating license: While running M1.x dialup networking is evoked several times
Xilinx Answer #3445 : Floorplanner-XACT: Core dumps on HP-UX 10.xx
Xilinx Answer #3418 : Cable - Is there a schematic for the Parallel Cable III (JTAG Cable)?
Xilinx Answer #3406 : EZTAG: How to generate a .svf file?
Xilinx Answer #3362 : JTAG Programmer - Part is not an SPROM, usercode cannot be specified on the command line, will be ignored
Xilinx Answer #3359 : What kinds of information IBIS Models do and don't provide.
Xilinx Answer #3322 : CPLD: Can the 9500 output buffer drive the load of several 9500s?
Xilinx Answer #3321 : CPLD : XC9500/XL:Is there a reset or a done pin for CPLDs to determine if the device runs correctly?
Xilinx Answer #3272 : M1.4: How to set up LM_LICENSE_FILE when using Veribest and WorkView Office
Xilinx Answer #3194 : CPLD: XC9500/XL: What is the polarity for the tri-state enable for CPLDs?
Xilinx Answer #3181 : M1.3, Dynatext, Xilinx Books: After installing Dynatext, no books are available.
Xilinx Answer #3164 : Can not open books in dynatext
Xilinx Answer #3123 : CPLD XC9500/XL : How are initial states of flip-flops determined on the 9500 CPLD's?
Xilinx Answer #3114 : HardWire: Where to get speed files?
Xilinx Answer #3090 : FPGA Configuration: Run times for configuration rates and CPLD programming.
Xilinx Answer #3077 : XC4000XL/XLT: Differences between the 4000XL and 4000XLT
Xilinx Answer #3070 : Modifying path of the dynatext.ini file
Xilinx Answer #3051 : Translating lattice LDF file to Xilinx XABEL format
Xilinx Answer #3019 : What is Dr. Watson?
Xilinx Answer #2966 : XC2000/XC3000/XC4000/XC5200: Tying two output pins to enhance current drive
Xilinx Answer #2935 : Converting pre-Unified library schematic designs to Unified libraries
Xilinx Answer #2932 : What is an IBIS model, (as opposed to a SPICE model)?
Xilinx Answer #2839 : Dynatext: How to contact Dynatext technical support?
Xilinx Answer #2778 : XC3000/XC4000/XC5200: impedance IOBs pullups for different devices
Xilinx Answer #2772 : FATAL_ERROR:basnc:basncsignal.c:262:1.61 mapping with -k switch
Xilinx Answer #2765 : Considerations for choosing external PULLDOWN resistor values for FPGA pins.
Xilinx Answer #2739 : XCHECKER: What should the RST pin be connected to in XC4000 or XC5200 devices?
Xilinx Answer #2736 : Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc.
Xilinx Answer #2712 : How to analyze the resources a module or partially completed design consumes?
Xilinx Answer #2709 : DTEXT: Error in file Dynatext.ini. full.lic cannot be located
Xilinx Answer #2576 : Cable - Parallel Cable III and Xchecker Cable specs and dimensions for lead connectors and posts
Xilinx Answer #2552 : Eztag: Error 203 Syntax error in bit file
Xilinx Answer #2551 : PROMs: What are the SMD numbers for 1700d family.
Xilinx Answer #2526 : What are the differences between C,I, M and B products in a package?
Xilinx Answer #2505 : Mixed Voltage Systems: Interfacing 3.3 Volt and 5 Volt devices.
Xilinx Answer #2469 : 9500 EZtag download gives error 126: unsupported command
Xilinx Answer #2463 : Replacement for the 1700DDD8R (Obsolete) is the 1700DDD8B
Xilinx Answer #2461 : ** PROMs: Does makeprom have the s-records file format?
Xilinx Answer #2449 : Basic UCF Syntax Examples for Design Placement and Timing Constraints
Xilinx Answer #2428 : What is HMGEN?
Xilinx Answer #2386 : FPGA/CPLD: Do FPGA and CPLD inputs have Hysteresis?
Xilinx Answer #2343 : DATA I/O / Synario: SUPPORTS XC9500 family devices
Xilinx Answer #2200 : HDL Synthesis guide pp 1-8 & 1-9: Location of design files is wrong.
Xilinx Answer #2180 : Veribest: Technical Support
Xilinx Answer #2155 : Definition of a "gate", when defining number of logic gates in a FPGA
Xilinx Answer #2148 : Where to get the FPGA Demo Board Schematic?
Xilinx Answer #2147 : XACT_CPLD: Hitop - This program has performed an ilegal operation.....
Xilinx Answer #2138 : M1/XACT: How do I add comments to my constraints file?
Xilinx Answer #2130 : M1 Licensing: Using a workstation as a server for PC and workstation applications
Xilinx Answer #2077 : DATA I/O: "ERROR: Incompatible user data for device selected" when programming 9536 with a JEDEC file / Notes on JEDEC file format
Xilinx Answer #2058 : BP MICROSYSTEMS, 9572: 9572 support missing in current v3.23 algorithm
Xilinx Answer #2044 : PC Hangs: Some S3-based video card Drivers are incompatible with WIN32S
Xilinx Answer #2040 : Packaging: Test Clip Manufacturers
Xilinx Answer #2033 : 4000XL: Inputs are 5V compatible
Xilinx Answer #2027 : What does abreviation "BSC" mean in package dimensions
Xilinx Answer #2019 : XNF Specification: What is difference between T and B direction in an EXT record?
Xilinx Answer #2015 : Dynatext Browser: dtext quits with bus error when executed from Solaris CDE.
Xilinx Answer #2013 : Running lmgrd brings up network to be logged in
Xilinx Answer #2004 : ** XABEL-CPLD (DS-571-PC1):How to print the on-line help
Xilinx Answer #1999 : XC5200: What level are the I/O pins on an unprogrammed 5k device?
Xilinx Answer #1998 : XC5200: What is the value of the weak pull-up on an I/O?
Xilinx Answer #1987 : How to preserve/keep/save or prohibit software from using certain pins
Xilinx Answer #1974 : Protel support for Xilinx libraries?
Xilinx Answer #1969 : XNFPREP: ERROR 3525: Symbol 'U117' (type = INV, output signal = BCLOCk-) has an invalid pin 'O-'.
Xilinx Answer #1965 : Hardwire: Power consumption?
Xilinx Answer #1942 : XC4000XL: VTT connections on 4000XL pinouts...
Xilinx Answer #1941 : FPGA Configuration: For Peripheral configuration which is the MSB D7 or D0?
Xilinx Answer #1918 : 7336, PROMs: Using the 7336 as a virtual SPROM
Xilinx Answer #1897 : XC3000/XC3000/XC4000/XC5200: Logic cells and the FPGA Density Cross Reference Guide
Xilinx Answer #1894 : PPR 5.2.1: Execution on PC is slow on Windows 3.11?
Xilinx Answer #1890 : Moisture sensitivity level: Where to find this information??
Xilinx Answer #1872 : Clock Skew Not Accounted for in Path Analysis
Xilinx Answer #1870 : Logical Resources Are Not Listed in Timing Reports
Xilinx Answer #1869 : Long Runtimes for Some Designs
Xilinx Answer #1845 : Cable - Xchecker, Parallel, and JTAG Cables what do they do and how do I identify them?
Xilinx Answer #1841 : JTAG - Is the JTAG circuitry of the 4000EX identical to the XC4000 and XC4000E?
Xilinx Answer #1833 : UART design available as part of RS-232 interface application note
Xilinx Answer #1828 : HW-112 ALERT: 17256D and 17256 verification problems
Xilinx Answer #1800 : fpga compiler: Wire load not found "parttype-s_wc"
Xilinx Answer #1788 : 4000EX: Can I use a tri-state buffer (OBUFT) with the Output MUX (OMUX2)?
Xilinx Answer #1771 : FPGA Configuration: Can a 4000E or 5200 lead a 4000EX in a daisy chain?
Xilinx Answer #1769 : TNT.41400: INITEMULATOR:FLOATING POINT EMULATOR (EMUTNT.DLL) IS REQUIRED
Xilinx Answer #1759 : DC2NCF Requires libC.sl Library on the HP Platform
Xilinx Answer #1757 : FPGA Compiler: Pullup/Pulldown Resistors are Deleted From Synopsys Design
Xilinx Answer #1752 : Invoking the LogiBLOX GUI the First Time Could Take More Than 15 Seconds
Xilinx Answer #1751 : ViewDraw Symbols May Not Be Updated Properly After Entering a Change LogiBLOX Command
Xilinx Answer #1745 : ILDFFDX and ILDFLDX Library Components Have Been Renamed
Xilinx Answer #1744 : Parameterized Attributes in the Viewlogic Viewdraw Schematic Editor Are Not Supported by Xilinx Tools
Xilinx Answer #1738 : Control C Does Not Abort the Installation Procedure
Xilinx Answer #1736 : Kernel Limitations May Cause Out of Memory Problems on the HP Platform
Xilinx Answer #1723 : XC5200: Use of DI pin to a flipflop in a Logic Cell (LC)
Xilinx Answer #1719 : The 4025E does not have address pins A18:A21, these are on EX/XL devices only.
Xilinx Answer #1715 : TNM attached to net between PAD and IBUF/BUFG not forward traced
Xilinx Answer #1691 : EZTAG: Can FPGAs be mixed in with 9500 devices when using the JTAG cable?
Xilinx Answer #1687 : FPGA Configuration: Makebits- CRC checking does not exist for configuration in 2K and 3K devices
Xilinx Answer #1686 : Old part works on board, but the new Xilinx part does not! --Asynchronous design.
Xilinx Answer #1681 : How do I specify a bidirectional I/O in my schematic?
Xilinx Answer #1678 : IBIS Models are now availible on the Xilinx Anonymous FTP site
Xilinx Answer #1675 : XC5200/XC4000E/EX/XL/XV: How flip-flop initial states are determined for FPGAs.
Xilinx Answer #1672 : What is the purpose of DONEIN, Q1Q4, Q3, Q2 on STARTUP macro?
Xilinx Answer #1668 : Xilinx online documentation available on FTP site
Xilinx Answer #1664 : Design Manager 6.0.1: PPR - "Error XLM:KEY_NOT_FOUND" (LPT Conflict). Using Win 95.
Xilinx Answer #1661 : 4000 device bitstream compatibility
Xilinx Answer #1654 : XC5200: programmable weak keeper cells.
Xilinx Answer #1651 : Configuring device I/Os as an open-drain (open-collector)
Xilinx Answer #1634 : Printed Circuit Board (PCB) considerations of Xilinx devices
Xilinx Answer #1624 : JTAG - Do the XC4000 based families require a special bitstream for JTAG Config?
Xilinx Answer #1618 : XC5200: How to use Direct Connect routing resources?
Xilinx Answer #1616 : Xchecker Software and HARDWARE: Troubleshooting Guide. Warnings and Error messages explained
Xilinx Answer #1605 : EZTag Cable: May have problems programming 9500's from computers with EPP port
Xilinx Answer #1600 : LICENSING: How to check the version of the lmgrd license manager and XXACTD license daemons
Xilinx Answer #1579 : FPGA Configuration: Size of external pulldown needed to create a logic low.
Xilinx Answer #1577 : JTAG - Are there pullups/pulldowns in the TAP pins(XC4000, XC4000e, XC5200, XC4000EX)
Xilinx Answer #1574 : XChecker Cable: The order part number for xchecker cable.
Xilinx Answer #1554 : EDIF 2.0.0 naming conventions and translation of escaped Verilog names to EDIF
Xilinx Answer #1520 : XC2000L/XC3000L/XC4000L: Estimating power consumption for 3.3V Devices (2000L, 3000L, 4000L)
Xilinx Answer #1519 : FPGA Configuration: What Threshold does CCLK use for 5 Volt FPGAs?
Xilinx Answer #1494 : XC4000E/EX/XL/XV/XLT: Duty Cycle
Xilinx Answer #1475 : Download Cables: Difference between DLC-5 and DLC-4
Xilinx Answer #1456 : HardWire: XNFRPT -I
Xilinx Answer #1428 : FPGA Configuration: CCLK does not toggle in master mode.
Xilinx Answer #1424 : Programmers: Data I/O: Unisite Programmers issue "Partial Write Not Supported" error on 1700 devices
Xilinx Answer #1423 : XC3000/XC4000: Are the internal tri-state busses(3k,4k) PULLED Up by default?
Xilinx Answer #1397 : CONCEPT: How to attach LOC properties to IPAD4/8/16 & OPAD4/8/16 macors
Xilinx Answer #1393 : XEPLD Optimize: Unexpected error: epldinst.cc:40
Xilinx Answer #1390 : Operational level of voltage/current on FPGA inputs
Xilinx Answer #1386 : W/S License Manager: Why is there a feature line for VIEWLOGIC?
Xilinx Answer #1380 : Configuration takes a long time.
Xilinx Answer #1370 : How do I set the graphics mode in XDE (editLCA) for DOS?
Xilinx Answer #1368 : How to submit a file on the Xilinx Customer Upload area on our FTP site
Xilinx Answer #1361 : XDM, XDE: Cannot select XDE from XDM with a XC5200 part
Xilinx Answer #1356 : JTAG - Can TDI, TCK, TMS and TDO be connected to a user signal and BSCAN?
Xilinx Answer #1351 : XC4000/E: How to install the 4025 and 4025E data files for the XACT 5.2.1/6.0.1 software from the CD-ROM (workstation and PC)
Xilinx Answer #1347 : Can Xilinx Devices be wave soldered or immersed in solder?
Xilinx Answer #1332 : How to access the Xilinx anonymous FTP site with the IP address
Xilinx Answer #1310 : The HW-112 Programmer is also known as the PP2
Xilinx Answer #1306 : VHDL synthesis : tristate multiplexer versus combinatorial multiplexer.
Xilinx Answer #1297 : Xchecker: How can I use it on low-power "L" 3.3V parts?
Xilinx Answer #1294 : XC5200: 5200 schematic libraries contain 'BUFGP' and 'BUFGS' symbols
Xilinx Answer #1289 : Synopsys : How to use OSC5, OSC52, and CK_DIV Cells from the XC5200 Synthesys Libraries
Xilinx Answer #1272 : Cable - How many devices can Parallel III (JTAG) cable program in a chain?
Xilinx Answer #1270 : **XACT-CPLD: Using a guide (.GYD) file to define pin constraints for CPLDs
Xilinx Answer #1258 : Foundry7.0 for PC runs w/ Windows NT; ssetup may yield "device not attached"
Xilinx Answer #1240 : XKEY 5.2 under Windows 3.11 does not see the key, but works fine under DOS.
Xilinx Answer #1237 : Xchecker 5.2.1: Partlist.xct from xact\data directory is used for downloading instead of xpart.def
Xilinx Answer #1233 : CPLD: 9500 BSDL File: Syntax pin_map_string pin description and FPGA pin_map_string description
Xilinx Answer #1219 : JTAG - Is the routing used by the XC4000/XC5200 TAP pins visible in XDE, EPIC, or FPGA Editor?
Xilinx Answer #1215 : JTAG - When is Boundary Scan available for use in the XC4000 based families?
Xilinx Answer #1211 : JTAG - How to get the `Scan Educator' tool from TI's website for a basic understanding of JTAG
Xilinx Answer #1207 : What is the latest version of addtnm and maketnm? Where to get addtnm and maketnm?
Xilinx Answer #1201 : Synopsys, XACT: What is the latest version of XBLOXGEN?/Where to get XBLOXGEN?
Xilinx Answer #1198 : How to access the Xilinx anonymous FTP site
Xilinx Answer #1197 : How to access the Xilinx Customer Download area on our FTP site
Xilinx Answer #1196 : XC3000: XACT 6.0.x/5.2.x- Unable to target 3090(A, L) or 3190(A, L) TQ144 device
Xilinx Answer #1195 : Xchecker Cable: What is the CCLK circuitry in the Xchecker cable?
Xilinx Answer #1188 : BOUNDARY SCAN/JTAG: Timing Parameters (rise time, fall time, max frequency) for TMS,TCK, and TDI
Xilinx Answer #1180 : **Obsolete Solution**: XACT-CPLD : An unrecognized Symbol Type 'NOR7' was found in netlist
Xilinx Answer #1174 : JTAG - Mandatory instructions defined by IEEE standard 1149.1
Xilinx Answer #1172 : JTAG - What is the bit order of the Instruction Register in Xilinx FPGA's
Xilinx Answer #1169 : Design Manager: Visual Works v2.0 Fatal Error Out of Memory
Xilinx Answer #1140 : Programmers: EZTAG: How to turn off Data Protection (DP) for the 9500 in EZTAG?
Xilinx Answer #1095 : Xchecker Cable: Can the Xchecker cable be used to program via JTAG Programming? Where is TDO?
Xilinx Answer #1083 : Xchecker cable is not connected correctly - Invalid port name
Xilinx Answer #1082 : EZTAG: Causes of Program and Erase problems
Xilinx Answer #1059 : XNF Specification v6.1 is now available on ftp, including XC7000 supplement
Xilinx Answer #1040 : What are VCC_BUS and VSS_BUS pins
Xilinx Answer #1031 : Xchecker cannot be used in place of NeoCad download cable in Foundry environment
Xilinx Answer #941 : JTAG - Consecutive readbacks via the JTAG interface in the XC4000/XC5200/Spartan devices
Xilinx Answer #909 : NeoCad's compatibility with Solaris
Xilinx Answer #907 : XC5200: Minimum pulse width on PROGRAM to reconfigure a 5200 device : 5k configuration
Xilinx Answer #880 : How to reach Commercial Documentation Services (CDS) & Viewlogic telesales for hard-copy manuals
Xilinx Answer #874 : XC2000/XC3000/XC4000/XC52000: How to reach Chip Supply for dies, multi-chip module (MCM) information
Xilinx Answer #869 : CADENCE: How to contact technical support?
Xilinx Answer #864 : How to reach Viewlogic technical support.
Xilinx Answer #838 : Hardware Debugger 6.0.1: The Hardware Debugger can crash if too many waveform windows are opened at once
Xilinx Answer #784 : Tutorial Example
Xilinx Answer #740 : FPGA Configuration:Asynch Peripherial mode-Done goes high, ouputs not active.
Xilinx Answer #699 : 6.0: Programmable Key: Change parallel port settings if key is not seen.
Xilinx Answer #696 : Configuration: Hazards of exceeding 3K CCLK low time maximum in Slave Serial Mode
Xilinx Answer #668 : FITNET/FITEQN: packing more pterms into an FFB macrocell
Xilinx Answer #647 : test
Xilinx Answer #645 : PROTEL 2.4: XNF 5.0 netlister does not supprt CLB primitives
Xilinx Answer #620 : MAKEBITS 5.0, 5.1: -p option (disable done pullup) does not work for 4000 family
Xilinx Answer #614 : SYMGEN 5.1: Does not support Viewlogic Proseries user-defined color defaults
Xilinx Answer #603 : XC3000, XC4000 PACKAGING: Which way does the die face in a CB type package? (up)
Xilinx Answer #601 : Mistake: blank XIT problem record
Xilinx Answer #581 : PROTEL 2.2: Use of carry logic causes XNFPREP ERROR 3626
Xilinx Answer #574 : PROLINK 5.0: 'Device Select' option can't find device family (missing library)
Xilinx Answer #571 : PROTEL: Not annotating design produces XNFPREP ERROR 3517
Xilinx Answer #570 : PROTEL 2.2:Use of XBLOX symbols may cause XNFMERGE Error 220, XNFPREP ERROR 3520
Xilinx Answer #544 : XNFPREP 5.0: Use of 'S' SAVESIG flag does not always stop logic deletion!
Xilinx Answer #536 : Error in simulation of carry logic : cy4 symbol : incorrect delay attributes : hold time violation
Xilinx Answer #533 : Obsolete: XC4000, SYNOPSYS FPGA Compiler: Example .synopsys_dc.setup file
Xilinx Answer #531 : OBSOLETE
Xilinx Answer #528 : PROTEL 2.2: XACT 5.0 Netlister writes out incorrect LOC properties
Xilinx Answer #523 : ** OBSOLETE ** XEPLD PROGRAMMER HW-120: reports Product code error
Xilinx Answer #513 : XDE 5.1 EDITLCA: Use of 'SwapSig' command cause XDE to crash
Xilinx Answer #512 : XDM 5.1: Choosing 4013D Causes "Error in 4013D.SPD" Message
Xilinx Answer #501 : Protel 2.2 wirelister can cause XNFPREP Error 3520 due to misplaced xnf files
Xilinx Answer #497 : LCA files tied by Makebits tie do not always pass DRC, possible Fatal Error 301's
Xilinx Answer #494 : WORKVIEW is not licensed by the C key: the old key (AA,AB,AC) is still required
Xilinx Answer #479 : How are Xilinx programs affected by the Pentium bug?
Xilinx Answer #469 : Xilinx Software may crash on Pentium machines due to processor overheating
Xilinx Answer #461 : XNFPREP fails with Error 3506 on MODEL records
Xilinx Answer #458 : PACKAGING: IPC SM-782 information on Xilinx packages is available
Xilinx Answer #457 : XC4000 Readback: How to work around rdclk max high and low time specs
Xilinx Answer #449 : PROLINK 5.0 is available on the Xilinx BBS
Xilinx Answer #448 : XDE 5.0: Do IOB names in EDITLCA correspond to pin or pad locations?
Xilinx Answer #447 : MAKEBITS 5.0: Default for Done Timing option is different that in version 4.31
Xilinx Answer #443 : XACT 5 plastic BGA 225-pin package file has incorrect ceramic pinout
Xilinx Answer #441 : XNFBA 5.0: about ERROR 301 <delay> on <PIN> of <instance> is not annotated.The pin is connected to the signal <signal>.
Xilinx Answer #425 : XABEL 5.0: Making a registered preset signal
Xilinx Answer #422 : Novell Network support phone numbers, BBS, FTP site address
Xilinx Answer #421 : XABEL 5.0: How to optimize your XABEL design to use IOB flip-flops
Xilinx Answer #415 : Fast Integer Multipliers in Xilinx FPGAs -- Reprint from XCELL Issue #14
Xilinx Answer #413 : CY4MODE symbol: a library part containing carry mode information
Xilinx Answer #411 : XDE 5.0: May hang loading file over a LANTASTIC network
Xilinx Answer #407 : XNFPREP 5.0: ERROR 3609 with XBLOX designs with carrylogic and rloc_range
Xilinx Answer #406 : XNFPREP 5.0.0: Possible cause of error 3520, invalid primitive
Xilinx Answer #403 : Workstation licensing, XACT 5.0: Use XLMCON to debug them.
Xilinx Answer #398 : XNFPREP 5.0.0: error 4665, inverter on CLB K pin
Xilinx Answer #387 : XKEY 5.0: Possible workaround for [XLM:KEY_NOT_FOUND]|
Xilinx Answer #386 : SYNTHX 5.0: Possible cause of 'pin was not defined', design worked in last rev
Xilinx Answer #385 : Logic Modelling and XACT 5: Run lca2xnf with -m and -v options
Xilinx Answer #384 : AHDL2X 5.02: 'Assertion failed' error due to > 128 states
Xilinx Answer #383 : XACT 5.0 software WILL work in OS/2 environment
Xilinx Answer #373 : XACT 5.0 memory manager requirements for all products
Xilinx Answer #371 : XABEL 5.0, SYMGEN 5.0: pins are absent from symbol with istype 'reg,invert'
Xilinx Answer #365 : XDE 5.0:Downloading from Probe causes 'DONE did not go high'
Xilinx Answer #363 : Synthx 5.0 may report ignoring maxclbs option even though it uses it
Xilinx Answer #359 : LCA2XNF 5.0: -v option produces XNF 4 netlist
Xilinx Answer #357 : ABL2XNF 5.0:AHDL2X gives Error 0250 [XLM:AUTHORIZATION_FAILURE]
Xilinx Answer #356 : MAKEBITS 5.0:XC3000A/L,3100A: Input does not appear to be connected internally
Xilinx Answer #353 : XNFMERGE 5.0: About ERROR 221
Xilinx Answer #344 : XNFMERGE 5.0: ERROR 30 caused by TNM property on CLB primitive
Xilinx Answer #343 : XNFPREP 5.0: ERROR 7852 on CLB primitive with associated timing specs
Xilinx Answer #342 : XNFPREP 5.0:Pins on CLB primitives are always locked and unswappable
Xilinx Answer #340 : XACT 5.0 Programmable Key: May not be recognized/transparent on some machines
Xilinx Answer #339 : Xilinx BBS SWHELP listings PART2 as of 7-14-94
Xilinx Answer #338 : Xilinx BBS XFAE listings PART2 as of 7-14-94
Xilinx Answer #332 : Xilinx BBS DFAE listings as of 7-14-94
Xilinx Answer #331 : Xilinx BBS MCPMAT listings as of 7-14-94
Xilinx Answer #330 : Xilinx BBS SWHELP listings PART1 as of 7-14-94
Xilinx Answer #324 : XABEL 5.0: How to do standalone designs
Xilinx Answer #321 : LCA2XNF 5.0: -w option erroneously produces netlist with no delay information
Xilinx Answer #313 : Running under OS2 2.1
Xilinx Answer #312 : XACT 5.0: Running under Microsoft Windows 3.1
Xilinx Answer #301 : XACT 5 Libraries Guide: Error in ACLK and GCLK pad connectivity
Xilinx Answer #300 : XACT 5 Libary Guide: Reference to RLOC use on bufts is incorrect
Xilinx Answer #298 : XDE: Converting an XACT 5 lca file to pre-XACT 5 format.
Xilinx Answer #295 : Global Index: Errors On HBLKNM, H_SET, HU_SET index listings
Xilinx Answer #293 : XABEL 5.0: How to change colors on Sun version
Xilinx Answer #283 : PACKAGING, XC2000: 2064L-VQ64 package has identical pinout as the 2018L-VQ64
Xilinx Answer #282 : BBS - What to do about 'transfer aborted' messages
Xilinx Answer #276 : XACT 5 Library Guide Table 4-16: carry modes listed are missing '-'
Xilinx Answer #275 : XCHECKER: Is the HW-XCH3V adapter necessary with 3.3V XL or L devices?
Xilinx Answer #271 : Minimum delay specifications for Xilinx devices.
Xilinx Answer #269 : XABEL 5.0, ERROR 12500: Make sure you have environment variable set
Xilinx Answer #268 : XACT 5 license manager 'invalid data' error messages
Xilinx Answer #266 : XMAKE 5.0 fails to find user defined subhierarchy due to filename periods
Xilinx Answer #264 : XNFPREP: Possible cause of ERROR 4015
Xilinx Answer #263 : XNFMERGE ERROR 220 may be caused by multiple periods in filenames
Xilinx Answer #262 : XNFPREP: Certain IOB primitive configuration statements cause errors
Xilinx Answer #258 : ABL2XNF issues error, 'can't find <design>.bl0
Xilinx Answer #257 : XCHECKER issues WARNING 001 when executing a VERIFY
Xilinx Answer #256 : XACT 5 library guide: incorrect F3 carry logic connection in figure 4-18
Xilinx Answer #252 : XDE: PC Memory requirements for loading different parts into EDITLCA
Xilinx Answer #250 : XDM fails, 'can't find termcap.xct, aborting'
Xilinx Answer #249 : BBS: Getting control characters on screen in graphics mode
Xilinx Answer #232 : Procedure for returning defective devices RMA
Xilinx Answer #231 : **Obsolete Solution**: HW-120 : Unable to find programmer, stuck in "Waiting for CTS" or "downloading" mode
Xilinx Answer #229 : OBSOLETE *****
Xilinx Answer #228 : XC4000: capacitance of XC4000 inputs
Xilinx Answer #227 : Obsolete: SYNOPSYS: Will Synopsys 3.1 work with XSI 3.01?
Xilinx Answer #212 : FPGA Configuration: FAST CCLK causes dataframe error (INIT goes Low).
Xilinx Answer #211 : Workstation XDE: Whatever happened to get_memsize.csh
Xilinx Answer #204 : XC4000, XC4000E Ground bounce app note is available
Xilinx Answer #202 : FPGA CONFIGURATION: How to handle slow Vcc rise time, brown out problems
Xilinx Answer #201 : PACKAGING: sources for socket converters and test sockets
Xilinx Answer #197 : Quarterdeck technical support # is 310-392-9701
Xilinx Answer #196 : test
Xilinx Answer #194 : JTAG - How to use EXTEST instruction before configuration in a XC4K/XC5K device?
Xilinx Answer #191 : JTAG BSDL - Using TI ASSET tester with Xilinx BSDL files (Instruction_Private)
Xilinx Answer #187 : Xilinx BBS GENINFO listings as of 7-14-94
Xilinx Answer #185 : Xilinx BBS XFAE listings PART1 as of 7-14-94
Xilinx Answer #184 : Xilinx BBS CXC listings as of 7-12-94
Xilinx Answer #181 : FPGA Configuration: Shifting serially from PROM file (LSB or MSB first?).
Xilinx Answer #177 : XC4000: How are 4000A parts different from 4000 parts?
Xilinx Answer #176 : FPGA CONFIGURATION: Can CCLK run before data is sent?
Xilinx Answer #175 : XC4000H: Why are there two tristate pins (TP and TS ) on the 4000H IOBs?
Xilinx Answer #173 : XC4000/A: XC4000 and XC4000A bitstreams are NOT compatible!
Xilinx Answer #171 : Generating pin constraints from an LCA file
Xilinx Answer #169 : FPGA Configuration: Excessive loading on cclk may cause frame error.
Xilinx Answer #167 : memgen: mexecute fails in viewlogic, pc crashes
Xilinx Answer #163 : XC2000/XC4000/XC5200- I/O pullup/pulldown availability
Xilinx Answer #160 : PACKAGING: What is the lead finish for the various packages?
Xilinx Answer #159 : XNF file created by EDIF2XNF contains high-level symbols instead of primitives
Xilinx Answer #158 : FPGA Configuration: Done goes high but outputs never become active.
Xilinx Answer #157 : FPGA Configuration: time to get off D7 after rs, before RDY/BUSY in async periph
Xilinx Answer #156 : PACKAGING: PLCC Chips fail on multichip board--swapped in chips function ok.
Xilinx Answer #154 : XC4000H: Computing output transition time for 4000H
Xilinx Answer #152 : FPGA: Default configuration of 2000, 3000, 4000 family IOBs (pullup)
Xilinx Answer #151 : XC2000/XC3000/XC4000/XC5200: What set, reset capabilities do the 2000. 4000, 5200 flip flops have?
Xilinx Answer #150 : XC3000, XC4000:Can the longline weak keeper circuit in be used as a storage element?
Xilinx Answer #149 : FPGA Configuration: How to reconfigure one 3k/4k device out of a daisy chain
Xilinx Answer #148 : How to join Xilinx International Users Forum (XIUF)
Xilinx Answer #147 : XC2000/XC3000: Can the crystal oscillator be used before configuration?
Xilinx Answer #144 : PACKAGES: PACKAGING- Plastic packages are not hermetic.
Xilinx Answer #143 : JTAG - What is the state of the INIT pin during boundary scan configuration?
Xilinx Answer #139 : Data I/O Tech Support and BBS numbers
Xilinx Answer #134 : FPGA CONFIGURATION: Effect of power-glitch invoked reset on XC2000/3000 devices
Xilinx Answer #127 : PACKAGES: Sources and information for sockets, contactors, receptacles, lead forming.
Xilinx Answer #126 : XC3000/XC4000/XC4000: Clock Buffers- (ACLK GCLK BUFGP BUFGS): When to use them
Xilinx Answer #124 : FPGA Configuration:init goes low, addresses keep incrementing (master parallel)
Xilinx Answer #122 : XC3000/XC4000: Using latches in 3k and 4k designs
Xilinx Answer #121 : XC3000/XC4000: Pin sense of internal tristate buffers
Xilinx Answer #118 : Password for Hotline Solutions account on BBS is moose
Xilinx Answer #117 : FPGA Configuration: Preparing a bitstream for peripheral mode configuration.
Xilinx Answer #116 : XC3000/XC4000: Can I source ACLK/GCLK from internal logic? BUFGS, BUFGP?
Xilinx Answer #115 : Where to get H-SPICE models of Xilinx device I/O
Xilinx Answer #114 : XC2000/XC3000/XC4000/XC5200: About decoupling capacitors for FPGAs
Xilinx Answer #113 : List of Prototyping/configurable computer board manufacturers.
Xilinx Answer #106 : XC3100:Timing of Direct Connects
Xilinx Answer #100 : Xilinx Libraries: All Xilinx/Viewlogic components have a LEVEL= attribute to decrease runtime