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Xilinx Answer #100 : Xilinx Libraries: All Xilinx/Viewlogic components have a LEVEL= attribute to decrease runtime
Xilinx Answer #101 : Viewsim: About ? Nodes in Timing Simulations
Xilinx Answer #102 : FPGA Configuration: DONE Doesn't Go High; General XC4000 Debugging Hints
Xilinx Answer #103 : XC4000: The Five Configurations of TBUFs
Xilinx Answer #105 : Initializing Mentor QuickSim simulation: Net names for the global reset signal
Xilinx Answer #106 : XC3100:Timing of Direct Connects
Xilinx Answer #107 : XC4000: Table of Connections To and From BUFGP and BUFGS
Xilinx Answer #109 : PROcapture: Do not remove the security key during the middle of a session
Xilinx Answer #110 : Viewlogic Simulation: Forcing a value to a signal and then releasing will cancel any FLOATVAL attributes
Xilinx Answer #113 : List of Prototyping/configurable computer board manufacturers.
Xilinx Answer #114 : XC2000/XC3000/XC4000/XC5200: About decoupling capacitors for FPGAs
Xilinx Answer #115 : Where to get H-SPICE models of Xilinx device I/O
Xilinx Answer #116 : XC3000/XC4000: Can I source ACLK/GCLK from internal logic? BUFGS, BUFGP?
Xilinx Answer #117 : FPGA Configuration: Preparing a bitstream for peripheral mode configuration.
Xilinx Answer #118 : Password for Hotline Solutions account on BBS is moose
Xilinx Answer #120 : VST gets stuck or stalls while simulating
Xilinx Answer #121 : XC3000/XC4000: Pin sense of internal tristate buffers
Xilinx Answer #122 : XC3000/XC4000: Using latches in 3k and 4k designs
Xilinx Answer #123 : XC4000: Use NODELAY attribute to get (fast) Input FF databook speed w/o delay
Xilinx Answer #124 : FPGA Configuration:init goes low, addresses keep incrementing (master parallel)
Xilinx Answer #126 : XC3000/XC4000/XC4000: Clock Buffers- (ACLK GCLK BUFGP BUFGS): When to use them
Xilinx Answer #127 : PACKAGES: Sources and information for sockets, contactors, receptacles, lead forming.
Xilinx Answer #128 : ViewSim: Global reset signal names for 2k, 3k, 4k, 5k, 7k, and 9k (startup)
Xilinx Answer #130 : Mentor 8.x: PLD_DA can't instantiate components, parts come up blank. Can select comps, but not place them. Component $LCA/<device>/<component> does not exist
Xilinx Answer #134 : FPGA CONFIGURATION: Effect of power-glitch invoked reset on XC2000/3000 devices
Xilinx Answer #135 : WIR2XNF:SEC:license not found For product GENERIC Error 4:iwinit failure
Xilinx Answer #136 : PROMS: AT&T flash serial proms cannot FAST configure an XC4000 device
Xilinx Answer #138 : PROMS: How to program a 'D' type prom from a different type master prom with a HW-112
Xilinx Answer #139 : Data I/O Tech Support and BBS numbers
Xilinx Answer #140 : XC4000: weight of 4005CB164 in Military B package - 11.5 grams
Xilinx Answer #141 : QuickSim: Unable to resolve expression symbol lca_technology, NULL model will be inserted
Xilinx Answer #143 : JTAG - What is the state of the INIT pin during boundary scan configuration?
Xilinx Answer #144 : PACKAGES: PACKAGING- Plastic packages are not hermetic.
Xilinx Answer #146 : VIEWLOGIC programs report no license for symbol or schematic
Xilinx Answer #147 : XC2000/XC3000: Can the crystal oscillator be used before configuration?
Xilinx Answer #148 : How to join Xilinx International Users Forum (XIUF)
Xilinx Answer #149 : FPGA Configuration: How to reconfigure one 3k/4k device out of a daisy chain
Xilinx Answer #150 : XC3000, XC4000:Can the longline weak keeper circuit in be used as a storage element?
Xilinx Answer #151 : XC2000/XC3000/XC4000/XC5200: What set, reset capabilities do the 2000. 4000, 5200 flip flops have?
Xilinx Answer #152 : FPGA: Default configuration of 2000, 3000, 4000 family IOBs (pullup)
Xilinx Answer #154 : XC4000H: Computing output transition time for 4000H
Xilinx Answer #155 : PLD_DA Check: Unable to evaluate property, unable to resolve lca_technology
Xilinx Answer #156 : PACKAGING: PLCC Chips fail on multichip board--swapped in chips function ok.
Xilinx Answer #157 : FPGA Configuration: time to get off D7 after rs, before RDY/BUSY in async periph
Xilinx Answer #158 : FPGA Configuration: Done goes high but outputs never become active.
Xilinx Answer #159 : XNF file created by EDIF2XNF contains high-level symbols instead of primitives
Xilinx Answer #160 : PACKAGING: What is the lead finish for the various packages?
Xilinx Answer #161 : How to see more of the error messages in PROcapture status window
Xilinx Answer #163 : XC2000/XC4000/XC5200- I/O pullup/pulldown availability
Xilinx Answer #167 : memgen: mexecute fails in viewlogic, pc crashes
Xilinx Answer #168 : VST or VST386+ gives ''error, unable to load primitives''
Xilinx Answer #169 : FPGA Configuration: Excessive loading on cclk may cause frame error.
Xilinx Answer #170 : XC4000 JTAG - Can boundary scan pins be used for JTAG and standard input/output at the same time?
Xilinx Answer #171 : Generating pin constraints from an LCA file
Xilinx Answer #173 : XC4000/A: XC4000 and XC4000A bitstreams are NOT compatible!
Xilinx Answer #174 : SYNOPSYS/XSI: Using an Input Latch (ILD_1) with No Delay
Xilinx Answer #175 : XC4000H: Why are there two tristate pins (TP and TS ) on the 4000H IOBs?
Xilinx Answer #176 : FPGA CONFIGURATION: Can CCLK run before data is sent?
Xilinx Answer #177 : XC4000: How are 4000A parts different from 4000 parts?
Xilinx Answer #178 : XC4000: What values do rams contain immediately after configuration?
Xilinx Answer #179 : Can an old 2020 .PRG file be used to program the 7272 parts?
Xilinx Answer #181 : FPGA Configuration: Shifting serially from PROM file (LSB or MSB first?).
Xilinx Answer #183 : PROwave: Viewing an arbitrary set of signals as a bus in the waveform window
Xilinx Answer #184 : Xilinx BBS CXC listings as of 7-12-94
Xilinx Answer #185 : Xilinx BBS XFAE listings PART1 as of 7-14-94
Xilinx Answer #187 : Xilinx BBS GENINFO listings as of 7-14-94
Xilinx Answer #188 : SPROM: Data I/O Programmers: Addresses for controlling programmable resets / reset polarity of Xilinx SPROM
Xilinx Answer #189 : Licensing: Forcing XACT License programs to use LM_LICENSE_FILE (Not for M1 version of software)
Xilinx Answer #191 : JTAG BSDL - Using TI ASSET tester with Xilinx BSDL files (Instruction_Private)
Xilinx Answer #193 : CPLD XC7236 : Can I use the algorithm for a 7236 for a 7236A part?
Xilinx Answer #194 : JTAG - How to use EXTEST instruction before configuration in a XC4K/XC5K device?
Xilinx Answer #195 : FPGA CONFIGURATION : Which pins are driven during clear/initialization? (master par)
Xilinx Answer #196 : test
Xilinx Answer #197 : Quarterdeck technical support # is 310-392-9701
Xilinx Answer #198 : SYN2XNF: issues ERROR 220: 'can't find &__logic_1__.map'
Xilinx Answer #201 : PACKAGING: sources for socket converters and test sockets
Xilinx Answer #202 : FPGA CONFIGURATION: How to handle slow Vcc rise time, brown out problems
Xilinx Answer #204 : XC4000, XC4000E Ground bounce app note is available
Xilinx Answer #206 : Obsolete: Synopsys Design Compiler: report_timing asks for Design Time, technology license.
Xilinx Answer #208 : 94 DATA BOOK: Error, p2-165 1994 data book on 3064a -6, Tcko
Xilinx Answer #209 : 94 DATA BOOK: TCLKIN missing from 3030VQ64 pinout
Xilinx Answer #211 : Workstation XDE: Whatever happened to get_memsize.csh
Xilinx Answer #212 : FPGA Configuration: FAST CCLK causes dataframe error (INIT goes Low).
Xilinx Answer #214 : 94 DATA BOOK: DATA 4 (I) missing on page 2-43 of 1994 data book
Xilinx Answer #215 : Prolink may hang after blank check on some pcs
Xilinx Answer #216 : SYNPLIFY: How to manage hierarchy using the syn_netlist_hierarchy and syn_hier attributes?
Xilinx Answer #218 : Powerview: values not displayed on schematic during simulation
Xilinx Answer #219 : Global reset signal name for FPGAs/EPLDs
Xilinx Answer #220 : Obsolete: SYNOPSYS 3.1a: XBLOX synthetic library for needs to be re-analyzed.
Xilinx Answer #221 : What format is the .PRG file?
Xilinx Answer #223 : 94 DATA BOOK 3rd: error in 4005pq160 pinout, p. 2-57
Xilinx Answer #226 : VHDL: Implementing the XC3000/XC4000 readback function.
Xilinx Answer #227 : Obsolete: SYNOPSYS: Will Synopsys 3.1 work with XSI 3.01?
Xilinx Answer #228 : XC4000: capacitance of XC4000 inputs
Xilinx Answer #229 : OBSOLETE *****
Xilinx Answer #230 : 94 DATA BOOK 2nd: Presettable Down Counter on page 8-72 is misdrawn
Xilinx Answer #231 : **Obsolete Solution**: HW-120 : Unable to find programmer, stuck in "Waiting for CTS" or "downloading" mode
Xilinx Answer #232 : Procedure for returning defective devices RMA
Xilinx Answer #235 : SPROMS: Military Parts: What is an 'B', 'N', 'M' and 'R' grade parts?
Xilinx Answer #236 : 94 DATA BOOK: 4010 pinouts missing reference to DOUT page 2-63
Xilinx Answer #237 : Programming XC7000 part with a JEDEC file gives checksum error
Xilinx Answer #239 : JTAG - Avoiding inadvertent activation of boundary scan in Xilinx devices with Pull-up resistors
Xilinx Answer #240 : PROcapture: Do not use RAM16.1, RAM32.1, ROM16.1, and ROM32.1 components
Xilinx Answer #242 : XC3000 JTAG - How to use Boundary Scan in a XC3000 device?
Xilinx Answer #244 : SYNPLIFY: How to instantiate Xilinx specific components in HDL?
Xilinx Answer #246 : VIEWsynthesis: Infering an xc4000 `set' flip-flop or an inverted xc3000 `reset' flip-flop
Xilinx Answer #249 : BBS: Getting control characters on screen in graphics mode
Xilinx Answer #250 : XDM fails, 'can't find termcap.xct, aborting'
Xilinx Answer #251 : Viewsim:ERROR:Multiple conflicting floatval attributes
Xilinx Answer #252 : XDE: PC Memory requirements for loading different parts into EDITLCA
Xilinx Answer #253 : XSIMMAKE may hang up while running CHECK if viewdraw.ini has invalid library
Xilinx Answer #256 : XACT 5 library guide: incorrect F3 carry logic connection in figure 4-18
Xilinx Answer #257 : XCHECKER issues WARNING 001 when executing a VERIFY
Xilinx Answer #258 : ABL2XNF issues error, 'can't find <design>.bl0
Xilinx Answer #259 : 94 DATA BOOK has incorrect pinout for 73108 EPLD pin 160
Xilinx Answer #260 : XBLOX 5.x: Implementing DATA_REG in IOB resources
Xilinx Answer #262 : XNFPREP: Certain IOB primitive configuration statements cause errors
Xilinx Answer #263 : XNFMERGE ERROR 220 may be caused by multiple periods in filenames
Xilinx Answer #264 : XNFPREP: Possible cause of ERROR 4015
Xilinx Answer #265 : XACT 5 install:It is possible to install place and route tools but not packages
Xilinx Answer #266 : XMAKE 5.0 fails to find user defined subhierarchy due to filename periods
Xilinx Answer #267 : XPP 5.0.0: -d option programs proms incorrectly if .bit file is split across multiple proms
Xilinx Answer #268 : XACT 5 license manager 'invalid data' error messages
Xilinx Answer #269 : XABEL 5.0, ERROR 12500: Make sure you have environment variable set
Xilinx Answer #270 : 7318/7336 inverted input in UIM causes warning 205
Xilinx Answer #271 : Minimum delay specifications for Xilinx devices.
Xilinx Answer #275 : XCHECKER: Is the HW-XCH3V adapter necessary with 3.3V XL or L devices?
Xilinx Answer #276 : XACT 5 Library Guide Table 4-16: carry modes listed are missing '-'
Xilinx Answer #277 : Processing multi-page flat OrCAD designs.
Xilinx Answer #281 : Orcad: SDT2XNF 'DS35-SDT-ERROR-033, no standard libraries used'
Xilinx Answer #282 : BBS - What to do about 'transfer aborted' messages
Xilinx Answer #283 : PACKAGING, XC2000: 2064L-VQ64 package has identical pinout as the 2018L-VQ64
Xilinx Answer #284 : PPR 5.2: What are the SaveSig (S), eXternal (X) netflags?
Xilinx Answer #285 : PPR 5.2: Memory requirements for various parts
Xilinx Answer #287 : XDM, PPR 5.2: XDM forces the use of invalid default TIMESPEC syntax
Xilinx Answer #288 : 94 DATA BOOK: 4005Hpg223 pinout missing pins L15 and L3 PAGE 2-101
Xilinx Answer #292 : Mentor Version 8 Interface User Guide (April 1994): erroneous statement on page 11-63
Xilinx Answer #293 : XABEL 5.0: How to change colors on Sun version
Xilinx Answer #294 : Obsolete -- Orcad SDT2XNF, INF2XNF ERROR 1, internal program error, code 0, return code 3
Xilinx Answer #295 : Global Index: Errors On HBLKNM, H_SET, HU_SET index listings
Xilinx Answer #297 : PPR 5.0: Information for users upgrading from APR for 3000A designs
Xilinx Answer #298 : XDE: Converting an XACT 5 lca file to pre-XACT 5 format.
Xilinx Answer #300 : XACT 5 Libary Guide: Reference to RLOC use on bufts is incorrect
Xilinx Answer #301 : XACT 5 Libraries Guide: Error in ACLK and GCLK pad connectivity
Xilinx Answer #303 : PPR 5.0: About 'HEAPMGMT - heap error #6' under windows DOS shell
Xilinx Answer #305 : SYMGEN 5.2, XDM 5.2: XDM Appears to hang when SYMGEN is invoked
Xilinx Answer #306 : HM2RPM: Running with DFLT_LOGIC=TRUE may cause errors in XNFPREP, PPR
Xilinx Answer #308 : Mentor 8: Using XACT 5 Timespec, TNM on an old library XC3000A/XC4000 design
Xilinx Answer #309 : Determining if a mouse will work with the XACT 5.0 PC install program
Xilinx Answer #310 : FITNET DRC error, flip flop using both SET and RESET
Xilinx Answer #311 : PPR 5.0: PPR Error 9062: Global Buffer Driven by IO, IBUF
Xilinx Answer #312 : XACT 5.0: Running under Microsoft Windows 3.1
Xilinx Answer #313 : Running under OS2 2.1
Xilinx Answer #314 : XBLOX 5.x: Error message regarding CAST (20051, 20141, 20142, 20184, 20177, 20199, 20336)
Xilinx Answer #316 : Xsimmake 5.2: Error message says to run functional simulation
Xilinx Answer #321 : LCA2XNF 5.0: -w option erroneously produces netlist with no delay information
Xilinx Answer #324 : XABEL 5.0: How to do standalone designs
Xilinx Answer #326 : PPR 5.0: Methods to reduce PPR runtime
Xilinx Answer #328 : PPR 5.0: CST file constraints do not override schematic constraints
Xilinx Answer #329 : XACT 5.x Design Architect: calling up old design gives "cannot determine version" error
Xilinx Answer #330 : Xilinx BBS SWHELP listings PART1 as of 7-14-94
Xilinx Answer #331 : Xilinx BBS MCPMAT listings as of 7-14-94
Xilinx Answer #332 : Xilinx BBS DFAE listings as of 7-14-94
Xilinx Answer #334 : XNFPREP 5.0: IOB primitives w/inverted outputs give PPR ERROR 1305
Xilinx Answer #335 : 94 DATA BOOK 3rd: TQ176 package dimensions on page 4-18 are incorrect
Xilinx Answer #338 : Xilinx BBS XFAE listings PART2 as of 7-14-94
Xilinx Answer #339 : Xilinx BBS SWHELP listings PART2 as of 7-14-94
Xilinx Answer #340 : XACT 5.0 Programmable Key: May not be recognized/transparent on some machines
Xilinx Answer #341 : xnf2wir 5.0: VSM gives 'ER Error - Could not find WIR file startup.1.'
Xilinx Answer #342 : XNFPREP 5.0:Pins on CLB primitives are always locked and unswappable
Xilinx Answer #343 : XNFPREP 5.0: ERROR 7852 on CLB primitive with associated timing specs
Xilinx Answer #344 : XNFMERGE 5.0: ERROR 30 caused by TNM property on CLB primitive
Xilinx Answer #345 : PPR 5.0: Getting report of timespec failed paths BEFORE routing phase
Xilinx Answer #347 : XDE/EDITLCA 5.0: Explanation of ODF, OLF, DBK, LOG files
Xilinx Answer #348 : 94 DATA BOOK: P 2-68 incorrectly list 4025 as available in mq208, not in pq223
Xilinx Answer #351 : VIEWSIM Error, XC7000 EPLD: Could not find WIR file xc7000:pl22v10.1
Xilinx Answer #353 : XNFMERGE 5.0: About ERROR 221
Xilinx Answer #354 : Behavioral blocks in EPLD schematic are not being updated
Xilinx Answer #356 : MAKEBITS 5.0:XC3000A/L,3100A: Input does not appear to be connected internally
Xilinx Answer #357 : ABL2XNF 5.0:AHDL2X gives Error 0250 [XLM:AUTHORIZATION_FAILURE]
Xilinx Answer #358 : SYN2XNF 3.4 / XACT 5.0: about XNFMERGE error 221 (processing hard macros)
Xilinx Answer #359 : LCA2XNF 5.0: -v option produces XNF 4 netlist
Xilinx Answer #360 : PPR 5.0: Possible cause of Segmentation or Memory Protection faults (TNMs)
Xilinx Answer #361 : PPR 5.0: Notplace * constraint with MD0, MD1 pins gives errors 9016, 9034
Xilinx Answer #362 : What is the fastest pin to pin delay?
Xilinx Answer #363 : Synthx 5.0 may report ignoring maxclbs option even though it uses it
Xilinx Answer #365 : XDE 5.0:Downloading from Probe causes 'DONE did not go high'
Xilinx Answer #366 : XMAKE 5.2:Error 3515,3516 about mixed libraries when -L used on old design
Xilinx Answer #367 : XACT 5: Acessing fast input pins for High Density Function Blocks
Xilinx Answer #370 : XDELAY 5.2: Correlating delays through TBUFs with data book values
Xilinx Answer #371 : XABEL 5.0, SYMGEN 5.0: pins are absent from symbol with istype 'reg,invert'
Xilinx Answer #372 : XDM 5.2: Symgen does not appear in menus if XC7200 or XC7300 part is selected
Xilinx Answer #373 : XACT 5.0 memory manager requirements for all products
Xilinx Answer #374 : XDELAY 5.0:SelectSpec option setting not saved in template file.
Xilinx Answer #376 : Possible cause of 'pld pds files not found'
Xilinx Answer #377 : XDM 5.0 only allows you to set APR seed value of 0-99
Xilinx Answer #378 : XACT 5: Using ViewSim to simulate board-level epld design
Xilinx Answer #380 : 94 Data Book: page 3-52, pinout for 73108pq160 error: pin 160 is GND
Xilinx Answer #382 : PPR 5.0: May ignore MAP=PLC on XC3000A CLBMAP symbols
Xilinx Answer #383 : XACT 5.0 software WILL work in OS/2 environment
Xilinx Answer #384 : AHDL2X 5.02: 'Assertion failed' error due to > 128 states
Xilinx Answer #385 : Logic Modelling and XACT 5: Run lca2xnf with -m and -v options
Xilinx Answer #386 : SYNTHX 5.0: Possible cause of 'pin was not defined', design worked in last rev
Xilinx Answer #387 : XKEY 5.0: Possible workaround for [XLM:KEY_NOT_FOUND]|
Xilinx Answer #388 : PPR 5.0, 3064APG132 package: Possible cause of Error 5807
Xilinx Answer #390 : GEN_SCH8 5.x: Can't open shared lib /tools/idea/lib/libC.sl
Xilinx Answer #391 : PLD_DA/Design Architect: "Error: Attempt to connect failed (for child of schematic named schematic)"
Xilinx Answer #392 : XSIMMAKE 5.2, Viewlogic: Possible cause of ERROR 7
Xilinx Answer #396 : EDIF2XNF 5.x: Error 3, port name not found on external library primitive for cell
Xilinx Answer #398 : XNFPREP 5.0.0: error 4665, inverter on CLB K pin
Xilinx Answer #400 : XSIMMAKE/XDRAW 5.2: XSIMMAKE seemingly halts exectution during XDRAW
Xilinx Answer #403 : Workstation licensing, XACT 5.0: Use XLMCON to debug them.
Xilinx Answer #406 : XNFPREP 5.0.0: Possible cause of error 3520, invalid primitive
Xilinx Answer #407 : XNFPREP 5.0: ERROR 3609 with XBLOX designs with carrylogic and rloc_range
Xilinx Answer #409 : PPR 5.2: Defining point-to-point timespecs in cst file
Xilinx Answer #411 : XDE 5.0: May hang loading file over a LANTASTIC network
Xilinx Answer #412 : PPR 5.0: PPR (possibly other programs) gives PHARLAP error when invoked
Xilinx Answer #413 : CY4MODE symbol: a library part containing carry mode information
Xilinx Answer #414 : 2.1i: NGD2EDIF: WARNING:NgdHelpers:33 - NOTE: This design contains the undriven net "PRLD"
Xilinx Answer #415 : Fast Integer Multipliers in Xilinx FPGAs -- Reprint from XCELL Issue #14
Xilinx Answer #416 : PPR 5.0: using XDE-EDITLCA colorblk command in guide file may cause error 12205
Xilinx Answer #417 : PROwave: Dynamic annotation of signal values in PROcapture stored in PROwave
Xilinx Answer #419 : PPR 5.0: Constraining RPMs in a CST file (includes RPMCON instructions)
Xilinx Answer #420 : PPR 5.0: TNM placed on a net does not get traced forward to all elements
Xilinx Answer #421 : XABEL 5.0: How to optimize your XABEL design to use IOB flip-flops
Xilinx Answer #422 : Novell Network support phone numbers, BBS, FTP site address
Xilinx Answer #424 : XABEL 5.0 and XC7000 EPLDS: The .D extension is not supported by PLUSASM
Xilinx Answer #425 : XABEL 5.0: Making a registered preset signal
Xilinx Answer #426 : XABEL 5.0, XC7000 EPLD: Trouble accessing D1 and D2 alu pins
Xilinx Answer #427 : SYNOPSYS FPGA COMPILER: To prevent Timespecs from apprearing in the XNF file.
Xilinx Answer #428 : VIEWSIM: How to fix 'Could not open VHDL file...', 'Unrecognized component...'
Xilinx Answer #429 : PLD_DA/EDIF2XNF 5.x: LOC properties placed on pads do not appear in netlist
Xilinx Answer #431 : XNFPREP: Possible cause of 'ERROR 1303, comma required' on Orcad designs
Xilinx Answer #432 : How flip-flop initial states are determined
Xilinx Answer #433 : FPGA COMPILER 3.1a and XSI 3.01: About 'cannot read library version'
Xilinx Answer #435 : PowerView,wir2xnf,xnf2wir: Working around 'SEC: host is not responding'
Xilinx Answer #436 : XPP 5.0: Why does it always ask for the "first" device?
Xilinx Answer #437 : PPR 5.0:Possible cause of 'Error 5805: Constraints to mapping symbol conflict'
Xilinx Answer #438 : SYNOPSYS: XNFPREP issues ERROR 3673 due to multiple clock buffers inserted.
Xilinx Answer #439 : 94 DATA BOOK: Error in PG299 Package Drawing, page 4-24
Xilinx Answer #440 : XC2000: XDE 5.0: About "Can't open 2018.spd" message.
Xilinx Answer #441 : XNFBA 5.0: about ERROR 301 <delay> on <PIN> of <instance> is not annotated.The pin is connected to the signal <signal>.
Xilinx Answer #443 : XACT 5 plastic BGA 225-pin package file has incorrect ceramic pinout
Xilinx Answer #445 : SYN2XNF pre-3.5.0: About 'ERROR 220: Can't open file 'vcc_.xnf'.'
Xilinx Answer #446 : Error "could not read design database"
Xilinx Answer #447 : MAKEBITS 5.0: Default for Done Timing option is different that in version 4.31
Xilinx Answer #448 : XDE 5.0: Do IOB names in EDITLCA correspond to pin or pad locations?
Xilinx Answer #449 : PROLINK 5.0 is available on the Xilinx BBS
Xilinx Answer #450 : 94 DATA BOOK 2nd: Which 7300 outputs have 24mA drive capability?
Xilinx Answer #452 : XNFPREP 5.0 issues error 7859 on a Timespec attribute.
Xilinx Answer #453 : SYN2XNF: Use of -s option causes creation of EXT records, XNFPREP Error 3527
Xilinx Answer #456 : Mentor Autologic: inserting PADs instead of PORTs causes XNFPrep ERROR 3527
Xilinx Answer #457 : XC4000 Readback: How to work around rdclk max high and low time specs
Xilinx Answer #458 : PACKAGING: IPC SM-782 information on Xilinx packages is available
Xilinx Answer #459 : Use of /MR as input precludes use as reset, even during initialization
Xilinx Answer #460 : Slow VCC rise time does not require use of /MR as a 'hold-off'
Xilinx Answer #461 : XNFPREP fails with Error 3506 on MODEL records
Xilinx Answer #463 : PLD_DVE/PLD_DVE_Sim 5.x appears to hang
Xilinx Answer #464 : XSIMMAKE 5.2: XSIMMAKE may run XBLOX on a design even after you remove all XBLOX logic
Xilinx Answer #465 : SPROMS: Configuration: 8-pin sockets w/built-in capacitors can cause multi-prom config problems
Xilinx Answer #466 : PPR 5.0 will not guide correctly with a pre-XACT 5.0 lca file
Xilinx Answer #467 : XEMAKE: Schematic design changes are ignored
Xilinx Answer #469 : Xilinx Software may crash on Pentium machines due to processor overheating
Xilinx Answer #472 : Differences between the 7318/7336 and 7354/7372/73108/73144
Xilinx Answer #473 : Possible cause of Error 'tl2035 the xnf file cannont be read by XEMAKE'
Xilinx Answer #476 : SPROMS: File Formats: Description of PROM/EEPROM file formats (Intel MCS, Motorola EXOR, Tektronix HEX)
Xilinx Answer #478 : PPR 5.0 and Timespec: How to use the timespec 'ignore' property
Xilinx Answer #479 : How are Xilinx programs affected by the Pentium bug?
Xilinx Answer #482 : XNF2WIR 5.x: Gives Error 210 if CY4 symbol is in design using pre XACT5 libs
Xilinx Answer #483 : PPR 5.0: Possible cause of Error 5607: Design has not been flattened
Xilinx Answer #485 : XNF2WIR ERROR 210 : could not load symbol of type [COULD_NOT_IDENTIFY]
Xilinx Answer #486 : VIEWSIM timing simulation: "x" on the output of flip flop. XSIMMAKE
Xilinx Answer #488 : SYNOPSYS: How to instantiate BSCAN in the 4k/5k in Verilog/VHDL in Synopsys (FPGA Compiler, Design Compiler, FPGA Express)
Xilinx Answer #489 : 94 DATA BOOK: page 2-148, 3090TQ176 pinout error: VSS (pin 133) is VCC
Xilinx Answer #492 : FPGA Configuration: Minimum pulse width for PROG to reconfigure an FPGA.
Xilinx Answer #494 : WORKVIEW is not licensed by the C key: the old key (AA,AB,AC) is still required
Xilinx Answer #495 : XSIMMAKE 5.0, 5.1, 5.2: Possible cause of XNFBA error 301.
Xilinx Answer #497 : LCA files tied by Makebits tie do not always pass DRC, possible Fatal Error 301's
Xilinx Answer #499 : XC4000/XC5200: How accurate are the internal oscillators in these devices?
Xilinx Answer #500 : PPR, WIR2XNF 5.0: Possible cause of PPR error 9016: use of -f option
Xilinx Answer #501 : Protel 2.2 wirelister can cause XNFPREP Error 3520 due to misplaced xnf files
Xilinx Answer #504 : SYNPLIFY: How to prevent the grouping of ports into arrays in the output EDIF netlist using the syn_noarrayports attribute?
Xilinx Answer #505 : WIR2XNF 5.0: About 'Unexpected token design_may_contain_rippers_recompilation..'
Xilinx Answer #508 : XC4000/XC5200: PROGRAM pin designed to ignore glitches <50nS)
Xilinx Answer #509 : Mentor Graphics 8.x on Sun workstations: F1 key gives Sun help instead of Mentor functions
Xilinx Answer #510 : SYNPLIFY: "tristate driver NoName on net NoName has its enable tied to GND"
Xilinx Answer #512 : XDM 5.1: Choosing 4013D Causes "Error in 4013D.SPD" Message
Xilinx Answer #513 : XDE 5.1 EDITLCA: Use of 'SwapSig' command cause XDE to crash
Xilinx Answer #514 : PPR 5.1, XC3000A: PPR Routes 3000A Pip in the Wrong Direction
Xilinx Answer #515 : SYNOPSYS FPGA COMPILER: Problems reading an XNF file back into Synopsys.
Xilinx Answer #517 : Programmers: DATA IO UNISITE: Programmer v4.7:Complains that 17128D bitstream is 4 bytes short
Xilinx Answer #519 : 94 DATA BOOK 2nd Edition: P. 2-85, PG156 package is missing I/O (A6) pin number
Xilinx Answer #520 : PPR 5.0: PPR 5.0 'HP_anneal' HP-PA version expiration override code
Xilinx Answer #522 : VST/386+ Gives "Terminal Error - Incompatible Version of MODEL Files."
Xilinx Answer #523 : ** OBSOLETE ** XEPLD PROGRAMMER HW-120: reports Product code error
Xilinx Answer #524 : PPR 5.1: Use of 5.0 guide file with XBLOX counters causes ERROR 9081
Xilinx Answer #525 : PPR 5.0: produces ERROR 1173, 'can't find .tpm file for the NOTH_PICMAP cell'
Xilinx Answer #526 : MAKEPROM 5.1: 'Address is greater than 64k' error, using MCS format - what to do
Xilinx Answer #527 : PPR 5.1:Possible cause of ERROR 9015 on XC3000 design (placement constraints)
Xilinx Answer #528 : PROTEL 2.2: XACT 5.0 Netlister writes out incorrect LOC properties
Xilinx Answer #529 : Possible cause of XSIMMAKE 5.0 ERROR 7 (sh: 17067 Memory fault - core dumped)
Xilinx Answer #530 : PPR 5.0,5.1: Possible cause of bad grouping using statements on TIMEGRP symbol
Xilinx Answer #531 : OBSOLETE
Xilinx Answer #533 : Obsolete: XC4000, SYNOPSYS FPGA Compiler: Example .synopsys_dc.setup file
Xilinx Answer #534 : Obsolete: XC4000, SYNOPSYS Design Compiler: Example .synopsys_dc.setup file
Xilinx Answer #536 : Error in simulation of carry logic : cy4 symbol : incorrect delay attributes : hold time violation
Xilinx Answer #537 : Obsolete: XC3000, SYNOPSYS Design Compiler: Example .synopsys_dc.setup file
Xilinx Answer #538 : Obsolete: XC7000, SYNOPSYS FPGA/Design Compiler: Example .synopsys_dc.setup file
Xilinx Answer #542 : XSI/SYNOPSYS: Constraining I/O pin locations from within Synopsys.
Xilinx Answer #543 : XABEL 5.1/EPLD designs: FOE pins are active *high*
Xilinx Answer #544 : XNFPREP 5.0: Use of 'S' SAVESIG flag does not always stop logic deletion!
Xilinx Answer #547 : MEN2XNF8 5.x: Could not find a registered simulation model with label: 'xc____'
Xilinx Answer #549 : SYNOPSYS: How to invert the reset (GSR/GR) pin on the STARTUP block?
Xilinx Answer #552 : VST: Possible cause of terminal error..."I" found as device pin number
Xilinx Answer #555 : Error es14 or es6: Too many shared D1 product terms
Xilinx Answer #556 : POWERVIEW 5.3.1, WIR2XNF 5.x:Error 4 'Couldn't find workview.msg in WDIR'
Xilinx Answer #557 : XBLXGS 5.x: possible cause of error "Bad status 79500182 from ddp_perform_check"
Xilinx Answer #558 : Obsolete -- Orcad: SDT2XNF fatal error DS35-SDT-ERROR-008: syntax error in inf file
Xilinx Answer #560 : SYNPLIFY: How to infer an enable register for a tri-state (storing 'z' over multiple clock cycles)?
Xilinx Answer #564 : FPGA COMPILER: PULLUPs/PULLDOWNs must be instantiated when using Synopsys.
Xilinx Answer #568 : 94 DATA BOOK 3rd: page 3-64, pinout error for 73144PQ160
Xilinx Answer #570 : PROTEL 2.2:Use of XBLOX symbols may cause XNFMERGE Error 220, XNFPREP ERROR 3520
Xilinx Answer #571 : PROTEL: Not annotating design produces XNFPREP ERROR 3517
Xilinx Answer #574 : PROLINK 5.0: 'Device Select' option can't find device family (missing library)
Xilinx Answer #575 : Design doesn't fit using 5.1, but used to fit with 5.0
Xilinx Answer #577 : XNF2WIR returns error 201 if viewdraw.ini is not in project directory
Xilinx Answer #581 : PROTEL 2.2: Use of carry logic causes XNFPREP ERROR 3626
Xilinx Answer #583 : PROcapture 6.0: Iconified PROcapture automatically quits on MS Windows exit
Xilinx Answer #584 : PPR 5.x guide may leave clock enable on flip-flops where CE was removed (3000A)
Xilinx Answer #586 : PROsynthesis PC INSTALL: PC locks up/crashes while installing, possible cause
Xilinx Answer #587 : VIEWLOGIC SIMULATION: FXC2K, FXC3K, FXC4K, FXC7K libs give quicker simulation
Xilinx Answer #588 : PROCAPTURE: cannot recognize the Xilinx C key. (No valid license for product)
Xilinx Answer #590 : PROSERIES: Plotting, other features are not MS Windows standard.
Xilinx Answer #592 : PROFLOW: Does not call PPR with all user-defined parameters (PPR.PRO problem)
Xilinx Answer #594 : VIEWLOGIC PROFLOW 6.0: Will continue executing after Xilinx errors occur.
Xilinx Answer #597 : PROcapture: Plotting to PostScript file doesn't work, possible cause (SHARE.EXE)
Xilinx Answer #598 : PROSERIES 6.0: About error, "386 chip is currently exectuing in virtual mode"
Xilinx Answer #601 : Mistake: blank XIT problem record
Xilinx Answer #603 : XC3000, XC4000 PACKAGING: Which way does the die face in a CB type package? (up)
Xilinx Answer #604 : Viewlogic PROseries 6.0: System Error, sharing violation on drive <drive>:
Xilinx Answer #606 : XDELAY 5.2.1: How to make all the TSspecs in -SelectSpec unhighlighted
Xilinx Answer #609 : WIR2XNF 5.x: INIT attribute on macros may not be passed to lower levels.
Xilinx Answer #614 : SYMGEN 5.1: Does not support Viewlogic Proseries user-defined color defaults
Xilinx Answer #615 : Unbonded Fast Output Enable (FOE) can't be specified.
Xilinx Answer #618 : Timsim8/PLD_DVE_BA: "WARNING: Unknown design object" on Autologic design
Xilinx Answer #619 : XACT 5.x QuickSim: Board-level simulation for Xilinx FPGAs and CPLDs
Xilinx Answer #620 : MAKEBITS 5.0, 5.1: -p option (disable done pullup) does not work for 4000 family
Xilinx Answer #621 : PROWAVE: Printing section of waveform causes entire waveform to print.
Xilinx Answer #622 : Programmers: XELTEK: SuperPro, SuperPro II has a bad XC7318/1736 algorithm (ver. 2.2)
Xilinx Answer #623 : XACT 5.x/M1 and Mentor compatibility information
Xilinx Answer #626 : EPLD Muncher always returns a warning on OrCAD OBUFT symbols
Xilinx Answer #627 : VERILOG-XL: How to handle upper/lower case conversion of Verilog signal names?
Xilinx Answer #630 : SYNOPSYS: How to tell what version of XSI (Xilinx-Synopsys Interface) you have.
Xilinx Answer #632 : PROsim, ViewSim: Using the LOADM command with Xilinx FPGA simulations
Xilinx Answer #633 : XC5200: How to shut off the internal oscillator
Xilinx Answer #635 : XSIMMAKE/CHECK: Gives Error 7 when run from the Design Manager (PROSERIES)
Xilinx Answer #637 : PROFLOW: Does not always display all available Xilinx device speed grades.
Xilinx Answer #640 : FPGA Express 3.x: Expression is ambiguous (VSS-501)
Xilinx Answer #644 : LogiCORE PCI: How to obtain copies of the PCI specification (from the PCI SIG)
Xilinx Answer #645 : PROTEL 2.4: XNF 5.0 netlister does not supprt CLB primitives
Xilinx Answer #647 : test
Xilinx Answer #648 : VERILOG-XL: Buffer output does not follow transitions on its input (transport and inertial delays)
Xilinx Answer #650 : CADENCE CONCEPT: Attaching multiple LOC constraints / properties / attributes to XBLOX components
Xilinx Answer #651 : PPR Error 5802: PGA package pin location "Uxx" assumed to be unbonded
Xilinx Answer #653 : Program under Windows error: GROWSTUB General Protection Fault, pointer.dll
Xilinx Answer #654 : Hardware Debugger: Error states a file cannot be opened when it is actually corrupted
Xilinx Answer #655 : Using OrCAD Capture with XACT
Xilinx Answer #657 : FLOORPLANNER-XACT: PPR May Fail Due to Invalid Floorplanner Placement
Xilinx Answer #658 : FLOORPLANNER-XACT: Warning 12926 : constraints file read that contains wildcards.
Xilinx Answer #659 : FLOORPLANNER-XACT: Multiple periods are not supported in filenames
Xilinx Answer #660 : FLOORPLANNER-XACT: Printing hangs the system if no default printer is selected.
Xilinx Answer #661 : FLOORPLANNER-XACT: Will not load file from directory that only has group write permission.
Xilinx Answer #662 : FLOORPLANNER-XACT: Saving a file to a write protected floppy results in a system error.
Xilinx Answer #663 : XNF2NGD Core dumps due to bad or missing part statement in XNF file.
Xilinx Answer #664 : Programmer reports bad checksum for BG225 .PRG file
Xilinx Answer #665 : Sun4 version of Muncher fails with usage error
Xilinx Answer #666 : 7336 or 7318 functions incorrectly after being programmed by Data I/O programmer
Xilinx Answer #667 : XEMAKE/XEMAKE6: schematic design functions incorrectly in simulation or in system
Xilinx Answer #668 : FITNET/FITEQN: packing more pterms into an FFB macrocell
Xilinx Answer #669 : No PLD file created when running from XDM
Xilinx Answer #671 : Error cl192 or cl126 while converting a PALASM (PDS) file
Xilinx Answer #672 : XACT: Xdelay/Timing Analyzer 6.0: Reported Setup Value on Carry Logic Path appears erroneous
Xilinx Answer #673 : Design Manager 6.0.1: Unhandled exception in 256 color mode on Compaq QVision boards.
Xilinx Answer #674 : SPROMS: Markings: XC1700 Ordering ID (part number) and PROM Marking ID are different for the same part
Xilinx Answer #675 : XABEL 5.1 (BLIFOPTX) fails on Truth Table designs
Xilinx Answer #677 : PPR 5.2.0, 4000E: Data read during Dual Port RAM simultaneous read and write is incorrect
Xilinx Answer #678 : PROflow: DOS Error # 83: Buffer too small
Xilinx Answer #679 : Prom file formatter fails with an error: Could not get model for statbar!
Xilinx Answer #680 : Obsolete -- Orcad: SDT2XNF Fails to write TNMs into the .XNF file
Xilinx Answer #681 : XEMAKE6 gives the error: hi10:[Warning] Cannot open CTL file <design>.ctl.
Xilinx Answer #682 : abnormal program termination memory protection (or Page) fault
Xilinx Answer #687 : XSimMake, XDraw: "Could not access Sheet 1 of SCHEMATIC <top>." Powerview 5.3.2
Xilinx Answer #688 : SYNPLIFY: How to infer the BUFGDLL cell for Virtex using the xc_clockbuftype attribute?
Xilinx Answer #691 : XSimMake: How to modify flows to run user programs, scripts, or batch files
Xilinx Answer #692 : EDIF2XNF: LOC or other I/O properties lost (ENWrite net bundles)
Xilinx Answer #694 : PPR 5.2.0 issues error 5846 on designs where the aclk or gclk is fed from a clb and the clb location is constrained
Xilinx Answer #695 : XC4000H: Input/Output mode defaults for 4000H
Xilinx Answer #696 : Configuration: Hazards of exceeding 3K CCLK low time maximum in Slave Serial Mode
Xilinx Answer #697 : 6.0: About WIN32S and XACTstep 6.0 (Design Manager Hangs)
Xilinx Answer #698 : 6.0, Compaq: Design Manager may give Unhandled Exception in 256 Color Mode.
Xilinx Answer #699 : 6.0: Programmable Key: Change parallel port settings if key is not seen.
Xilinx Answer #700 : 6.0: About "Problem inv.PROCapture...Leave PSFM"
Xilinx Answer #701 : 6.0: Memory requirements for various parts.
Xilinx Answer #703 : 6.0: PC install requires Swap Space > 0 Meg, due to Win32s.
Xilinx Answer #704 : 6.0: PC hangs if Virtual Memory is checked while Design Manager is running.
Xilinx Answer #705 : 6.0: List of files that XACTstep 6.0 install places in c:\windows and c:\windows\system
Xilinx Answer #706 : 6.0: win32s/WinProbe may cause Design Manager to hang during translate.
Xilinx Answer #707 : FITNET will not use PIN 1 (MR) even if MRINPUT=ON was specified in Viewlogic
Xilinx Answer #709 : Design Manager/Flow Engine 6.0.1: GROWSTUB General Protection Fault, pointer.dll
Xilinx Answer #710 : Design Manager 6.0.1: Cannot find input design or work directory
Xilinx Answer #711 : Design Manager 6.0.1: win32s/WinProbe may cause Design Manager to hang during translate under Windows 3.11
Xilinx Answer #713 : PROsim hangs with a win32s error (multiple causes/resolutions)
Xilinx Answer #715 : 6.0: "Win32s requires file sharing and locking support. Please execute share.exe before continuing" (vshare.386)
Xilinx Answer #716 : Design Manager 6.0.1: System Error, Unhandled Exception: Subscript out of bounds.
Xilinx Answer #717 : **OBSOLETE** CADENCE ES-Verilog interface is available on the 5.2/6.0 CD
Xilinx Answer #718 : Flow Engine 6.0.1: Optimize Step Must Be Run to Read in XACT-Performance Changes in Constraints File
Xilinx Answer #720 : Design Manager 6.0.1: PC hangs if Virtual Memory is checked while Design Manager is running.
Xilinx Answer #721 : Design Manager/Flow Engine 6.0.1: cancel button can cause memory leaks
Xilinx Answer #722 : Design Manager M1.5: Timing Simulation Data (time_sim.*) is not created
Xilinx Answer #723 : Design Manager 6.0.1: Target Family cannot be changed after project is created
Xilinx Answer #724 : Design Manager/Flow Engine 6.0: Application Error: Stack Overflow
Xilinx Answer #725 : Design Manager 6.0.1: Calling DOS program within a Windows application causes screen to go blank
Xilinx Answer #726 : 2.1i Design Manager: New behavior for UCF declaration introduced in SP3
Xilinx Answer #727 : Design Manager 6.0.1: Translate fails to creat a Version/Revision
Xilinx Answer #728 : Design Manager 6.0.1: Unable to create directory for the new revision
Xilinx Answer #729 : Design Manager 6.0.1: Manually deleting project data can cause System Error
Xilinx Answer #730 : Design Manager 6.0.1: Attempts to Rename the Design Name causes System Error
Xilinx Answer #731 : Design Manager 6.0.1: Report Browser error: The report file is missing
Xilinx Answer #732 : Flow Engine 6.0.1: Changes to Options Templates are not used
Xilinx Answer #733 : Design Manager 6.0.1: Guide Data Specified in two Dialogs
Xilinx Answer #734 : SIMPRIMS: What is the usage of the X_SUH cell?
Xilinx Answer #735 : PLD_DMGR error in Solaris 2.x: font could not be loaded, loading failed
Xilinx Answer #736 : X2VPREP/TIMENET/TIMENETX: Error--Incompatible netlist version
Xilinx Answer #738 : XBLOX 5.x: internal error 20224, representation_error
Xilinx Answer #739 : Gen_sch8 fails under Mentor B.x with "call to undefined procedure"
Xilinx Answer #740 : FPGA Configuration:Asynch Peripherial mode-Done goes high, ouputs not active.
Xilinx Answer #741 : After Installing XACT 5.2/6.0 user can no longer plot from Viewlogic Software
Xilinx Answer #746 : Install: Online Help Hyperlinks do no work on workstation (sun, sparc, hp), Acrobat v1.0
Xilinx Answer #747 : FLOORPLANNER-XACT: The Floorplanner may cause segmentation faults/core dumps
Xilinx Answer #749 : CPLD Datasheets - How to get 9500 or 9500XL information?
Xilinx Answer #751 : XNF2WIR Error 10: Unknown record type 'bsm(X).xnf'.
Xilinx Answer #752 : Design Manager: System Error, Unhandled Exception: ERROR_FILE_NOT_FOUND
Xilinx Answer #754 : Design Manager 6.0.1: Translate process gives memory allocation error
Xilinx Answer #755 : PROSeries is not compatible with Windows 95/NT
Xilinx Answer #756 : CONCEPT-HDL: Virtex-E support?
Xilinx Answer #757 : PPR ignores timing constraints when invoked from the command line
Xilinx Answer #758 : Programmers: HW-130: Programmer flashes red FAIL light with HW-12x (7300) adapter in place
Xilinx Answer #760 : FPGA Configuration: XC4000E won't configure in socket designed for XC4000?
Xilinx Answer #761 : POWER.EXE may slow down PPR
Xilinx Answer #762 : EDIF2XNF error 6, "module.eds" not found in directory: possible causes
Xilinx Answer #763 : How to run XACTstep 6.0 from the CD; installation procedure (long)
Xilinx Answer #765 : "Extra" RAM Components in ViewLogic 4KE Libraries, no license found for symbol
Xilinx Answer #766 : How to delete a design viewpoint in Mentor 8
Xilinx Answer #767 : xnf2wir error 214: pin names for <component> do not match Viewlogic symbol
Xilinx Answer #768 : Gen_sch8/XBLXGS: ld.so: libeddm.so.1/libbase_lib.so.14: not found
Xilinx Answer #770 : Hardware Debugger: Only one signal can be selected at a time in a waveform window
Xilinx Answer #771 : Hardware Debugger: Crosshair cursor is invisible on a black background
Xilinx Answer #772 : Translate (& other DOS tools) hang if "Exclusive in Foreground" is checked.
Xilinx Answer #774 : XC5200: Mode pins M0, M1, M2 are bidirectional, but library MD0, MD1, MD2 are unidirectional.
Xilinx Answer #775 : runtime error R6018 - unexpected heap error
Xilinx Answer #776 : Design Manager: PC connected to Novell network hangs when running translate.
Xilinx Answer #777 : Virtex: Bypass Capacitors -- what are the requirements?
Xilinx Answer #778 : Benchmark. PPR runtime on various machines
Xilinx Answer #780 : MAKEBITS 5.2.X: length count differs due to new default -lc=aligned_lc
Xilinx Answer #782 : How can hold time violations occur when the data book states 0 ns hold times?
Xilinx Answer #783 : FLOW ENGINE 6.0: Hangs or freezes during a compile
Xilinx Answer #784 : Tutorial Example
Xilinx Answer #786 : Fncsim8/XBLXGS fails under Mentor B.x with "call to undefined procedure"
Xilinx Answer #787 : VST : component not found in library
Xilinx Answer #788 : **Obsolete Solution**: CPLD: Attribute Assignment: Using the LOC attribute for Function block and macrocell assignment (XEPLD v6.0)
Xilinx Answer #789 : How to simulate with Workview Office and XACTstep 6.0.1
Xilinx Answer #793 : Programmers: HW-130: Programmer does not accept .bit file format
Xilinx Answer #794 : XDE/EDIT LCA 5.2: INTERNAL PROGRAM ERROR (Please contact support personnel): bprog: 19,6: 10: not a pip
Xilinx Answer #796 : Hardware Debugger 6.0.1: Xchecker Cable Can't Be Detected or Readback Only Works Once
Xilinx Answer #798 : Retargeting a design in Mentor Design Architect (Convert Design)
Xilinx Answer #799 : A Possible Solution for the 'Smalltalk Error' when Design Manager 6.0 is Invoked
Xilinx Answer #800 : M1.5i/2.1i: Constraints: TNM's cannot be attached to tri-stated output flip flops (OFDT) via the TIMEGRP statement.
Xilinx Answer #802 : Running XACTStep 6.0 Design Manager on OS/2 is not possible
Xilinx Answer #805 : Design Manager 6.0 Smalltalk Error
Xilinx Answer #808 : XDM 5.x: XC3100A-09 not selectable, gives "-9 is not a valid speed grade"
Xilinx Answer #809 : How to select a pin on a symbol in PROcapture
Xilinx Answer #810 : XC3000: How to specify FGM mode in a schematic design using a CLBMAP
Xilinx Answer #813 : PROM File Formatter errors on 5202 only:unpadbs : HS round : frame 111 nframe 112 bit 2 of 4;
Xilinx Answer #816 : XACT 6.0 : Install - How can I setup XACT to run over a network?
Xilinx Answer #818 : Printing problems with PROcapture 6.1: Missing or greyed out lines
Xilinx Answer #819 : XC5200: Dedicated GCLK pins for I/O when using BUFGP
Xilinx Answer #821 : XC3000/XC4000/XC5200: xde in vesa16 mode requires 800x600x16 color support
Xilinx Answer #823 : Hardware Debugger 6.0.1: Groups cannot be used to create other groups.
Xilinx Answer #824 : Hardware Debugger 6.0.1: Groups w/ many signals may not be displayed properly in graphical waveform windows
Xilinx Answer #825 : Hardware Debugger 6.0.1: The Console becomes jumbled when it made too small.
Xilinx Answer #826 : Hardware Debugger 6.0.1: The Cable command Logic Level of Pins is not a continuous probe.
Xilinx Answer #827 : Hardware Debugger 6.0.1: A group cannot be deleted from the Signal Groups dialog.
Xilinx Answer #828 : Hardware Debugger 6.0.1: Nothing can be selected when viewing waveforms textually.
Xilinx Answer #829 : Hardware Debugger 6.0.1: A group cannot be modified using the Signal Groups dialog.
Xilinx Answer #830 : Hardware Debugger 6.0.1: Help will be disabled if the help file is located on a network drive.
Xilinx Answer #831 : Hardware Debugger 6.0.1: Printing graphical waveform using Landscape orientation does not rotate waveform.
Xilinx Answer #832 : Hardware Debugger 6.0.1: Once a signal or group is selected in a graphical waveform, it can't be unselected
Xilinx Answer #833 : Hardware Debugger 6.0.1: Double-clicking on close box in a window's title bar doesn't close the window
Xilinx Answer #834 : Hardware Debugger 6.0.1: Nets split during implementation are shown as split nets in available signals list
Xilinx Answer #835 : Hardware Debugger 6.0.1: Timeout After X Seconds option only for External triggers.
Xilinx Answer #836 : Hardware Debugger 6.0.1: Clicking No in Press enter to Start Readback dialog shows FailedReadback message
Xilinx Answer #837 : Hardware Debugger 6.0.1: Selecting File->Print without a printer installed gives an internal warning
Xilinx Answer #838 : Hardware Debugger 6.0.1: The Hardware Debugger can crash if too many waveform windows are opened at once
Xilinx Answer #839 : Hardware Debugger 6.0.1: Once a macro has been issued, there is no way to interrupt it.
Xilinx Answer #840 : Hardware Debugger 6.0.1: When a macro is saved, invalid macro commands are not flagged.
Xilinx Answer #841 : Hardware Debugger 6.0.1: Non-consecutive lines in the Console window cannot be selected using the CTRL key
Xilinx Answer #842 : Hardware Debugger 6.0.1: Printing only prints the currently displayed waveform portions.
Xilinx Answer #843 : Hardware Debugger 6.0.1: Clicking Run macro toolbar icon generates an error if a macro is not in focus.
Xilinx Answer #844 : Hardware Debugger 6.0.1: Console and macro windows cannot be printed from the Hardware Debugger.
Xilinx Answer #845 : Hardware Debugger 6.0.1: More than 500 snapshots will not be displayed.
Xilinx Answer #846 : Hardware Debugger 6.0.1: A readback text file (.rdb) of 0 bytes will be created if not enough disk space
Xilinx Answer #847 : Hardware Debugger 6.0.1: Textually saved waveforms cannot be re-opened into the Hardware Debugger.
Xilinx Answer #848 : Hardware Debugger 6.0.1: Cannot download using the Hardware Debugger if running from an executable CDROM.
Xilinx Answer #849 : Hardware Debugger 6.0.1: The Hardware Debugger cannot readback at 9600 baud on some machines.
Xilinx Answer #850 : Hardware Debugger 6.0.1: 1st readback may fail after a verify performed in the middle of several readbacks
Xilinx Answer #851 : Hardware Debugger 6.0.1: "Save Readback" in the File menu is de-activated when a waveform is iconized.
Xilinx Answer #852 : Hardware Debugger 6.0.1: Text waveforms cannot be printed from the Hardware Debugger.
Xilinx Answer #853 : Hardware Debugger 6.0.1: Help button in the New Group Name dialog does not invoke help.
Xilinx Answer #854 : Hardware Debugger 6.0.1: Hardware Debugger may issue an EMM386 error or hang on invocation.
Xilinx Answer #855 : Hardware Debugger 6.0.1: Only 3 characters show when displaying # of clocks applied before first snapshot
Xilinx Answer #856 : ProWave and ProSim: How to change system colors
Xilinx Answer #857 : Synopsys: XC5200: clock inversion is implemented in a function generator, not at the flip-flop.
Xilinx Answer #860 : XC4000E: 4025E pinout update for the MQ240, HQ240, and HQ304 packages
Xilinx Answer #864 : How to reach Viewlogic technical support.
Xilinx Answer #865 : How to contact OrCAD technical support: hotline, bbs numbers
Xilinx Answer #867 : Proflow changes the Viewdraw.ini file while using Pre-Unified Libraries
Xilinx Answer #868 : Differences between DS550 (EPLD) software versions 5.x and 6.0
Xilinx Answer #869 : CADENCE: How to contact technical support?
Xilinx Answer #872 : Workview: Viewdraw gives Pharlap error 33 when plotting
Xilinx Answer #874 : XC2000/XC3000/XC4000/XC52000: How to reach Chip Supply for dies, multi-chip module (MCM) information
Xilinx Answer #875 : VSMUPD: vsec: Error 8037: License node restriction does not match client's node for product ViewBASE
Xilinx Answer #880 : How to reach Commercial Documentation Services (CDS) & Viewlogic telesales for hard-copy manuals
Xilinx Answer #881 : Specifying an FDCE in VIEWsynthesis
Xilinx Answer #882 : MAKEPROM: INTERNAL PROGRAM ERROR when ran on a xc5200 device.
Xilinx Answer #883 : XCHECKER cannot pull the DONE pin LOW.
Xilinx Answer #885 : FPGA Configuration: Express Mode Bitstream loaded to the same pins as Peripheral Download.
Xilinx Answer #889 : MODELSIM VLOG (MTI): WARNING: [TSCALE] - Module '...' does not have a `timescale directive in effect, but previous modules do
Xilinx Answer #890 : In Windows 95, Prom File Formatter menus do not function correctly
Xilinx Answer #893 : QuickSim/Solaris: Could not load object file xxx.ss5_b, no such file or directory
Xilinx Answer #894 : Gen_sch8 5.x fails on Solaris with "crt1:bad open" or "libbase: can't open file"
Xilinx Answer #895 : XBLXGS 5.x fails on Solaris with "crt1:bad open" or "libbase: can't open file"
Xilinx Answer #897 : ProCapture Error when printing : vlwp Metafile does not exist
Xilinx Answer #898 : check -p sdesign.1 fails because of invalid/overlapping nets
Xilinx Answer #902 : Information about running XACT 5.2.1/6.0.1 (with WVO) in Windows NT
Xilinx Answer #905 : Mentor/EDIF2XNF: purple LOC properties on PADs are lost, gold properties are fine
Xilinx Answer #906 : PPR Error #1173 fplan.p file cannot be found when PPR is Run From FloorPlanner.
Xilinx Answer #907 : XC5200: Minimum pulse width on PROGRAM to reconfigure a 5200 device : 5k configuration
Xilinx Answer #908 : Design Manager 6.0: Design Manager doesn't start. Says "Not enough Memory"
Xilinx Answer #909 : NeoCad's compatibility with Solaris
Xilinx Answer #910 : Foundation 6.x: is there Windows 95, Windows NT, OS/2 support?
Xilinx Answer #912 : **Obsolete**Foundation HDL Editor: editor will not start
Xilinx Answer #913 : PLD_Men2XNF8 5.x: "test: unknown operator"
Xilinx Answer #914 : **Obsolete Solution**: Installing XABEL-CPLD Software Over A Network
Xilinx Answer #915 : PPR : Error 5606 : Unable to create output MXN or PIC cell.
Xilinx Answer #917 : Design Manager: Unhandled exception, invalid file name, PCFilename class
Xilinx Answer #921 : FLOORPLANNER-XACT: Unable to load fplan.pm occurs when opening the Floorplanner.
Xilinx Answer #922 : WIR2XNF error: could not find WIR file for a user-created component
Xilinx Answer #926 : Programmers: HW-130: Installation and Debugging tips (PC platforms)
Xilinx Answer #928 : PPR, XNFPREP: INIT=S property ignored because INIT converted to "init"
Xilinx Answer #930 : Programmers: Data I/O: Checksums on Data I/O programmers may not match when doing a "load" and doing a "read"
Xilinx Answer #934 : 94 DATA BOOK 3rd: Solder pad layout for PQ160 package on page 4-2 shows an incorrect I2 dimension
Xilinx Answer #939 : Foundation Simulator: macro outputs always 'Z' during simulation
Xilinx Answer #940 : JTAG - How to configure a XC4000/XC5200/Spartan families via Boundary Scan
Xilinx Answer #941 : JTAG - Consecutive readbacks via the JTAG interface in the XC4000/XC5200/Spartan devices
Xilinx Answer #942 : XNFPREP error 3527: possible causes if using Foundation
Xilinx Answer #943 : Hardware Debugger 6.0.1: Verification yields "Part type "?" is not defined in 'partlist.xct'
Xilinx Answer #945 : PPR 5.20: Support for dual phase clocks in 3000A devices
Xilinx Answer #946 : WIN32S problems after installing Foundation (win32s v1.30a) - OE20.EXE, unexpected DOS error 21
Xilinx Answer #947 : NC-VERILOG: How to back annotate the SDF file for timing simulation?
Xilinx Answer #948 : SYNPLIFY: "Net work.ibtpu(behavior)-o_c_c has mixed driver types" when using Virtex pullups/pulldowns
Xilinx Answer #949 : XC5200: Slew rates (RISE and FALL times) for outputs with a 50 pF load
Xilinx Answer #952 : PPR: Guidelines for using manually edited LCAs as PPR guide files
Xilinx Answer #954 : Foundation XVHDL, F6.x: Instantiating I/O buffers causes XNFPREP error 3530
Xilinx Answer #955 : ** OBSOLETE ** VERILOG-XL: 4000E setup/hold violations on WCLK
Xilinx Answer #960 : MAKEBITS, MAKEPROM v5.2: bit file and prom file size may differ from that generated with v5.1/5.0 software.
Xilinx Answer #961 : Programmers: HW-130: Are the HW-120 adapters compatible with the HW-130 Programmer?
Xilinx Answer #964 : XChecker 5.2.1: Downloading a valid bitstream in DOS produces a frame error - INIT goes low
Xilinx Answer #965 : Place & Route in Flow Engine produces PPR error 5603: "Unable to open .xtf file"
Xilinx Answer #966 : Hardware Debugger 6.0.1: Error Message: Cannot find TEMP directory
Xilinx Answer #969 : XSIMMAKE: Check.exe fails while using the simulation utility in Windows.
Xilinx Answer #970 : Defining pin attributes/locations for a VHDL code using Viewsynthesis
Xilinx Answer #973 : How to specify a BUFGP vs. BUFGS using Viewsynthesis?
Xilinx Answer #974 : ** OBSOLETE ** XNFPREP 5.20: changes "INIT=S" to lower case "init=S", which PPR 5.20 ignores
Xilinx Answer #977 : FLOORPLANNER-XACT: Unable to load file <design>.lca / FPLAN : ERROR 1576 : Error in LCA file
Xilinx Answer #979 : 94 DATA BOOK 3rd: PQ100 package dimensions on page 4-10
Xilinx Answer #980 : Foundation: BTRIEVE error messages reported in Project Manager message window
Xilinx Answer #982 : Error 1140: the design contains X unresolved references
Xilinx Answer #983 : CPLD: XC9500/XL: How to set FAST slew rate for 9K outputs in PLUSASM and ABEL?
Xilinx Answer #984 : Foundation: VHDL entry option is not selectable
Xilinx Answer #986 : Foundation: How to delete a component from a user library
Xilinx Answer #989 : XCHECKER 5.2.1: Files required for standalone XChecker software (PC or Workstation).
Xilinx Answer #992 : XC5200 JTAG - Sample/Preload in a XC5200 appears to work like BYPASS
Xilinx Answer #993 : JTAG - /PROGRAM held low in FPGA's limits boundary scan instruction set
Xilinx Answer #994 : Foundation: Improper Netlist error while loading functional simulation
Xilinx Answer #997 : Using XACT 5.2.1 with Mentor Graphics' B.x release
Xilinx Answer #998 : XC7300F electrical characteristics
Xilinx Answer #1004 : **Obsolete Solution**: Programmers: HW-130: The 7372 is non-functional if the security bit is programmed
Xilinx Answer #1005 : When items are selected in Procapture, selected color is the opposite color.
Xilinx Answer #1006 : Programmers: HW-130: "Device Manufacturer code error"
Xilinx Answer #1010 : Timsim8/PLD_DVE_BA gives "Delete operation on object failed"
Xilinx Answer #1011 : PPR issues error 9025 on 5k design; FPLAN finds no errors
Xilinx Answer #1012 : WVOffice: while printing a project, the printouts are fuzzy
Xilinx Answer #1013 : Gen_sch8 error: Bad status 79501087 from ddp__add_instance
Xilinx Answer #1014 : Design Manager/Flow Engine 6.0.1: A guide file specified in the Advanced menu may not be used/implemented
Xilinx Answer #1016 : Using MakeTNM and addTNM in order to add TNMS to a .XNF file.
Xilinx Answer #1017 : Designing with the XC5200 family using synthesis
Xilinx Answer #1022 : Quicksim II: No-connects appear on Fncsim8-created schematic containing XBLOX
Xilinx Answer #1023 : PROMS: Atmel EEPROM: Is the Atmel prom compatible with Xilinx 1700 series?
Xilinx Answer #1024 : Selecting New Device in Design manager give Unhandled Exception Error. Message not understood
Xilinx Answer #1027 : Foundation Simulator: PRINT command described incorrectly in documentation
Xilinx Answer #1028 : Foundation HDL Editor: Compiling an ABEL file as a stand-alone CPLD design.
Xilinx Answer #1029 : Programmers: HW-130: ERROR - Reset not programmed.
Xilinx Answer #1031 : Xchecker cannot be used in place of NeoCad download cable in Foundry environment
Xilinx Answer #1033 : XC3000: Place Block syntax for APR is different than for PPR, results in APR Error 213.
Xilinx Answer #1034 : **Obsolete**Foundation: SC Symbols list is empty when adding a component in Schematic Capture
Xilinx Answer #1036 : CPLD: ABEL: Controlling Global Net Utilization for 9500 designs with XABEL-CPLD
Xilinx Answer #1037 : ProCapture will not open up when selecting Design Entry from Proflow
Xilinx Answer #1038 : **Obsolete Solution**: XABEL-CPLD: Possible cause of General Prot. Faults, and being disconnected from Internet/network
Xilinx Answer #1040 : What are VCC_BUS and VSS_BUS pins
Xilinx Answer #1041 : Design Manager 6.0.x: Unhandled exception, xact raw binary interface error
Xilinx Answer #1043 : Foundation: Possible causes of XNFMERGE Warning 285
Xilinx Answer #1045 : Foundation Simulator: XC7300/XC9500 flip-flop outputs unknown (PRLD signal)
Xilinx Answer #1047 : **Obsolete Solution**: XACT-CPLD: hi12:[Error]Keyword MC9500_PTERM_LIMIT in the CTL file is invalid.
Xilinx Answer #1050 : Designing with the XC9500 family in Mentor (XACT 5.2.x)
Xilinx Answer #1051 : XNFPREP: Error 3526: Illegally inverted pin with XBLOX SYNC_RAM symbol
Xilinx Answer #1052 : Design Manager 6.0.x: runtime 6008 not enough space for arguments
Xilinx Answer #1054 : design manager : translate general protection fault Wir2xnf TNT 11020
Xilinx Answer #1056 : Foundation: How to move a project around
Xilinx Answer #1058 : **Obsolete Solution**: XACT-CPLD: 9500: Creating Programmable Ground Pins in XC9500 Designs
Xilinx Answer #1059 : XNF Specification v6.1 is now available on ftp, including XC7000 supplement
Xilinx Answer #1061 : SYNPLIFY: How is the top level module or entity/architecture determined?
Xilinx Answer #1062 : Procapture: SECURITY no valid license for product: ProSeries
Xilinx Answer #1063 : **Obsolete**Foundation: Key stops working on BAS and BSV packages
Xilinx Answer #1065 : XC3000/XC4000/XC5200: How to select cmos input thresholds for FPGAs
Xilinx Answer #1066 : XBLOX 5.x: ONE_HOT COUNTER with unconnected UP/DN pin results in DOWN counter
Xilinx Answer #1067 : FPGA/CPLD/PROM: Markings: What are the Device/Package Markings for Xilinx Devices?
Xilinx Answer #1068 : Foundation: Importing a Viewlogic design with a user library
Xilinx Answer #1069 : How to specify TIMESPECs
Xilinx Answer #1070 : SPROMS: XC1700D: What is the SPROM input capacitance value?
Xilinx Answer #1071 : XACTstep Libraries Guide: TS identifier in Mentor NOT limited to 01, 02, etc.
Xilinx Answer #1072 : Fast outputs versus fast slew rate outputs in Xilinx devices
Xilinx Answer #1073 : PAR: "Number of GCLKS 5 out of 4" with Virtex Synplify netlist
Xilinx Answer #1074 : Timsim8: "return code 1" from segmentation fault under Solaris
Xilinx Answer #1075 : wir2xnf gives error 4 when using Powerview 6.0 (iwinit failure), need lsclient daemon
Xilinx Answer #1076 : Quicksim II: Obsolete-library RAMs and ROMs output X's in XACT 5.2
Xilinx Answer #1078 : MODELSIM VLOG (MTI): Running Verilog simulation
Xilinx Answer #1080 : EZTAG: When programming, gives message "Bad command or file name."
Xilinx Answer #1081 : **Obsolete Solution**: Programmers: EZTAG: Can't find file "other.bsd" when programming chain of 9500's
Xilinx Answer #1082 : EZTAG: Causes of Program and Erase problems
Xilinx Answer #1083 : Xchecker cable is not connected correctly - Invalid port name
Xilinx Answer #1085 : LCA2XNF may use unit delays (functional) in timing simulation flow
Xilinx Answer #1089 : VERILOG-XL: Specifying multiple libraries in a Verilog simulation
Xilinx Answer #1091 : VCS: Error: undefined hierarchical reference "glbl.GSR" (<design>.v line ####)
Xilinx Answer #1092 : PQ44 package dimensions incorrect in 1994 Data Book
Xilinx Answer #1095 : Xchecker Cable: Can the Xchecker cable be used to program via JTAG Programming? Where is TDO?
Xilinx Answer #1097 : The DOS based XCHECKER software may not run over a NOVELL network.
Xilinx Answer #1098 : M1: Powerview: User-owned directory/files may be created in Xilinx tree
Xilinx Answer #1100 : XC4000E: What is state of RAMs upon power-up/configuration?
Xilinx Answer #1101 : Men2XNF8/ENWrite error: "Pin does not map to a net in model" due to incorrect COMPMC16 macro
Xilinx Answer #1102 : How to use PROflow with the 4000e family.
Xilinx Answer #1104 : MAKEBITS TIE--Should all designs be tied?
Xilinx Answer #1109 : 96 DATA BOOK: 4025ehq208 not found in partlist.xct
Xilinx Answer #1111 : XC5200: Dynamic power consumption values (most up-to-date)
Xilinx Answer #1112 : XC5200: Typo reads "50-kW to 100-kW pull-up resistor" in 'The Programmable Logic Data Book', 7/96
Xilinx Answer #1113 : **CPLD : 9500 : Programmer: EZTAG: Errors 1020, 1019: While programming 9500 device with Xchecker cable
Xilinx Answer #1117 : XC4000: XACT 5.2- MEMWIN / Memory Generator does not support Dual Port RAMs
Xilinx Answer #1118 : Foundation XVHDL: Synthesis of VHDL causes message: No entity selected.
Xilinx Answer #1119 : SPROMS: HW-112: What is the HW-112 programmer support for 1700L?
Xilinx Answer #1122 : **Obsolete Solution**: SPROMS: 1736: The 1736 device is not available as an L (low power) part.
Xilinx Answer #1124 : Viewlogic: Do NOT use $ARRAY in Xilinx designs
Xilinx Answer #1125 : **Obsolete**Foundation install hangs at "searching for XACT environment"
Xilinx Answer #1127 : SYNOPSYS: The entity .. depends on the package std_logic_arith. Reanalyze the source
Xilinx Answer #1128 : Problems after installing Xact 6.0.1 (Win32s v1.30a) - OE20.EXE, unexpected DOS error 21
Xilinx Answer #1132 : **Obsolete**Foundation Simulator: 'Invalid chip descriptor' error while loading netlist
Xilinx Answer #1133 : XNF2INF Error-008: An invalid parttype "52xx" was specified in the XNF file
Xilinx Answer #1134 : FLOORPLANNER-XACT: Unable to invoke the floorplanner from the Design Manager
Xilinx Answer #1135 : PROsim error: Could not find wir file xc5200:osc52.1
Xilinx Answer #1138 : Amount of memory that is required by XACT/XDE 5.2.1
Xilinx Answer #1139 : Workview Office 7.1.2 is the only version that is compatible with Windows 3.11
Xilinx Answer #1140 : Programmers: EZTAG: How to turn off Data Protection (DP) for the 9500 in EZTAG?
Xilinx Answer #1141 : XSIMMAKE creates schematic symbols with double bounded bus pins.
Xilinx Answer #1142 : install XACT 5.2.1 on Sparc: /cdrom/scripts/check_os.csh: Permission denied.
Xilinx Answer #1144 : **Obsolete Solution**: Programmers: HW-130: Can't find programmer or system crash problem on Toshiba laptops
Xilinx Answer #1146 : **Obsolete Solution**: DATA BOOK: 1994 3rd Edition: Error in boundary scan order for 4010 BG255 on page 2-62
Xilinx Answer #1150 : Design Manager/Flow Engine: BlackBoxes appear instead of Characters
Xilinx Answer #1151 : Design Manager: System Error, Unhandled Exception: ERROR_FILE_NOT_FOUND
Xilinx Answer #1153 : PPR: ERROR 1173: the file \path\dsn.lca associated with the LCA cell \path\dsn could not be found.
Xilinx Answer #1154 : PPR 5.2: Error 5814: Constraint file block name '[name]' could not be found in net list
Xilinx Answer #1155 : Foundation: Pins on Abel symbol not matched to any signal in <abel_file>.xnf
Xilinx Answer #1156 : LogiCORE PCI: Does it support Big or Little Endians?
Xilinx Answer #1157 : Powerview 6.0 has a different default VSM option, requires new file
Xilinx Answer #1159 : XEPLD 6.0.1: vm2006:Internal Error and - invalid ID] when taegine is run
Xilinx Answer #1161 : Workview Office, PCI v1.1: Simulation fails if using unit delays only.
Xilinx Answer #1162 : FPGA/CPLD: Boundary Scan: Where do you get BSDL files for the Xilinx FPGAs and CPLDs?
Xilinx Answer #1163 : "Can't open display" error when invoking install and other programs with graphical interfaces
Xilinx Answer #1164 : **Obsolete Solution**: PROGRAMMERS: Data I/O: Algorithms are currently not qualified
Xilinx Answer #1165 : XPP, HW-112: XPP v5.2.0 does not recognize 4020EHQ240 .bit file
Xilinx Answer #1166 : XSI Libraries: Synopsys libraries (pre- A2.1i) analyzed for older versions of Synopsys
Xilinx Answer #1167 : XABEL: AHDL2X will hang at "processing equations..." with wide buses.
Xilinx Answer #1169 : Design Manager: Visual Works v2.0 Fatal Error Out of Memory
Xilinx Answer #1172 : JTAG - What is the bit order of the Instruction Register in Xilinx FPGA's
Xilinx Answer #1174 : JTAG - Mandatory instructions defined by IEEE standard 1149.1
Xilinx Answer #1175 : XABEL: Xt Warning: ...Couldn't open file xmain.uid - MrmNOT_FOUND
Xilinx Answer #1179 : SPROMS: Checksums: What are the PROM file and programmer checksums?
Xilinx Answer #1180 : **Obsolete Solution**: XACT-CPLD : An unrecognized Symbol Type 'NOR7' was found in netlist
Xilinx Answer #1181 : Proflow : DOS error #53 : Can't open file.
Xilinx Answer #1182 : procapture dos error #75 occurred: access denied...
Xilinx Answer #1183 : Proflow : Project Verification Error
Xilinx Answer #1184 : **Obsolete**Foundation Timing simulation : BAX file <design> does not exist XACT6 Design Manager process ?
Xilinx Answer #1185 : PPR 5.2.0: ERROR 1582: Error in writing LCA data to memory:
Xilinx Answer #1186 : XNF2WIR ERROR 217: The logical function of <component> and its Viewlogic model do not match.
Xilinx Answer #1187 : XNFPREP failes due to capital letters in filename
Xilinx Answer #1188 : BOUNDARY SCAN/JTAG: Timing Parameters (rise time, fall time, max frequency) for TMS,TCK, and TDI
Xilinx Answer #1189 : Analyzing the Synopsys Designware and Simulation Libraries for M1 and XACT 5.2.1
Xilinx Answer #1190 : **Obsolete Solution**: XC7300 : How to force a wired-AND function into the UIM in Xabel-CPLD
Xilinx Answer #1191 : PPR 5.2.x: abnormal program termination: memory protection fault in Windows95 (Win 95)
Xilinx Answer #1192 : EZTAG: INTERNAL ERROR: condition 'returned ==....at line '4046' in file 'rcab.c'
Xilinx Answer #1193 : WIR2XNF:Error-V (version) statement not unique, out of order or missing
Xilinx Answer #1195 : Xchecker Cable: What is the CCLK circuitry in the Xchecker cable?
Xilinx Answer #1196 : XC3000: XACT 6.0.x/5.2.x- Unable to target 3090(A, L) or 3190(A, L) TQ144 device
Xilinx Answer #1197 : How to access the Xilinx Customer Download area on our FTP site
Xilinx Answer #1198 : How to access the Xilinx anonymous FTP site
Xilinx Answer #1199 : LCA2XNF: Warning:23 pins do not have routing delays, PPR shows 0 unroutes
Xilinx Answer #1201 : Synopsys, XACT: What is the latest version of XBLOXGEN?/Where to get XBLOXGEN?
Xilinx Answer #1202 : 96 DATA BOOK: The 4020EHQ240 has 192 user IOs, not 193 as shown on p4-176
Xilinx Answer #1203 : 5200 VL libs : FJKRSE or FJKSRE does not function properly
Xilinx Answer #1206 : NEC VersaGlide Mouse driver causes Flow Engine to crash (Fatal exception at 0D)
Xilinx Answer #1207 : What is the latest version of addtnm and maketnm? Where to get addtnm and maketnm?
Xilinx Answer #1209 : ** OBSOLETE ** CADENCE: How the Cadence/Xilinx schematic Interface software is obtained (DS-CDN, DS-381)
Xilinx Answer #1210 : Possible cause of XNFPREP 3527 :"Pad connected to invalid symbol pins"
Xilinx Answer #1211 : JTAG - How to get the `Scan Educator' tool from TI's website for a basic understanding of JTAG
Xilinx Answer #1212 : Workstation Install: How to Install software for a specific platform
Xilinx Answer #1213 : WORKSTATION INSTALL: Translation table syntax errors (XkeysymDB)
Xilinx Answer #1215 : JTAG - When is Boundary Scan available for use in the XC4000 based families?
Xilinx Answer #1217 : Viewsim: backannotation from Viewsim/Viewtrace to Viewdraw doesn't work
Xilinx Answer #1219 : JTAG - Is the routing used by the XC4000/XC5200 TAP pins visible in XDE, EPIC, or FPGA Editor?
Xilinx Answer #1220 : JTAG - How to 'turn on' jtag circuitry via XDE and EPIC for XC4K/XC5K devices
Xilinx Answer #1221 : Timing Analyzer 6.0.1: Won't save reports to an .xrp file in Windows 95.
Xilinx Answer #1224 : Reading an Ocad 386+ design into Orcad Capture 7.0 for windows
Xilinx Answer #1225 : How to re-target a different Xilinx device family with Viewlogic's Altran
Xilinx Answer #1226 : PACKAGES: Information on calculating Temperature/Thermal Characteristics (Theta-JA)
Xilinx Answer #1227 : Template Manager M1/XACT : How to specify options not available in the options menu of Design Manager
Xilinx Answer #1229 : LogiCORE PCI32 4000/Spartan: Should i/o's be set to TTL or CMOS for the 4KXLT or Spartan device?
Xilinx Answer #1233 : CPLD: 9500 BSDL File: Syntax pin_map_string pin description and FPGA pin_map_string description
Xilinx Answer #1235 : Design Manager M1: Translate hangs while attempting to read in a netlist file
Xilinx Answer #1236 : **Obsolete**Foundation: BTRIEVE 1002 or memory allocation error on XC4000E project
Xilinx Answer #1237 : Xchecker 5.2.1: Partlist.xct from xact\data directory is used for downloading instead of xpart.def
Xilinx Answer #1238 : Logitech Mouse driver causes Translate to Hang
Xilinx Answer #1239 : Xsimmake (5.2.x) patch needed for Workview Office (Windows 95 and NT)
Xilinx Answer #1240 : XKEY 5.2 under Windows 3.11 does not see the key, but works fine under DOS.
Xilinx Answer #1241 : Foundation: How long can Net Names and Pin Names be?
Xilinx Answer #1242 : LogiCORE PCI: Does the XC4000E meet capacitance and inductance specs for PCI?
Xilinx Answer #1243 : Flow Engine 6.0.1: DOS 16m error - protected mode requires VCPI within virtual 8086
Xilinx Answer #1244 : PROsim or ViewSim: Outputs of ROM primitives are 'x' (indeterminant state).
Xilinx Answer #1245 : Gen_sch8 fails under Mentor B.x with "Unresolved Propagate symbol"
Xilinx Answer #1246 : Fncsim8/XBLXGS fails under Mentor B.x with "Unresolved Propagate symbol"
Xilinx Answer #1247 : patch for Flex/LM errors with xsimmake/check in Workview Office 7.2 (Error 8034)
Xilinx Answer #1252 : NGD2VER: The PC path is not being interpreted correctly in the 'uselib and 'include statements
Xilinx Answer #1253 : Viewlogic: How do I LOC an IPAD4/8/16 or an OPAD4/8/16 ?
Xilinx Answer #1256 : Foundation HDL Editor: "Unhandled Exception" during VHDL synthesis
Xilinx Answer #1258 : Foundry7.0 for PC runs w/ Windows NT; ssetup may yield "device not attached"
Xilinx Answer #1260 : **Obsolete Solution**: Programmers: Data I/O: These programmers have been re-qualified to program Xilinx XC1700 serial PROMs
Xilinx Answer #1262 : Quicksim II: Could not find a registered simulation model, NULL model will be inserted
Xilinx Answer #1264 : PROcapture: "Pin/Net disassociation at location ..."
Xilinx Answer #1265 : PPR 5.x: ERROR 5812
Xilinx Answer #1266 : **Obsolete Solution**: Programmers: HW-130: Verification Failure For a 17128D and 17256D
Xilinx Answer #1269 : XC4000E: MEMGEN always uses the part 4005EPG156 for Synchronous Rams.
Xilinx Answer #1270 : **XACT-CPLD: Using a guide (.GYD) file to define pin constraints for CPLDs
Xilinx Answer #1272 : Cable - How many devices can Parallel III (JTAG) cable program in a chain?
Xilinx Answer #1273 : Check, Procapture, viewdraw: Schematic components cannot be found.
Xilinx Answer #1278 : SPROMS: File formats: What is the maximum capacities for Tektronix, Motorola EXORmacs, and Intel MCS formats?
Xilinx Answer #1279 : JTAG - Does data appear on TDO and DOUT during JTAG configuration of 4k/5k/Spartan families?
Xilinx Answer #1282 : CPLD: XC9500: Pull-ups in IOB should pull up to VccIO, not VccINT as Data Book shows
Xilinx Answer #1283 : Viewsynthesis: Symbol precompiled_xc3000:FDPE cannot be found
Xilinx Answer #1286 : Foundation Simulator: simulating bi-directional signals
Xilinx Answer #1287 : XBLOX 5.x: Internal error 20224: representation_error
Xilinx Answer #1289 : Synopsys : How to use OSC5, OSC52, and CK_DIV Cells from the XC5200 Synthesys Libraries
Xilinx Answer #1291 : Foundation: Keylock (Sentinel driver) must be upgraded after an upgrade from Win3.1 to Win95
Xilinx Answer #1293 : XC5200: UserClk must be enabled in Makebits before CK_DIV will be used.
Xilinx Answer #1294 : XC5200: 5200 schematic libraries contain 'BUFGP' and 'BUFGS' symbols
Xilinx Answer #1295 : BIDIRectional IOs with Viewsynthesis
Xilinx Answer #1297 : Xchecker: How can I use it on low-power "L" 3.3V parts?
Xilinx Answer #1301 : XC5200: Programmable keeper cells are automatically enabled when all buffers are in 3-state mode
Xilinx Answer #1302 : CONCEPT2XIL: "Architecture not found" errors
Xilinx Answer #1303 : XNFPREP 5.2.x: ERROR 3582 issued because XC5200 does not have IOB registers
Xilinx Answer #1304 : Foundation/XABEL: "Synthesis Failed" when synthesizing ABEL file.
Xilinx Answer #1305 : XC5200: BUFG - different skew between clock pin and non clock pin.
Xilinx Answer #1306 : VHDL synthesis : tristate multiplexer versus combinatorial multiplexer.
Xilinx Answer #1308 : CPLD: XC9500: How many outputs can you simultaneously drive at 24 mA?
Xilinx Answer #1309 : Design Manager : Cannot find data file "xc9500.bos" in the XACT path.
Xilinx Answer #1310 : The HW-112 Programmer is also known as the PP2
Xilinx Answer #1311 : men2xnf8/enwrite: Pin mapping from part interface to superseding interface not possible
Xilinx Answer #1312 : XC3000/XC4000/XC5200: PAR ERROR 4kpl:7 - Too many TBUFs (TRISTATEs) driving longline
Xilinx Answer #1313 : Why does Flow Engine run the XBLOX program on my non-XBLOX design?
Xilinx Answer #1315 : XDRAW/Xsimmake: Invalid KeyWord 'WINDOW_BACKGROUND'
Xilinx Answer #1317 : F1.4, F1.5 Simulator: Saving simulation probes and I/O signals
Xilinx Answer #1318 : SPROMS: Markings: 1700 and 1700D/L package marking interpretation
Xilinx Answer #1319 : M1: EDIF2NGD doesn't recognize the parttype from a Viewlogic EDIF file.
Xilinx Answer #1320 : M1: EDIF2NGD: WARNING:0 - GLOBAL property on a net other than power or ground
Xilinx Answer #1321 : Design Manager reports: xmake is inaccessable
Xilinx Answer #1322 : Hardware debugger: Incorrect cable specification given.
Xilinx Answer #1323 : FPGA Express: What Xilinx software is needed if FPGA Express is the design entry tool
Xilinx Answer #1325 : FPGA Express: Cannot find type information (.typ) for IEEE.STD_LOGIC_1164.STD_LOGIC (HDL-353)
Xilinx Answer #1330 : SPROMS: PROM FILE FORMATTER: How to format large daisy-chained bitstreams for XChecker
Xilinx Answer #1331 : How to add XACT-Performance (Timespec) constraints to my CST file
Xilinx Answer #1332 : How to access the Xilinx anonymous FTP site with the IP address
Xilinx Answer #1334 : ProCapture displays CB4CLED.1 symbol pins 'D0' and 'Q0' as diagonals
Xilinx Answer #1337 : SYNPLIFY: How to apply the DRIVE property using the xc_props attribute?
Xilinx Answer #1342 : Foundation: XC4000 CD4CLE macro counts independent of clock enable
Xilinx Answer #1343 : OrCAD Capture 6.x: How to import an ABEL file in Capture?
Xilinx Answer #1344 : XC4000: XDE- editlca: find RxCx returns the wrong block in 4013(E) - 4025(E)
Xilinx Answer #1346 : XNFMERGE: Warning Unrecognized Property 'HDL_SOURCE' on symbol 'sym_name'
Xilinx Answer #1347 : Can Xilinx Devices be wave soldered or immersed in solder?
Xilinx Answer #1349 : XABEL: How to assign preload value to registers in an EPLD
Xilinx Answer #1350 : XABEL: How to assign set/reset preload values to registers in an FPGA
Xilinx Answer #1351 : XC4000/E: How to install the 4025 and 4025E data files for the XACT 5.2.1/6.0.1 software from the CD-ROM (workstation and PC)
Xilinx Answer #1353 : Design Manager: Rhdexec.dat does not exist
Xilinx Answer #1354 : My CBxxx counter is not fast enough for my design
Xilinx Answer #1355 : Foundation: Can't print schematics to network printer under Windows 95
Xilinx Answer #1356 : JTAG - Can TDI, TCK, TMS and TDO be connected to a user signal and BSCAN?
Xilinx Answer #1358 : JTAG - How to attach a pullup or pulldown resistor on the 4K TDO pin?
Xilinx Answer #1359 : JTAG - Pullup and pulldown availability on 5200 TDO
Xilinx Answer #1360 : Error message when running XACT 6.0 on a network when translating
Xilinx Answer #1361 : XDM, XDE: Cannot select XDE from XDM with a XC5200 part
Xilinx Answer #1362 : Foundation XVHDL, JTAG: How to instantiate the BSCAN symbol for Boundary Scan
Xilinx Answer #1363 : Will a Pentium Pro or MMX instruction (P6) speed up Xilinx software?
Xilinx Answer #1366 : Foundation XVHDL: Using pullups and pulldowns
Xilinx Answer #1367 : **Obsolete Solution**: CPLD: XC9500: What is the JTAG app note is being refered to on page 3-14 of the 7/96 Databook?
Xilinx Answer #1368 : How to submit a file on the Xilinx Customer Upload area on our FTP site
Xilinx Answer #1369 : LogiCORE PCI: Information on pipelining signals in PCI designs
Xilinx Answer #1370 : How do I set the graphics mode in XDE (editLCA) for DOS?
Xilinx Answer #1372 : Foundation XVHDL: How to lock down I/O pins
Xilinx Answer #1373 : Foundation XVHDL: How to use I/O Flip-Flops
Xilinx Answer #1374 : Foundation XVHDL: How to use Bidirectional I/O
Xilinx Answer #1375 : Foundation XVHDL: Using Global Buffers
Xilinx Answer #1376 : Foundation XVHDL: Using Global Set/Reset and STARTUP
Xilinx Answer #1377 : Foundation XVHDL: How to specify FAST Slew rate
Xilinx Answer #1379 : OrCAD Capture 7.0: Error CAP0044 empty pin number has been created for pin xx
Xilinx Answer #1380 : Configuration takes a long time.
Xilinx Answer #1381 : Workview Office: use VCD format with ViewTrace; fixes bad clock pulses in simulation
Xilinx Answer #1382 : PPR/Foundation: Duplicate name errors when guiding designs entered in Foundation
Xilinx Answer #1385 : XCHECKER 5.2.1: Error 265 : INIT signal is low.
Xilinx Answer #1386 : W/S License Manager: Why is there a feature line for VIEWLOGIC?
Xilinx Answer #1388 : XABEL/FOUNDATION: What is needed to compile a design containing XABEL blocks
Xilinx Answer #1389 : Xsimmake, Workview Office: Using Workview Office 7.1.2 or 7.2 with XACTstep 6.0.1 (Xsimmake failed)
Xilinx Answer #1390 : Operational level of voltage/current on FPGA inputs
Xilinx Answer #1391 : INSTALL: Hard Drive missing in the drive Status of the Set Path windows
Xilinx Answer #1393 : XEPLD Optimize: Unexpected error: epldinst.cc:40
Xilinx Answer #1394 : Workview Office: License exclusive restriction errors (1055, 8031, 8051)
Xilinx Answer #1396 : Foundation: Can you put LOCs on IPAD4/8/16 or OPAD4/8/16?
Xilinx Answer #1397 : CONCEPT: How to attach LOC properties to IPAD4/8/16 & OPAD4/8/16 macors
Xilinx Answer #1399 : XC5200: Recommended maximum sink and source currents
Xilinx Answer #1400 : CPLD: XC9536 Does not have local feedback paths
Xilinx Answer #1402 : XChecker: "Done did not go high" for 5200 download.
Xilinx Answer #1403 : XC9500/XC7000: Translate warning 295: The LOC parameter 'LOC=FB1_16' on the macro symbol $1I1 is not supported for XC7000 designs
Xilinx Answer #1405 : DATABOOK 1996 Edition: Ambiguity regarding PG299 pins E5, E16, T5 and T16
Xilinx Answer #1408 : CPLD: XC9500/XL: What should be done with unused JTAG pins in the XC9500/XL?
Xilinx Answer #1410 : Orcad SDT2XNF: Does it support Windows 95 and NT?
Xilinx Answer #1411 : OSC4.vli is not included in the XC4000E unified library.
Xilinx Answer #1415 : **Obsolete Solution**: Programmers: HW-130: PROLINK/HW-120: Manufacturer and product code / product i.d. errors on 7300 devices
Xilinx Answer #1416 : CHECK or XNFPREP fail because of invalid characters in signal names
Xilinx Answer #1417 : Programmers: HW-130: Are the HW-112 (PP2) adapters compatible with the HW-130 Programmer?
Xilinx Answer #1418 : FLOORPLANNER-XACT: ATI video driver may cause general protection fault
Xilinx Answer #1419 : PPR error 5812 - Constraint file error
Xilinx Answer #1420 : SPROMS: Can the VPP/VCC pin be tied through a resistor to +5V?
Xilinx Answer #1423 : XC3000/XC4000: Are the internal tri-state busses(3k,4k) PULLED Up by default?
Xilinx Answer #1424 : Programmers: Data I/O: Unisite Programmers issue "Partial Write Not Supported" error on 1700 devices
Xilinx Answer #1426 : Orcad VST all outputs are undefined
Xilinx Answer #1428 : FPGA Configuration: CCLK does not toggle in master mode.
Xilinx Answer #1429 : Workview Office: What Workview Office products should I install for a Xilinx restricted license? (OEM1/OEM2)
Xilinx Answer #1430 : ORCAD: DS32-VST-ERROR-030, symbol has incomplete pin information.
Xilinx Answer #1431 : ORCAD: Xnfprep trims ground and power signals from Orcad Capture
Xilinx Answer #1432 : HARDWARE DEBUGGER: Many internal signals cannot be selected
Xilinx Answer #1435 : Invoking XDM requires to be logged in as root
Xilinx Answer #1437 : OrCAD Capture 7.0: Fails to create xnf file
Xilinx Answer #1439 : XC73144: How to configure programmable ground option
Xilinx Answer #1440 : PROCapture 6.1: Can I print entire design and change fonts before printing?
Xilinx Answer #1441 : Timsim8 ends with return code 100 (XNFBA error 256) on non-Mentor XBLOX design
Xilinx Answer #1442 : XEPLD 6.x: Unexpected error detected, please report to Xilinx with reference "epldinst.cc40."
Xilinx Answer #1444 : Workview Office gives "Error" but no error message. (WVOinstall info)
Xilinx Answer #1445 : Viewsynthesis: STARTUP instantiation
Xilinx Answer #1447 : xnf2wir/xsimmake: General Protection Fault on Windows95.
Xilinx Answer #1449 : Possible Solution for Unexpected Error Detected. Reference writepif.cc: 871
Xilinx Answer #1450 : UNISIMS: The pin names for VCC and GND have changed to P and G
Xilinx Answer #1451 : How to run Viewsynthesis from DOS
Xilinx Answer #1453 : XC7336/XC7318: "Drive Unused IO Pads on Chip" option not available for 7336, 7318
Xilinx Answer #1454 : XC5200: LCA2XNF v5.2.1 writes out 5-input logic gates for XC5200
Xilinx Answer #1455 : XACT/SYNOPSYS: XSI 5.2.1 .db files for synthesizing 5210-4, 5215-5, and 5215-6
Xilinx Answer #1456 : HardWire: XNFRPT -I
Xilinx Answer #1458 : Synopsys: Where can I get a list of all components I am able to instantiate? How can I get a listing of all library cell names in a XSI Library?
Xilinx Answer #1459 : How to get the pin order of a XSI Library Cell in Synopsys or How to get the pins names for a XSI library cell
Xilinx Answer #1461 : XDE: Why is the INIT value shown for RAM/ROM different than what I specified?
Xilinx Answer #1463 : Foundation: Importing Viewlogic designs with multi-page macros
Xilinx Answer #1466 : Timing Analyzer 6.0.1: Cannot print .XRP from Timing Analyzer when running Windows 95
Xilinx Answer #1468 : XBLOX 5.x: Possible simulation problems if the labels are missing
Xilinx Answer #1469 : FPGA Configuration: XChecker: "ERROR 264: DONE signal did not go high"
Xilinx Answer #1472 : XC3000: I/O Slew Rates and other AC parameters (rise/fall times)
Xilinx Answer #1473 : Foundation XVHDL: How to control the # of BUFGs which are automatically inserted.
Xilinx Answer #1475 : Download Cables: Difference between DLC-5 and DLC-4
Xilinx Answer #1476 : PRE-UNIFIED CARRY symbol: Not supported
Xilinx Answer #1477 : FPGA Express/Compiler: Possible Incorrect Logic with downto Range Integer Comparison in VHDL
Xilinx Answer #1478 : CPLD: XC9500: Does Vccint have to be powered up before Vccio?
Xilinx Answer #1480 : CPLD: XC9500: What is the Power consumption/dissipation of a 9500 device?
Xilinx Answer #1481 : FGPA Express: How do you use pullups or pulldowns?
Xilinx Answer #1482 : Workview Office: Viewsynthesis SML semantic errors during synthesis: %PIN_LOAD
Xilinx Answer #1483 : FPGA Express: How do you specify slew rate in FPGA Express?
Xilinx Answer #1484 : Foundation XVHDL: Using XBLOX
Xilinx Answer #1485 : Foundation XVHDL: Using RAM and ROM in XC4000 devices
Xilinx Answer #1486 : Foundation XVHDL: Using CLB Latches
Xilinx Answer #1487 : Foundation XVHDL: Using Timespecs
Xilinx Answer #1489 : CPLD: 9500: How do you use global clock nets?
Xilinx Answer #1490 : CPLD: XC9500: Device Slew Rates (Rise/Fall times) with capacitive loads
Xilinx Answer #1493 : PROFlow 3.0: About "PSFM !No resume"
Xilinx Answer #1494 : XC4000E/EX/XL/XV/XLT: Duty Cycle
Xilinx Answer #1495 : M1 and Workview Office: How do I set up concurrent licensing?
Xilinx Answer #1496 : PROMS: Can reset polarity be changed on a programmed device by reprogramming it?
Xilinx Answer #1498 : Foundation XVHDL: How to access a user-created VHDL library
Xilinx Answer #1500 : FPGA Express: Does FPGA Express have any 'scripting' capability?
Xilinx Answer #1501 : Foundation: Connecting a symbol bus pin to a bus of different width
Xilinx Answer #1502 : Foundation: BTRIEVE error 11: specified file name is invalid.
Xilinx Answer #1504 : **XACT-CPLD: Need two Project.lst files if using both XACT and XACT-CPLD and PROflow
Xilinx Answer #1506 : XACT: How to LOC (lock) pins and reserve/restrict pins via a constraints file
Xilinx Answer #1507 : Foundation: Adding parts and speed grades to the selection menus
Xilinx Answer #1509 : Foundation XVHDL: Win32s Error, Unhandled Exception Detected
Xilinx Answer #1512 : **Obsolete**Foundation 6.0 Install: Error: VXD driver Daikon.386 missing
Xilinx Answer #1514 : 96 DATA BOOK: Missing dimension for HQ304 lead thickness 'c' on p11-37
Xilinx Answer #1516 : PPR error 6103: Possible Cause of "The EQN symbol ... has an invalid pin ... "
Xilinx Answer #1518 : Foundation Schematic: Changing table (title block) information or date on schematics
Xilinx Answer #1519 : FPGA Configuration: What Threshold does CCLK use for 5 Volt FPGAs?
Xilinx Answer #1520 : XC2000L/XC3000L/XC4000L: Estimating power consumption for 3.3V Devices (2000L, 3000L, 4000L)
Xilinx Answer #1521 : syn2xnf : ERROR 220: Can't open file '__ffgen__.xnf'
Xilinx Answer #1523 : X9500: Using Local Feedback Paths
Xilinx Answer #1525 : Foundation Install: Hangs or give Fatal Exception while "Attaching Libraries"
Xilinx Answer #1531 : Viewsim: vsec error 1026 Required license not found for product Viewsim
Xilinx Answer #1532 : Workstation install: How to find a particular file on the Sun/HP 5.2.1 CD
Xilinx Answer #1535 : UNISIMS/SIMPRIMS: Verilog naming rules for user-specified identifiers in Xilinx designs
Xilinx Answer #1536 : CPLD: XC9500/XL: How are unused I/O pins handled?
Xilinx Answer #1538 : PROMs: XC1736A Reset Polarity is not programmable
Xilinx Answer #1539 : 2.1i Install: How to install the Concept-HDL libraries on Windows PC (NT/95/98)?
Xilinx Answer #1540 : SYNPLIFY: How to convert tristate multiplexers to LUT multiplexers using the syn_tristatetomux attribute?
Xilinx Answer #1542 : Foundation Install: shadow caused segment load failure lm_acs.dll
Xilinx Answer #1543 : Hardware Debugger 6.0.1: Parallel download cable is not supported.
Xilinx Answer #1544 : Design Manager 6.0.1: Translate in Win 95 produces a DOSGRAB "DOS mode" message
Xilinx Answer #1545 : Foundation Schematic: How to quickly locate nets in a schematic
Xilinx Answer #1546 : WIR2XNF ERROR: SEC: HOST is not in the HOSTS file. ERROR 4: IWINIT Failure.
Xilinx Answer #1547 : Foundation: Trying to open Project Manager exits Windows
Xilinx Answer #1548 : M1 V-System: VHDL/VITAL RAMs do not simulate properly or respond to stimuli on HP-UX
Xilinx Answer #1549 : Foundation: Selecting Using Help gives "not enough memory"
Xilinx Answer #1550 : PROsim: Simulation with OSC4.1: could not find WIR file xc4000:osc4.1
Xilinx Answer #1553 : OrCAD Capture 7.0: How to add the net attributes?
Xilinx Answer #1554 : EDIF 2.0.0 naming conventions and translation of escaped Verilog names to EDIF
Xilinx Answer #1555 : VERILOG-XL 2.6: "WARNING: The source browser has detected a bad object in the source."
Xilinx Answer #1556 : Foundation XVHDL: how to use the OSC4 oscillator
Xilinx Answer #1557 : XNFBA error 301: Possible workaround
Xilinx Answer #1558 : Windows 95: help fails with three programs within XACTstep 6.0 program group
Xilinx Answer #1559 : "error #83 buffer too small" is given when starting PROcapture
Xilinx Answer #1560 : FPGA Configuration: Express Mode requires CRC disabled or INIT will go LOW.
Xilinx Answer #1561 : SYNPLIFY: How to specify a port on a black_box is a clock using the syn_isclock attribute?
Xilinx Answer #1562 : QuickSim: MODEL property expected but not found, NULL model will be inserted
Xilinx Answer #1565 : OrCAD Capture 7.0: xnfmerge error 20 caused by invalid pin record with TIMESPEC symbol
Xilinx Answer #1566 : FLOORPLANNER-XACT: Printing Problems in Windows 95
Xilinx Answer #1567 : XC3000/XC4000/XC52000: XACT 5.2- XNFMERGE: S attribute attached to OBUF output at top level gets dropped
Xilinx Answer #1568 : XNFMERGE 5.2.0: FAST, MEDFAST, MEDSLOW properties dropped when attached to OFD/OUTFF/OBUF/OBUFT macros
Xilinx Answer #1570 : ABEL//PLD to XNF Translator: Pin not declared as output pin / No Equation outputs
Xilinx Answer #1571 : XEPLD/XABEL: xr2: [Error] Ignoring symbol with same name as previous symbol.
Xilinx Answer #1572 : XC9572: JEDEC file generation and JTAG programming support
Xilinx Answer #1574 : XChecker Cable: The order part number for xchecker cable.
Xilinx Answer #1575 : XC4000XL: 1996 DATA BOOK: Page 4-24 table 10.Supported Source for XC4000-Series Device Inputs is incorrect
Xilinx Answer #1576 : XDE issues messages on non-applicable TNM and Timespecs
Xilinx Answer #1577 : JTAG - Are there pullups/pulldowns in the TAP pins(XC4000, XC4000e, XC5200, XC4000EX)
Xilinx Answer #1579 : FPGA Configuration: Size of external pulldown needed to create a logic low.
Xilinx Answer #1583 : Foundation Schematic: Viewlogic Import error - cannot connect wire to symbol
Xilinx Answer #1585 : UNISIMS/SIMPRIMS: BUFE, BUFT behaves differently for fron-end and back-end simulation for Virtex
Xilinx Answer #1586 : Foundation: How to generate a schematic from an XNF file
Xilinx Answer #1589 : 95216F .LCF file missing from HW-130 archive
Xilinx Answer #1590 : Viewsynthesis - vhdl error: the name "pfalling"/"prising" is undefined
Xilinx Answer #1594 : XACT-CPLD: rg37:[Warning] Programming output for device type 95144160 is not supported
Xilinx Answer #1599 : M1 WS INSTALL : HP system requirement : HP unix 10.x
Xilinx Answer #1600 : LICENSING: How to check the version of the lmgrd license manager and XXACTD license daemons
Xilinx Answer #1601 : Foundation: Importing OrCAD Schematics to Foundation
Xilinx Answer #1602 : HW-130: What adapters do I need to program a 9500?
Xilinx Answer #1603 : CPLD :XC9500/XL: When can the XC9500 internal IOB pullups be accessed?
Xilinx Answer #1604 : M1: Pin Locking, I/O Constraints in UCF file
Xilinx Answer #1605 : EZTag Cable: May have problems programming 9500's from computers with EPP port
Xilinx Answer #1606 : Viewsynthesis: Unexpected Heap Error 6000
Xilinx Answer #1607 : Constraints: How do I specify Timespec and Timegroup constraints in a UCF file
Xilinx Answer #1609 : 96 DATA BOOK: pps. 4-113 to 4-116 4025E / 4028EX/XL pinout shows 21 address pins
Xilinx Answer #1610 : Report Browser 6.0: File extensions for each report file and their locations.
Xilinx Answer #1613 : Design Manager 6.0.1: Out of memory errors with Windows95
Xilinx Answer #1615 : XCHECKER SOFTWARE 5.2.1: What are the system memory requirement in order to run?
Xilinx Answer #1616 : Xchecker Software and HARDWARE: Troubleshooting Guide. Warnings and Error messages explained
Xilinx Answer #1617 : XCHECKER SOFTWARE: What is the difference between xck88.exe and xchecker.exe?
Xilinx Answer #1618 : XC5200: How to use Direct Connect routing resources?
Xilinx Answer #1619 : Esperan VHDL Tutorial: Who to contact for more information.
Xilinx Answer #1620 : Esperan VHDL tutorial: Where are the example VHDL labs/files?
Xilinx Answer #1621 : PPR, XDELAY: Why timing/performance results differ in the two report files.
Xilinx Answer #1622 : Xaltran: How to install and use with Workview Office.
Xilinx Answer #1623 : Foundation Simulator: How to assign a value to a bus using Formulas
Xilinx Answer #1624 : JTAG - Do the XC4000 based families require a special bitstream for JTAG Config?
Xilinx Answer #1625 : XC9500: Quiescent Supply Currents
Xilinx Answer #1626 : Foundation Simulator: Unknown outputs on 3K VHDL/ABEL/schematic design
Xilinx Answer #1629 : 9500 EZTAG: Patches/Updates are availible on Xilinx BBS/FTP site
Xilinx Answer #1630 : How to manually edit a prowave waveform
Xilinx Answer #1631 : XABEL-CPLD v6.1.2: JEDEC to ABEL Conversion not available under Win95
Xilinx Answer #1632 : XEPLD, XC7318, XC7336: nd100:[Error] (nd104, hi317) Could not map '<instance>' into a fast function block. (Fast Clocks)
Xilinx Answer #1633 : XEPLD, XC7318, XC7336: nd100:[Error] (nd105, hi317) Could not map '<instance>' into a fast function block. (Fast Output Enables, FOE)
Xilinx Answer #1634 : Printed Circuit Board (PCB) considerations of Xilinx devices
Xilinx Answer #1636 : M1 : Invoking LogiBLOX Graphical User Interface (GUI)
Xilinx Answer #1637 : M1-Pre: How to get MAP to report number of flip-flops, LUTs used
Xilinx Answer #1638 : XABEL,XACT-CPLD: Only one product term allowed for OE, Set, Reset, Clk (9500, 7300)
Xilinx Answer #1639 : OrCAD Capture 7.0: design rule check gives warning message:[DRC0014] for BUFT components
Xilinx Answer #1640 : CPLD : XC9500: Where to find svf2xsvf.exe for ISP using the 8051 microcontroller
Xilinx Answer #1641 : ** XABEL-CPLD: Some hints on the error 'Done: failed with exit code: 0001'
Xilinx Answer #1642 : M1 : Examples of Timing Specification in the User Constraint File (.ucf)
Xilinx Answer #1643 : WIR2XNF 5.2.x: Check program failed, symbol for ___ is newer than WIR file
Xilinx Answer #1644 : M1.4: How to setup and debug Multi-Pass Place and Route/Turns Engine/Networked PAR
Xilinx Answer #1645 : 96 DATA BOOK: 4000E prom size (bits) page 4-57
Xilinx Answer #1646 : 96 DATA BOOK: XC4000EX Program Data and Prom size (bits), p. 4-58
Xilinx Answer #1649 : Design Manager 6.0.1: Translate--> XMAKE: ERROR: Failed to find part type <part> in 'partlist.xct'.
Xilinx Answer #1651 : Configuring device I/Os as an open-drain (open-collector)
Xilinx Answer #1654 : XC5200: programmable weak keeper cells.
Xilinx Answer #1655 : UNISIMS/SIMPRIMS: How is the $recovery system task used in the Block SelectRAM+ models?
Xilinx Answer #1657 : Foundation: How to use a library macro as a template for a user-defined macro
Xilinx Answer #1659 : XC4000E/EX/XL/XLT/XV: M1- TBUF net Delay 4000EX - Effect of the Pullup.
Xilinx Answer #1661 : 4000 device bitstream compatibility
Xilinx Answer #1664 : Design Manager 6.0.1: PPR - "Error XLM:KEY_NOT_FOUND" (LPT Conflict). Using Win 95.
Xilinx Answer #1666 : XABEL,XACT-CPLD: What Xilinx packages come with XABEL(DS371) and XACT-CPLD(DS560)?
Xilinx Answer #1668 : Xilinx online documentation available on FTP site
Xilinx Answer #1669 : ** XABEL-CPLD: Out Of Memory error or long compile times (@CARRY directive)
Xilinx Answer #1670 : SYNOPSYS : The output of replace_fpga still contains CLB element/write command fails in FPGA Compiler
Xilinx Answer #1671 : XDM 5.2: The Translate Menu does not have XEMAKE underneath it
Xilinx Answer #1672 : What is the purpose of DONEIN, Q1Q4, Q3, Q2 on STARTUP macro?
Xilinx Answer #1673 : M1 : HDL flow with LogiBLOX, implementation and simulation files.
Xilinx Answer #1675 : XC5200/XC4000E/EX/XL/XV: How flip-flop initial states are determined for FPGAs.
Xilinx Answer #1676 : PPR 5.2.1: Hangs the machine, doesn't respond
Xilinx Answer #1677 : M1.x: EPIC has no Printing Capability
Xilinx Answer #1678 : IBIS Models are now availible on the Xilinx Anonymous FTP site
Xilinx Answer #1679 : Checking the Hardware and software requirement on Workstation and PC.
Xilinx Answer #1680 : XNFPREP 5.2.1: Error 7859:'C2P' type TS attribute 'TSxx' need an associated TS flag attached to a net or pin.
Xilinx Answer #1681 : How do I specify a bidirectional I/O in my schematic?
Xilinx Answer #1682 : Design Manager 6.0.1: Unfamiliarly named filesystem, ParcPlace Systems, FATFilename
Xilinx Answer #1683 : TIMING ANALYZER 6.0.1: Discrepancy between Timing Analyzer and Xdelay
Xilinx Answer #1685 : Install: How to install XACT 5.2.1 on a HP ver 10.20
Xilinx Answer #1686 : Old part works on board, but the new Xilinx part does not! --Asynchronous design.
Xilinx Answer #1687 : FPGA Configuration: Makebits- CRC checking does not exist for configuration in 2K and 3K devices
Xilinx Answer #1688 : XACT-CPLD, 9500: What do my environment settings need to be?
Xilinx Answer #1689 : Foundation XVHDL: missing TNM attribute will cause XNFPREP Error 7845
Xilinx Answer #1691 : EZTAG: Can FPGAs be mixed in with 9500 devices when using the JTAG cable?
Xilinx Answer #1692 : 17256D PROM recall--device ID errors (two lot codes only)
Xilinx Answer #1693 : Foundation HDL Editor: Performing a text search causes PC to lock up.
Xilinx Answer #1695 : 96 DATA BOOK:page 4-358 commercial voltage range for 3100A
Xilinx Answer #1696 : 96 DATA BOOK: Solder time for Maximum soldering temperature is incorrect for 9500 parts
Xilinx Answer #1697 : XC1765DPD8C PROM: "Selected algorithm (1765D) is not correct for the device in the socket (1736D)"
Xilinx Answer #1699 : XACT Timing Analyzer: Cannot open file C:\\con<num>.<num> (Win95 only)
Xilinx Answer #1700 : CPLD XC9500/XL: Test process of devices before shipment
Xilinx Answer #1701 : XC9500: "Single Cell Charge Loss" (SCCL) or "Single Bit Charge Loss" (SBCL)
Xilinx Answer #1703 : XC7300: Can I use a product term Output Enable in a Fast Function Block (FFB)
Xilinx Answer #1704 : Prom File Formatter 6.0.1: Where does the concatenated file go for a daisy-chained prom file?
Xilinx Answer #1706 : XABEL: How to get test vectors (.TMV file) into an XC9500 JEDEC file
Xilinx Answer #1707 : CPLD XC9500: Minimum reset signal pulse width
Xilinx Answer #1708 : XC4000E Synopsys Libraries: XC4000E -2 .db files available for users of XSI 5.2.1 & Synopsys 3.3b and above
Xilinx Answer #1709 : XC3000 Synopsys Libraries: XC3100A -1 and -09 .db files available for users of XSI 5.2.1 & Synopsys 3.3b
Xilinx Answer #1710 : XNF2WIR Error 13: Unsupported XNF netlist version '6'.
Xilinx Answer #1711 : XABEL-CPLD 6.1.2: Is this an automatic upgrade to v6.1.1?
Xilinx Answer #1712 : 7300: Fast clock driver is connected to non-fast clock pin
Xilinx Answer #1713 : win 95: Simulation Utility fails with "Path/File access error"
Xilinx Answer #1715 : TNM attached to net between PAD and IBUF/BUFG not forward traced
Xilinx Answer #1716 : SPW: Is there support for Cadence's SPW product?
Xilinx Answer #1717 : XABEL-CPLD: Does it run under Windows 95?
Xilinx Answer #1718 : Diamond Speed Star 64: Translate or Design Manager hanging
Xilinx Answer #1719 : The 4025E does not have address pins A18:A21, these are on EX/XL devices only.
Xilinx Answer #1720 : M1: Solaris install from HP mounted CD gives "Could not write directory"
Xilinx Answer #1722 : CONCEPT2XIL Error #169: Port modes are not the same. The entity declaration needs to be updated
Xilinx Answer #1723 : XC5200: Use of DI pin to a flipflop in a Logic Cell (LC)
Xilinx Answer #1727 : CONCEPT2XIL/HDLCONFIG: Warning: No acceptable view exists for cell AND2 in library <path_to_library>
Xilinx Answer #1728 : CONCEPT-HDL: How to generate a board-level symbol?
Xilinx Answer #1729 : Workview Office: Error 8031: Flex/LM Error: Cannot find license file[-1,73:2]
Xilinx Answer #1732 : Design Manager 6.0.1: Error - "Cannot find input design. Please specify an existing design"
Xilinx Answer #1735 : Change->LogiBLOX does not reliably update symbol in Workview Office
Xilinx Answer #1736 : Kernel Limitations May Cause Out of Memory Problems on the HP Platform
Xilinx Answer #1738 : Control C Does Not Abort the Installation Procedure
Xilinx Answer #1743 : The -p Option of XNF2NGD Does Not Override the PART Statement in the XNF File
Xilinx Answer #1744 : Parameterized Attributes in the Viewlogic Viewdraw Schematic Editor Are Not Supported by Xilinx Tools
Xilinx Answer #1745 : ILDFFDX and ILDFLDX Library Components Have Been Renamed
Xilinx Answer #1751 : ViewDraw Symbols May Not Be Updated Properly After Entering a Change LogiBLOX Command
Xilinx Answer #1752 : Invoking the LogiBLOX GUI the First Time Could Take More Than 15 Seconds
Xilinx Answer #1757 : FPGA Compiler: Pullup/Pulldown Resistors are Deleted From Synopsys Design
Xilinx Answer #1759 : DC2NCF Requires libC.sl Library on the HP Platform
Xilinx Answer #1763 : M1 - RLOCs May Not Be Attached to Hard Macros
Xilinx Answer #1769 : TNT.41400: INITEMULATOR:FLOATING POINT EMULATOR (EMUTNT.DLL) IS REQUIRED
Xilinx Answer #1771 : FPGA Configuration: Can a 4000E or 5200 lead a 4000EX in a daisy chain?
Xilinx Answer #1772 : Makeprom: Where can I find a Workstation version of psplit?
Xilinx Answer #1773 : xc4000e: dp-ram:xnfprep gives segmentation fault, core dump
Xilinx Answer #1777 : Problems with Back-Annotation of Designs Containing Single CLB Replication Groups which are Not Eliminated by MAP
Xilinx Answer #1778 : Design Summary is Located at the End of the MRP (Map Report) File
Xilinx Answer #1784 : Synopsys Design Compiler: insert_pads->"This site is not licensed for FPGA compiler"
Xilinx Answer #1785 : SYNOPSYS: How to force a IOB NODELAY latch or flip-flop?
Xilinx Answer #1787 : 4000EX/XL: Can I use both the Output FF (OFD) and the Output MUX (OMUX2) of an IOB at the same time?
Xilinx Answer #1788 : 4000EX: Can I use a tri-state buffer (OBUFT) with the Output MUX (OMUX2)?
Xilinx Answer #1789 : xmake 6.0.1: l.s01.1: /usr/xilinx/bin/sparc/xsifix: fatal: relocation error: symbol not found
Xilinx Answer #1790 : 96 DATA BOOK: 95108 PQ160 does not have No Connects listed.
Xilinx Answer #1791 : XC9500F JTAG - Does it support JTAG functionality?
Xilinx Answer #1792 : Foundation Schematic: How to control output slew rate
Xilinx Answer #1793 : VERILOG-XL: Error! acc_replace_delays() [PLI-NOAPPREPMIPD] Error modifying MIPD: no XL loads on port
Xilinx Answer #1794 : Design Manager 6.0.1: Translate issues "cannot copy translated netlist"
Xilinx Answer #1795 : 4000E/EX: Can the BUFGLS, BUFGE, and BUFFCLK (4000X) and BUFGP and BUFGS (4000E) be driven with Internal Logic?
Xilinx Answer #1798 : Foundation Simulator: Where are custom Formulas stored?
Xilinx Answer #1799 : ** XABEL-CPLD: "Done: failed with exit code: 0003" when running Fitter
Xilinx Answer #1800 : fpga compiler: Wire load not found "parttype-s_wc"
Xilinx Answer #1801 : XC7300: MR (Master Reset) Pin can optionally be used as an input
Xilinx Answer #1802 : Synopsys FPGA Compiler: Error OPT-101: The target library does not contain inverter.
Xilinx Answer #1810 : M1.3 MAP: BLKNM, HBLKNM, RLOC and LOC Properties May Not be Respected by MAP in Some Instances
Xilinx Answer #1815 : ppi2040:[Error] The instance '$1I1/O' of component type 'OBUFT' is not supported or...
Xilinx Answer #1816 : XC9500: How to detemine low power mode timing (tLP, TLOGILP)
Xilinx Answer #1818 : M1.2/M1.3/M1.4 MAP: Exact Guide Mode May Not Recreate All COMPs from Initial Design Even When the Source Design Has Not Changed
Xilinx Answer #1821 : DATA I/O v5.3 algorithm 1700D programming failures: Device will not program, fails low voltage verify, CEO fails to assert
Xilinx Answer #1824 : ** HW-130: Programming 73144 yields "Warning! Programming Error at Address XXXX"
Xilinx Answer #1825 : UNISIMS/SIMPRIMS 2.1i: CLKDLL doesn't lock after RST is de-asserted
Xilinx Answer #1826 : Orcad: XNFPREP Error 3649: Possible cause if using CC8CLED with Capture 7.0
Xilinx Answer #1828 : HW-112 ALERT: 17256D and 17256 verification problems
Xilinx Answer #1829 : Bitstream compatability of the 3000, 3000A, 3000L, 3100 and 3100A devices.
Xilinx Answer #1832 : M1: Getting XACT and M1 License Files to use same license manager.
Xilinx Answer #1833 : UART design available as part of RS-232 interface application note
Xilinx Answer #1835 : Foundation: After unzipping archived project, errors updating xnf netlist
Xilinx Answer #1836 : The oscillator in the 4000 FPGA is disabled (if OSC4 unused) after configuration.
Xilinx Answer #1837 : What is the absolute junction temperature Tj for plastic and cermaic parts?
Xilinx Answer #1838 : Foundation: Netlist Conversion Error Missing pin <pin> of <symbol> or library error
Xilinx Answer #1839 : Foundation XVHDL: How to use Wide-Edge Decoders
Xilinx Answer #1840 : Foundation XVHDL: Setting NODELAY property on inputs
Xilinx Answer #1841 : JTAG - Is the JTAG circuitry of the 4000EX identical to the XC4000 and XC4000E?
Xilinx Answer #1842 : XC7336: Programming gives product ID error
Xilinx Answer #1843 : QuickSim: Mode pins (MDO, MD1, MD2) cannot be used in board-level simulation.
Xilinx Answer #1844 : Mentor schematic: Adding an INIT property to a CPLD flip-flop
Xilinx Answer #1845 : Cable - Xchecker, Parallel, and JTAG Cables what do they do and how do I identify them?
Xilinx Answer #1846 : 2.1i/1.5x/XABEL-CPLD: Controlling optimization using 'keep' and 'LOGIC_OPT'
Xilinx Answer #1861 : M1.3/M1.4 PAR/MAP: TBUFs with RLOC Constraint Must be Part of RPM with RLOC_ORIGIN Constraint
Xilinx Answer #1863 : Back-Annotation Timing Data May Contain Overly Conservative Values for the Setup Requirements of Some IOB Input Flip-Flops and Latches. Physical Post-layout Simulation Occurs When NGDAnno Is Ca lled Without a Reference to the NGM File.
Xilinx Answer #1867 : M1.xi: TRCE: IOB register to PAD paths (and vice-versa) are not reported or controlled
Xilinx Answer #1869 : Long Runtimes for Some Designs
Xilinx Answer #1870 : Logical Resources Are Not Listed in Timing Reports
Xilinx Answer #1871 : TRCE: Reports May Contain Preliminary Timing Values
Xilinx Answer #1872 : Clock Skew Not Accounted for in Path Analysis
Xilinx Answer #1873 : Hardware Debugger Cannot Communicate With HP-10.x OS Serial Port
Xilinx Answer #1883 : M1: ERROR:basnb - SECURITY ERROR --Unable to lock license for ngdbuild: license file syntax (-2,134:2) No such file or directory
Xilinx Answer #1884 : CPLD XC9500/XL: What is the guaranteed spec for data retention?
Xilinx Answer #1885 : M1Security is Based on FLEXlm, and Requires Lmgrd v4_1 and Xilinxd
Xilinx Answer #1890 : Moisture sensitivity level: Where to find this information??
Xilinx Answer #1891 : ** XABEL-CPLD6.1.2: problem with OLE server registration
Xilinx Answer #1893 : M1/A2.1i, Workview Office: Viewlogic library description file (LIBS.LST) for Workview Office/M1
Xilinx Answer #1894 : PPR 5.2.1: Execution on PC is slow on Windows 3.11?
Xilinx Answer #1895 : VERILOG-XL: SDFA Error: Type of INSTANCE xxxx does not match CELLTYPE <cell_name>
Xilinx Answer #1896 : M1 QuickSim: GSR (global set/reset) port removed from XC4000EX library
Xilinx Answer #1897 : XC3000/XC3000/XC4000/XC5200: Logic cells and the FPGA Density Cross Reference Guide
Xilinx Answer #1898 : MAP M1.1.1a: -os speed causes BITGEN-DRC ERROR:0 - netcheck: no source pins found on signal
Xilinx Answer #1900 : NGDBUILD (csttrans) M1.1.1A: ERROR:0 - Could not find INST(S) <signal name> in design
Xilinx Answer #1902 : Check issues warnings on ASHEETP, ASHEETL, BSHEETL, etc
Xilinx Answer #1903 : **Obsolete**Foundation Simulator: Unknown outputs on XBLOX or VHDL design
Xilinx Answer #1904 : FLow Engine 6.0.1: Error - Command line exceeds allowable limit
Xilinx Answer #1905 : Foundation HDL Editor: Code isn't highlighted with different colors properly.
Xilinx Answer #1907 : 2000L,3000L,3100L,4000L,4000XL: How do these 3.3V parts differ from their 5V counterparts?
Xilinx Answer #1908 : Global reset polarity in 2K, 3K, 4K/E/EX, 5K, 7K, and 9K devices
Xilinx Answer #1909 : OrCAD Simulate: How to use Xilinx's global reset and tri-state signals for functional simulation?
Xilinx Answer #1910 : 5.2.1: HP install Fatal Error 6015 cannot open file to write cdrom ...
Xilinx Answer #1912 : 4000E/EX/XL/XV: Bare die, what should the backside (substrate) connected to?
Xilinx Answer #1913 : Available patches for M1.1.1a 4KEX Pre-release...
Xilinx Answer #1915 : Merging license files for M1 and XACT-Step on WorkStations...
Xilinx Answer #1916 : NGDBUILD m1.1.1a: error 0:Unable to lock license for ngdbuild, no such feature exists.
Xilinx Answer #1918 : 7336, PROMs: Using the 7336 as a virtual SPROM
Xilinx Answer #1921 : PROsim: Out of Memory when loading a VSM file
Xilinx Answer #1923 : MODELSIM: How to compile the 1.5 Simprim, LogiBLOX, Unisim, and Coregen HDL libraries?
Xilinx Answer #1924 : Prowave: Sharing violation error
Xilinx Answer #1925 : XC5200: XACT 5.2.1- xnfprep: Error 4708
Xilinx Answer #1928 : 96 DATA BOOK: No pinout for the XC4036EX in a HQ240 package
Xilinx Answer #1929 : Xc9500: The fitter report pinout does not match that of the data book
Xilinx Answer #1931 : Flow Engine 6.0.1: Message "Could not find 2018.spd" during compilation of XC4000 design
Xilinx Answer #1932 : XNFPREP 6.0.1: Error 3525:Symbol `name' (type = INFF, output signal = WS0) has invalid pin CE
Xilinx Answer #1934 : Foundation Simulator: Can I prevent my design from being flattened for functional simulation?
Xilinx Answer #1935 : XC5200: What is the T(TSHZ) spec for 5200?
Xilinx Answer #1937 : PPR 5.2.1: Possible Cause of PPR error 9016 if using Floorplanner
Xilinx Answer #1938 : Foundation Schematic: Adding Attributes - LOC, X, etc.
Xilinx Answer #1939 : Timing Analyzer 6.0.1: Error - ctl3d32.dll This is not the correct version
Xilinx Answer #1940 : XNFMERGE : Warning 285. Net names and symbol pin names do not match.
Xilinx Answer #1941 : FPGA Configuration: For Peripheral configuration which is the MSB D7 or D0?
Xilinx Answer #1942 : XC4000XL: VTT connections on 4000XL pinouts...
Xilinx Answer #1943 : CONCEPT: CAPSLOCK_OFF and its effect on translation of lower-cased pin name properties
Xilinx Answer #1944 : dsgnmgr M1.1.1a: "Cannot find tool definition file..."
Xilinx Answer #1947 : FPGA Express v1.xx: App note available on FPGA Express XACT 5.2.x flow and M1 flow
Xilinx Answer #1948 : xc4000EX cclk maximum frequency specification
Xilinx Answer #1949 : Are M1 BIT files compatible with XCHECKER 5.x?
Xilinx Answer #1950 : Foundation: "File specified in $FILE parameter is missing" when pushing into macro
Xilinx Answer #1952 : **Obsolete**Foundation: Service Pack Install - Setup will not run
Xilinx Answer #1954 : XNFMERGE: how does it recognize what is a primitive vs. what is a macro in an XNF file?
Xilinx Answer #1956 : XACT-CPLD, XC9500: Assertion failed: ia.RetSize()==1 && ia[0]->RetInputInstance(), file outinst.cc
Xilinx Answer #1958 : Flow Engine 6.0.1: How to speed up the Translate step (wir2xnf) in XACT 6.
Xilinx Answer #1959 : Prowave: Can't load .wfm file into Prowave
Xilinx Answer #1960 : OrCAD Capture 7.0: XMAKE 5.2.0 fails to find user defined subhierarchy for 4kE design
Xilinx Answer #1963 : PPR: Design not routing (unroutes) because placement is to tightly packed.
Xilinx Answer #1964 : XNF specification: Naming Conventions for nets, buses, components and pins
Xilinx Answer #1965 : Hardwire: Power consumption?
Xilinx Answer #1966 : Viewsynthesis: BSCAN and Mode pin instantiation
Xilinx Answer #1967 : Viewsynthesis: PULLUP/PULLDOWN instantiation
Xilinx Answer #1969 : XNFPREP: ERROR 3525: Symbol 'U117' (type = INV, output signal = BCLOCk-) has an invalid pin 'O-'.
Xilinx Answer #1970 : XMAKE 5.x: File beltypes.dat not found
Xilinx Answer #1972 : Foundation Express 2.0.x: multiple modules in Foundation schematic can cause RLOC error:x4kma:312 in MAP
Xilinx Answer #1974 : Protel support for Xilinx libraries?
Xilinx Answer #1975 : How to lock down I/O pins in Exemplar
Xilinx Answer #1976 : EZTAG: WARNING: Part type "XC95xxx" is supported only in BYPASS mode.
Xilinx Answer #1978 : Foundation XABEL: "XABEL is not installed" error when synthesizing ABEL code
Xilinx Answer #1980 : PPR 5.2.x: Relaxing PPR timespecs in xactinit.dat
Xilinx Answer #1981 : For PQ100 package, how to identify pin 1 since there are 2 holes on the package
Xilinx Answer #1982 : ngdbuild m1.1.1a: Prohibit pin locations in ucf file.
Xilinx Answer #1983 : NGDBUILD M1.1.1a: Invalid UCF/NCF file entry value detected while searching for PART
Xilinx Answer #1984 : FPGA Configuration: Address Pins A18 - A21 are optional for XC4000EX only
Xilinx Answer #1985 : M1.3/M1.4/M1.5/A2.1i ,Workview Office : Adding custom functions to ViewDraw (EDIFNETO/EDIFNETI/LogiBLOX)
Xilinx Answer #1986 : Foundation: After copying a project, some files are missing
Xilinx Answer #1987 : How to preserve/keep/save or prohibit software from using certain pins
Xilinx Answer #1988 : XC4000E: Creating Synchronous or Dual port RAM for MemGen
Xilinx Answer #1989 : FPGA: Input/Output pin levels on various family of devices.
Xilinx Answer #1991 : CONCEPT-SCALD: --Iterated Instance methodology replaces SIZE property
Xilinx Answer #1992 : SYNPLIFY: How to instantiate LUT primitives in HDL for Virtex?
Xilinx Answer #1994 : Orcad SDT2XNF: What is the latest version of inf2xnf ?
Xilinx Answer #1995 : SYNPLIFY: How to set the different I/O standards for Virtex using the xc_padtype attribute?
Xilinx Answer #1997 : Design Manager M1: Fails to start (hangs/core dumps/segmentation faults) on UNIX machines
Xilinx Answer #1998 : XC5200: What is the value of the weak pull-up on an I/O?
Xilinx Answer #1999 : XC5200: What level are the I/O pins on an unprogrammed 5k device?
Xilinx Answer #2000 : OrCAD Capture 7.0 : How to create a symbol to represent an XNF file?
Xilinx Answer #2001 : M1: What are the differences between node-locked and floating licenses?
Xilinx Answer #2003 : M1: Win95/NT Release: Overall Installation and License issues
Xilinx Answer #2004 : ** XABEL-CPLD (DS-571-PC1):How to print the on-line help
Xilinx Answer #2005 : CONCEPT-HDL: How to integrate CORE Generator modules?
Xilinx Answer #2010 : Foundation XVHDL: message "No entity bound to this instance"
Xilinx Answer #2011 : XSimmake 5.2.1, Workview Office 7.3.0 or newer: check/vsm_ngui fail under XSimmake script
Xilinx Answer #2012 : Input and Output parameters (i.e. setup times) from XDELAY don't match those listed in Data Book.
Xilinx Answer #2013 : Running lmgrd brings up network to be logged in
Xilinx Answer #2015 : Dynatext Browser: dtext quits with bus error when executed from Solaris CDE.
Xilinx Answer #2017 : FPGA Configuration: Difference between the preamble/length count of XC4000/E/EX and the XC5200
Xilinx Answer #2019 : XNF Specification: What is difference between T and B direction in an EXT record?
Xilinx Answer #2022 : SYNPLIFY: How to instantiate and initialize Virtex Select BlockRAM+?
Xilinx Answer #2024 : COMPOSER: Is there support for Cadence's Composer product?
Xilinx Answer #2026 : Configuration: APM - Can RDY/BSY be used to signal start of configuration instead of INIT?
Xilinx Answer #2027 : What does abreviation "BSC" mean in package dimensions
Xilinx Answer #2029 : CPLD: XC9500: Programming an XC9500 CPLD with a microcontroller (ISP)
Xilinx Answer #2033 : 4000XL: Inputs are 5V compatible
Xilinx Answer #2034 : Flow Engine 6.0.1: xnfprep error 7804: CST file doesn't exist
Xilinx Answer #2037 : M1/XSI v1.1.1a: Template runscripts in $XILINX/synopsys/examples are incorrect
Xilinx Answer #2039 : NG2VER, NGD2XNF: Unable to copy temporary file ...
Xilinx Answer #2040 : Packaging: Test Clip Manufacturers
Xilinx Answer #2042 : CONCEPT2XIL: "Unknown child port decl" / "Architecture not found errors"
Xilinx Answer #2043 : FLOORPLANNER-XACT: Driver problem (macxw4.drv) with Win95
Xilinx Answer #2044 : PC Hangs: Some S3-based video card Drivers are incompatible with WIN32S
Xilinx Answer #2045 : HW-130 programmer support for 9500 series devices
Xilinx Answer #2046 : Bad Workview Office 7.2 CDs have been sent out by Xilinx
Xilinx Answer #2050 : XNFMERGE 5.2.1: INTERNAL ERROR: 293
Xilinx Answer #2051 : XNFPREP 5.2.1: Errors 7822, 7854 from constraints file TIMESPEC
Xilinx Answer #2055 : CADENCE XIL2CDS: XIL2CDS hangs on HP-UX v10.20
Xilinx Answer #2056 : CONCEPT2XIL/SIR2EDF: " Error! Cell name not specified" errors
Xilinx Answer #2058 : BP MICROSYSTEMS, 9572: 9572 support missing in current v3.23 algorithm
Xilinx Answer #2059 : FPGA Configuration: Peripheral Configuration from MCS file causes error (EX/XL).
Xilinx Answer #2060 : Workview Office: Project Manager issues "unexpected file format" and "invalid page fault"
Xilinx Answer #2061 : FPGA Express, FPGA Compiler II: How to obtain information on shell commands (FST)
Xilinx Answer #2062 : XBLOX: Running XBLOX on remote Solaris machine gives "UNIX error ENOENT" after loading defaults.qofRunning XBLOX for Sun4 on Solaris on remote machine gives "UNIX error ENOENT" after loading de faults.qof
Xilinx Answer #2063 : PROMS: XC17128L and XC17256L Data I/O programming support now available
Xilinx Answer #2064 : Design Manager 6.0.1: Error "unhandled exception, invalid file name" on startup
Xilinx Answer #2065 : HW-130/XC95216: Product code errors when programming a device
Xilinx Answer #2066 : **Obsolete**Foundation Schematic: PPR ERROR 9028 when using COMPMC8 macro in 5200 design
Xilinx Answer #2068 : 96 DATA BOOK: Inconsistency in Pinout for 4025E PG299 package
Xilinx Answer #2069 : QuickSim II: Output of XBLOX BUS_IFxx component is X
Xilinx Answer #2071 : CB228, CB196, CB164, CB100: Where do customer get the pins formed?
Xilinx Answer #2072 : M1 Map - A parsing error has occurred at line 2, token 'P124'.
Xilinx Answer #2074 : LCA2XNF 5.2.1: Outputs an Inaccurate .xnf file
Xilinx Answer #2075 : Viewsynthesis: How to disable automatic XBLOX insertion
Xilinx Answer #2076 : Problem with pin mismatch, macro in Workview Office, xnf from Synplicity or FPGA Express
Xilinx Answer #2077 : DATA I/O: "ERROR: Incompatible user data for device selected" when programming 9536 with a JEDEC file / Notes on JEDEC file format
Xilinx Answer #2078 : Cadence Concept XC4000E: ofdtxi flip-flop powers-up reset instead of set in Hardware.
Xilinx Answer #2079 : 7336 part programmed by BP Micro programmer works, but HW-130 programmed part does not--LOWPWR problem
Xilinx Answer #2080 : SYNOPSYS 3.x: Set_max_delay attribute is not passed on to .sxnf
Xilinx Answer #2081 : **Obsolete**Foundation Schematic: How to replace a symbol without deleting nets
Xilinx Answer #2083 : XDM: XC4025E part is not displayed, even though partlist.xct is correct
Xilinx Answer #2084 : XEPLD 6.0: hi604: [Warning] Unexpected TIMESPEC string ignored
Xilinx Answer #2085 : 3000L: speed files and TQ144 package file
Xilinx Answer #2089 : M1/FPGA Compiler: Sometimes set_false_path/set_max_delay not translated by write_script
Xilinx Answer #2090 : XNFPREP 5.2.1: error 4572 and error 4573
Xilinx Answer #2091 : Makebits 5.2.1: XDE, XDM and commandline differences in Default options for a 4000e and a 5200 part
Xilinx Answer #2092 : Design Manager 6.0.1: OE20 Caused an Invalid Page Fault (Illegal Operation) in Windows 95
Xilinx Answer #2093 : XC7000: Device Slew Rates (Rise/Fall times)
Xilinx Answer #2094 : PPR 5.2.x: XC5200 design with Readback gives ERROR 9905: NET "$I417/CLK" has no source
Xilinx Answer #2095 : Workview Office: Viewsynthesis support is available for XC9500 family.
Xilinx Answer #2097 : **Obsolete**Foundation Simulator: Greek fonts appear in the Waveform Editor
Xilinx Answer #2098 : FPGA Configuration: What are the thresholds for the Configuration Pins?
Xilinx Answer #2099 : M1: NGDBUILD fails with Multiple Driver errors. EDIFNETO option missing
Xilinx Answer #2100 : M1 PLD_EDIF2TIM: Error: Cannot find library specified "SIMPRIMS"
Xilinx Answer #2104 : SYNPLIFY: How to instantiate RAM or ROM in HDL (Verilog/VHDL)?
Xilinx Answer #2105 : 96 DATA BOOK/ISP APPLICATION GUIDE: Inconsistency in High-drive output current
Xilinx Answer #2106 : 2.1i NGD2VER/NGD2VHDL: WARNING:NetListWriters:104 - Port bus BUS_NAME[3:0] on block TOP is not reconstructed.
Xilinx Answer #2108 : HW-130, XC1700/D/L: Device FAILED Low Vcc or Low Voltage Verify
Xilinx Answer #2109 : CPLD : XC9500/XL Fitter Report Equation Syntax
Xilinx Answer #2110 : Foundation HDL Editor: ABEL state diagram template gives grounded outputs.
Xilinx Answer #2116 : V1.4 COREGEN: SYNOPSYS VHDL FLOW
Xilinx Answer #2118 : V1.5, V1.4 COREGEN, JAVA: This program has performed an illegal operation /page fault in module WINAWT.DLL on Windows (display settings problem)
Xilinx Answer #2119 : FPGA Configuration: Device seems to be in bypass mode and will not configure.
Xilinx Answer #2122 : VERILOG-XL: Error! Instance specific item not found in `uselib path. Directory : <path_to_library>
Xilinx Answer #2126 : CPLD: 9500/XL : ESD information
Xilinx Answer #2129 : HW-130: programmer displays "HW-133-PG84" when TQ100 adapter is used.
Xilinx Answer #2130 : M1 Licensing: Using a workstation as a server for PC and workstation applications
Xilinx Answer #2132 : 96 DATA BOOK: 3064APQ160/3164APQ160 pinouts pin 2 and pin 3 should be N.C. pins
Xilinx Answer #2133 : CPLD: 9500: EZTag : xchecker rcab error 4059
Xilinx Answer #2135 : Xmake fails during OrCAD Annotate: program does not support incremental annotation
Xilinx Answer #2136 : HW-130: Installation tips for SunOS workstation platforms
Xilinx Answer #2138 : M1/XACT: How do I add comments to my constraints file?
Xilinx Answer #2139 : CPLD: 9500 : Are 9500 Inputs 5 volt tolerant when Vccio is 3.3 volts?
Xilinx Answer #2140 : Foundation: Difference between I/O Pads and I/O Terminals
Xilinx Answer #2141 : Design Manager M1.3/M1.4/M1.5: "illegal command line for invoking the Flow Engine", produced when spaces are used in the path; basut 215
Xilinx Answer #2142 : Hardware Debugger 6.0.1: .ll file not found
Xilinx Answer #2144 : XC9500 JTAG - How long does it take to carry out various JTAG instructions in 9500 CPLDs?
Xilinx Answer #2145 : SYNPLIFY: How to a declare PULLUP/PULLDOWN in HDL (Verilog/VHDL)?
Xilinx Answer #2146 : CPLD: XC9500: How to place a macrocell/signal in low power mode (LOWPWR or PWR_MODE)
Xilinx Answer #2147 : XACT_CPLD: Hitop - This program has performed an ilegal operation.....
Xilinx Answer #2148 : Where to get the FPGA Demo Board Schematic?
Xilinx Answer #2149 : 1.1 JTAG Programmer - JTAG programming software gives error:0
Xilinx Answer #2150 : CPLD: XC9500: The high level output voltage of an 9500 CPLD is ~4 volts
Xilinx Answer #2152 : Foundation: BTRIEVE error 88 - incompatible mode error
Xilinx Answer #2153 : FLOORPLANNER-XACT: Cannot see STARTUP, READBACK, of BSCAN symbols in my foorplanner.
Xilinx Answer #2155 : Definition of a "gate", when defining number of logic gates in a FPGA
Xilinx Answer #2157 : bitgen m1.2-WS: TIE option may cause incorrect functionality.
Xilinx Answer #2161 : Foundation Project Manager: How to copy a user created macro from one project to another?
Xilinx Answer #2165 : Hardware Debugger 6.0.1: Message - Cannot get the startup directory.
Xilinx Answer #2166 : Cable not recognized: Eztag hangs when execute is pressed
Xilinx Answer #2167 : Synopsys: How to specify slew rates in Synopsys FPGA Compiler or Design Compiler?
Xilinx Answer #2172 : XDM, Design Manager 5.2.1: Returns " <speed grade> is not a valid speed grade"
Xilinx Answer #2173 : PPR: FATAL ERROR: The msg set for "msg" does not exist
Xilinx Answer #2174 : XC9500: Hitop.exe fails erroneously saying too many pins are used on 9500 design
Xilinx Answer #2177 : OrCAD Capture: Design rule check gives "no matching pin" error for OFD16 component
Xilinx Answer #2178 : CPLD : 9500: Quality Assurance: How are Xilinx xc9500/xc7300 parts tested?
Xilinx Answer #2180 : Veribest: Technical Support
Xilinx Answer #2181 : M1: ERROR: basnb - SECURITY ERROR -- Unable to lock license for ngdbuild: Cannot find license file (-1,73:2) No such file or directory
Xilinx Answer #2183 : 4000XL/4000EX switching characteristics (rise/fall)
Xilinx Answer #2185 : SYNPLIFY: How to change the output slew rate using the xc_fast attribute?
Xilinx Answer #2187 : M1.x: EPIC: How do I change the default display colors and fonts?
Xilinx Answer #2190 : XDELAY 5.2.1: Doesn't IGNORE the path specify by the TIMESPEC IGNORE attribute
Xilinx Answer #2191 : M1 Map - FATAL_ERROR:baste:bastetspec.c:2317:1.62 - NET OFFSET...
Xilinx Answer #2193 : M1 Map - Warning:baste:102 - Logic enclosed by Fmap symbol '..' has too many inputs
Xilinx Answer #2195 : JTAG - Do Update Latches and Data Registers get reset in Test Logic Reset State?
Xilinx Answer #2196 : 5200: Readback with xchecker on 5202 devices
Xilinx Answer #2197 : What are the differences between Synopsys FPGA Compiler and Design Compiler?
Xilinx Answer #2200 : HDL Synthesis guide pp 1-8 & 1-9: Location of design files is wrong.
Xilinx Answer #2201 : ppr Error 9004: The IOPAD must be placed in a dedicated pad location.
Xilinx Answer #2202 : LEAPFROG: How to compile the Xilinx Alliance libraries for Cadence's Leapfrog?
Xilinx Answer #2203 : Xsimmake reports no license for schematic in Pro Series
Xilinx Answer #2205 : PPR 5.x: Possible cause of ERROR 9929
Xilinx Answer #2207 : M1 Map: What are the rules for merging FFs into an IOB with the MAP -pr b switch?
Xilinx Answer #2208 : EZTAG: EZTAG.EXE cannot be run as a DOS application under Windows NT
Xilinx Answer #2209 : V1.4.0 CORE Generator: Foundation Schematic Flow
Xilinx Answer #2211 : XC4036EX/XL: HQ240 package list is missing information
Xilinx Answer #2213 : M1.x: EPIC: How to read the CLB carry mode
Xilinx Answer #2214 : Workstation Install: Invalid License Key (inconsistent encryption code for....
Xilinx Answer #2215 : CPLD: OPT=MERGE
Xilinx Answer #2216 : CONCEPT HDL Direct Error: Invisible property SIG_NAME="GR \G": Illegal HDL name: illegal character after signal or port name
Xilinx Answer #2217 : What do the Xs and @s mean in the Fitter report?
Xilinx Answer #2220 : Foundation Express: Edit Constraints option greyed out; cannot access Constraints GUI
Xilinx Answer #2222 : M1: install over Novell network gets "can't find license file" error.
Xilinx Answer #2223 : M1.4 Cadence Concept interface: Frequently asked questions
Xilinx Answer #2224 : VERILOG-XL: Error! Module (...) has a `timescale directive but previous modules do not
Xilinx Answer #2226 : M1: Difference between FEATURE and INCREMENT line in license.dat file
Xilinx Answer #2227 : M1: Design Manager help ->ld.so.1:hyperhelp:fatal:libXmu.so.4:can't open file: errno=2
Xilinx Answer #2229 : PROM File Formatter 6.0.1: Page Fault (illegal operation) during Save PROM Operation
Xilinx Answer #2230 : FPGA Express: Using RLOC_ORIGIN with Express RPMs
Xilinx Answer #2232 : M1.2.11 MAP: FATAL_ERROR:x4kma:x4kmabel.c:161:1.37 - Didn't find out signal on bel G
Xilinx Answer #2233 : SYNPLIFY: Why aren't Unified Library names used in the XNF?
Xilinx Answer #2234 : M1.5, M1.4 MAP/NGDBUILD, LogiBLOX: Pin mismatch between block ... at pin ....
Xilinx Answer #2235 : M1 LOGIBLOX: LogiBLOX Memfile will not accept all Memgen conventions
Xilinx Answer #2236 : PROMS: Differences between XC1700 and XC1700D PROMs
Xilinx Answer #2237 : M1.4, M1.3 LOGIBLOX: LogiBLOX core dumps with Illegal Instruction on a HP-UX 9.07
Xilinx Answer #2238 : M1.3 LOGIBLOX: LogiBLOX "Simple Gates" options have invalid Styles in menu
Xilinx Answer #2239 : M1.5 LOGIBLOX: LogiBLOX will not always "Stop on Warning"
Xilinx Answer #2240 : M1.5/M1.4/M1.3 LOGIBLOX: LogiBLOX warnings are not indicated in NGDBUILD summary
Xilinx Answer #2241 : ** OBSOLETE ** M1.5 LOGIBLOX: LogiBLOX will not save vendor information for vendor "Other"
Xilinx Answer #2242 : M1.5/M1.4/M1.3 LOGIBLOX: LogiBLOX will not accept a memfile without a file extension of ".mem"
Xilinx Answer #2243 : M1.3/M1.4/M1.5 CPLD: Fitter takes more than 200 Megs of RAM while fitting a design
Xilinx Answer #2244 : NGD2EDIF M1.3: WARNING:basnu - This design contains the undriven net "<net name>"
Xilinx Answer #2245 : M1 (FPGA/Design Compiler): Versions of Synopsys compatible with the Xilinx Alliance software
Xilinx Answer #2246 : M1.3 JTAG Programmer: Doesn't check to make sure proper 9500 device package is used
Xilinx Answer #2248 : Design Manager M1.3/M1.4/M1.5: Configuration Template does not contain option for creating MASK file
Xilinx Answer #2249 : M1 MAP, XC4000EX CCxxCLE counter library macros: WARNING:x4kma - Signal xxx on pin G4 of CY4 symbol is not required by carry mode INC-F-CI
Xilinx Answer #2250 : M1.3/M1.4 JTAG Programmer: Unnamed device added to chain if you Cancel from Add Device
Xilinx Answer #2252 : M1.3: Failure to program a 9500 device on Windows NT using the JTAG cable
Xilinx Answer #2254 : FPGA Express: warning given: "'xxx/GC' (or /GS) is not connect to any net..."
Xilinx Answer #2255 : M1: Concept HDL Direct gives "Error#171: Port exists in entity declaration..."
Xilinx Answer #2256 : NGDBUILD: WARNING:basnu:11 - Ignoring unexpected data value "true" on "FAST" property
Xilinx Answer #2257 : Design Manager M1.3/M1.4/M1.5/i: The User Constraint File (design.ucf) is used even if not specified
Xilinx Answer #2258 : M1.3(FPGA Compiler)-Common issues/solns when re-compiling M1.3 XSI XDW libraries
Xilinx Answer #2260 : M1 MAP: Running map with -os area may yield a larger implementation than with -oe normal
Xilinx Answer #2261 : 1.3 JTAG Programmer - Only Parallel cable seen if both Xchecker and Parallel cables connected
Xilinx Answer #2262 : Design Manager: The difference between "Version" and "Revision"
Xilinx Answer #2264 : NGDBUILD: Launcher: NOT compiling module.ngo because its source was not found
Xilinx Answer #2266 : Flow Engine M1: Text in status window flickers during compile
Xilinx Answer #2267 : FPGA Express: Deleting Multiple Files from the Express Project Window
Xilinx Answer #2268 : Concept2xil causes NGDBUILD to issue "ERROR:based:48-..Duplicate port a in cell "alias_bit".
Xilinx Answer #2270 : FPGA Express v1.1: Does not allow Verilog parameters used as indices for arrays
Xilinx Answer #2271 : Hardware Debugger M1.3: Verify Bitstream finds bits mistched.
Xilinx Answer #2272 : Flow Engine M1: Flow Engine log (fe.log) area is truncated at the top
Xilinx Answer #2273 : M1.3/M1.4 JTAG Programmer: Files are "missing" when programming across platforms
Xilinx Answer #2274 : M1 MAP: Designs which fit a target XC4000/E/L device in XACT may not fit when mapped with the M1 Mapper due to register ordering
Xilinx Answer #2275 : FPGA Express 2.x: Undefined macro 'ifdef, VE-0
Xilinx Answer #2276 : NC-VERILOG: ncelab: *F,CUMSTS: Timescale directive missing on one or more modules.
Xilinx Answer #2277 : Design Manager M1: How to change background colors from grey to white on workstations
Xilinx Answer #2280 : M1.3/M1.4 Map: Map fails to pack RLOC'd carry logic in RPMs (Relationally Placed Macros) with LOC'd DFFs.
Xilinx Answer #2281 : M1.5/M1.4/M1.3 MAP: Automatic insertion of GSR/GR is not supported in M1.
Xilinx Answer #2282 : FPGA Express: Individual bits of a bus cannot be used as clock signals
Xilinx Answer #2283 : HDL timing simulation: compiling testbench reveals port mismatches
Xilinx Answer #2284 : Design Manager M1: Design Manager does not start/come up when I double-click the icon (PC)
Xilinx Answer #2286 : Hardware Debugger M1.3: Download, Verify, and Debug menu commands are not executed.
Xilinx Answer #2287 : FPGA Express: Opening up Express to an Existing to a User Default Location
Xilinx Answer #2288 : M1.5/M1.4/M1.3 MAP: BEL-level PROHIBIT constraints are not supported
Xilinx Answer #2289 : 1.5i MAP, XC4000E/L/EX/XL: Map cannot use the DI input to source an HMAP (xc4000e/ex/xl)
Xilinx Answer #2291 : M1.3 MAP: Unable to pack CLB driven by 2 external signals with DFFs sharing an SR signal.
Xilinx Answer #2293 : Hardware Debugger M1.3: Cannot print Macro files.
Xilinx Answer #2295 : M1.3 MAP: Version number of Mapper is not reported in the .MRP report file
Xilinx Answer #2296 : 2.1i JTAG Programmer - ERROR:basut - no functional test vectors in JEDEC file
Xilinx Answer #2298 : M1.3/M1.4 MAP may generate Wide Decoder groups that cannot be placed/routed.
Xilinx Answer #2300 : Hardware Debugger M1.3: DEBUG menu commands not executing.
Xilinx Answer #2301 : M1.3 MAP: ERROR:x4kma:312 - Unable to obey design constraints which require the combination...
Xilinx Answer #2302 : M1: How to find the C Vol Serial Number and ethernet address?
Xilinx Answer #2303 : 1.3 JTAG Programmer: Software will allow Verify of Read-Protected device in SVF mode
Xilinx Answer #2306 : M1.x: EPIC: Changing the design mode to "Read Only", "Read/Write", or "No Logic Changes"
Xilinx Answer #2307 : M1.3/M1.4 CPLD: Fitter issues spurious nd14 warnings
Xilinx Answer #2308 : M1.3 MAP: Map doesn't validate PROHIBIT constraints before writing them out.
Xilinx Answer #2309 : 1.5i Map - MAP does not report which TIMESPEC is used when there are duplicate TIMESPECs
Xilinx Answer #2310 : Hardware Debugger M1.3: Debug operations do not affect target board.
Xilinx Answer #2311 : Synopsys vhdlan: Common issues/solutions re-compiling the M1.3/M1.4 XSI simulation libraries
Xilinx Answer #2312 : 1.5i, 2.1i 4K* Map - 'ERROR: baste:125 - The RLOC value of "R62C2.FFY" on CLB .... in RPM ....'. The design is too large for the given device and package (can't fit design).
Xilinx Answer #2313 : Hardware Debugger M1.3: Waveform Signal Display window scrolls do not function properly.
Xilinx Answer #2315 : Timing / Flow Engine M1: Using a user-modified PCF file
Xilinx Answer #2317 : ** OBSOLETE ** M1.3 MAP: The design summary section of the map report file (.mrp) is ambiguous.
Xilinx Answer #2319 : ** OBSOLETE ** M1.3 MAP gives misleading error: ERROR:0 - BLKNM parameter not supported on WAND symbol
Xilinx Answer #2322 : Hardware Debugger M1.3: Display Signals window displays all "tied" signals.
Xilinx Answer #2323 : Hardware Debugger M1.3: Uppercase MACRO commands are invalid.
Xilinx Answer #2325 : Design Manager/Flow Engine M1: Crashes during cut and paste
Xilinx Answer #2326 : Flow Engine M1: Can not generate back-annotated XNF files for XC7000 or XC9000 devices
Xilinx Answer #2327 : M1 CPL: PWR_MODE attribute cannot be placed on non-logic symbols
Xilinx Answer #2328 : 2.1i/1.5i Design Manager/Template Manager: How to enable Express Mode Configuration Option for the SpartanXL Family
Xilinx Answer #2329 : M1 Xilinx Design Manager - Abel is not a valid file entry format
Xilinx Answer #2331 : M1 NGDBUILD: ERROR:basts:68 - NET...which has a NET OFFSET...not pad-related...
Xilinx Answer #2332 : 1.5i Map: How to ignore RLOCs / Map does not have a built-in ability to ignore RLOCs completely (or, the meaning of the MAP "-ir" option)
Xilinx Answer #2334 : M1.3/M1.4 CPLD: Fitter warning xr5100 - Inserting an output buffer
Xilinx Answer #2335 : Hardware Debugger M1.3: Cable Self Check fails or doesn't run specified number of cycles.
Xilinx Answer #2336 : M1.3/M1.4 : 9500 : Hitop: Fitter warning xr5049 - invalid 'BUFG' parameter
Xilinx Answer #2337 : 1.5i, 2.1i Map - "place instance *" constraint causes ERROR:x4kma:148 - IBUF symbol cannot be merged, incompatible site types
Xilinx Answer #2338 : EZtag: SVF file generation mode does not work when data security is enable.
Xilinx Answer #2339 : M1.5i/2.1i; CPLD: TIG (Ignore Timing) timing constraint not supported
Xilinx Answer #2340 : Hardware Debugger M1: No popup-menu for the console window.
Xilinx Answer #2341 : M1.3/M1.4 CPLD: Fitter does not recognize the vcc labelled net as a special net name
Xilinx Answer #2342 : M1.3 JTAG Programmer: Output -> Cable Setup breaks cable connection
Xilinx Answer #2343 : DATA I/O / Synario: SUPPORTS XC9500 family devices
Xilinx Answer #2345 : M1.3 MAP: "Unable to obey design constraints" errors / Unsupported CLB combinations involving dual output logical components (DPRAM, RAM16x2)
Xilinx Answer #2346 : Hardware Debugger M1.3: "Signal List is Empty" when Displaying signals from Console.
Xilinx Answer #2347 : Hardware Debugger M1: Missing newline charactor when reading UNIX macros in Win95 or WinNT4.0
Xilinx Answer #2348 : Design Manager M1: Report Browser can't open reports after Design Implement
Xilinx Answer #2350 : Hardware Debugger M1: Changing the color of the wavforms in the waveform window
Xilinx Answer #2351 : Hardware Debugger M1.3: "Need to define some signals to display" from Pulse RESET.
Xilinx Answer #2352 : M1.3: JTAG Programmer Error Message when downloading with device in bypass mode
Xilinx Answer #2353 : Hardware Debugger M1.3, M1.4 :Hardware debugger features, eg download, not available on command line
Xilinx Answer #2355 : Hardware Debugger M1.3: Available signals list do not follow bit order.
Xilinx Answer #2356 : Hardware Debugger M1: Can not communicate with non-standard port names
Xilinx Answer #2357 : Hardware Debugger M1.3: Console command "port auto" doesn't work on win95 and NT4.0
Xilinx Answer #2359 : Flow Engine M1: Multi-Pass Place & Route summary report not shown until completion
Xilinx Answer #2360 : Flow Engine M1: ERROR: basut -switch "-l" is excluded or already used
Xilinx Answer #2361 : Flow Engine M1: ERROR: basut -Argument"../xc4000ex.ngd" has an invalid extension.
Xilinx Answer #2362 : M1.3 MAP: What do "Clock IOBs" mean in the MAP report ?
Xilinx Answer #2363 : 1.5i MAP: How can I estimate the total number of packed CLBs in my design?
Xilinx Answer #2364 : 1.5i 4K* Map - "ERROR 0 - FMAP symbol - RLOC parameter suffix doesn't match block type" on single-flip-flop macros
Xilinx Answer #2366 : 1.5i 4K* Map - ERROR: BLKNM parameter not supported on WAND symbol (4K family)
Xilinx Answer #2367 : M1.3 MAP: MAP DRC does not check the validity of RLOC and LOC location constraints on fast carry logic
Xilinx Answer #2370 : SYNPLIFY: How to preserve instances with unused outputs using the syn_noprune attribute?
Xilinx Answer #2371 : A schematic may be written despite error from reserved names used in design
Xilinx Answer #2372 : xc3000/XC4000E/EX/XL/XC5200: Output capacitance is same as input capacitance.
Xilinx Answer #2373 : VERILOG-XL: Error! Identifier (glbl) not defined [Verilog-IDNOD]
Xilinx Answer #2374 : Timing error reported for both flop and RAM, but only applies to RAM
Xilinx Answer #2375 : NGDANNO uses the max value only when different drivers drive the same net
Xilinx Answer #2379 : SYNPLIFY: How to lock down I/O pins in HDL (Verilog/VHDL)?
Xilinx Answer #2380 : M1.3 JTAG Programmer: Programming a 9500 device fails intermittently on a Solaris machine
Xilinx Answer #2381 : --OBS--Timing Analyzer: Sun - Using middle mouse button to copy & paste closes application
Xilinx Answer #2382 : --OBS--Timing Analyzer: Using arrow keys to execute previous commands does not work
Xilinx Answer #2383 : --OBS-- Timing Analyzer: "Macro /tmp/xil_922 failed" - what does this mean?
Xilinx Answer #2384 : --OBS--Timing Analyzer: Can I insert comments into macros?
Xilinx Answer #2385 : --OBS---Timing Analyzer: Expected one number greater than or equal to 0.000000
Xilinx Answer #2386 : FPGA/CPLD: Do FPGA and CPLD inputs have Hysteresis?
Xilinx Answer #2387 : vhdldbx: Error vhdlsim, 259 sdf file line ##: instance xsim4 not found.
Xilinx Answer #2388 : M1.2-WS: Why doesn't the M1 license.dat list the xc9500 in the Components section?
Xilinx Answer #2389 : --OBS--Timing Analyzer: TIMINGAN caused an invalid page fault in module LIBBASTW.DLL
Xilinx Answer #2390 : Foundation: Btrieve 12 : Lmacs, cannot find the specified file (*.HDR)
Xilinx Answer #2391 : --OBS--Timing Analyzer: When selecting sources/destinations, everything is grayed out
Xilinx Answer #2393 : --OBS--Timing Analyzer: Using Shift F8 to select items in dialogs does not work
Xilinx Answer #2394 : --OBS-- Timing Analyzer: After applying a filter in a dialog, how do I un-apply it?
Xilinx Answer #2395 : --OBS--Timing Analyzer: What does "Filter for <items> Not to be Selected" mean?
Xilinx Answer #2396 : --OBS-- Timing Analyzer: Keyboard shortcut for File -> Open Physical Constraints changes
Xilinx Answer #2397 : M1.3 MAP: User-defined TIMESPEC constraints added outside the "SCHEMATIC" section of the .PCF file are commented out by MAP
Xilinx Answer #2398 : PAR M1.5 - PAR appears to ignore soft range constraints
Xilinx Answer #2399 : PAR M1.3 - PAR placement rules are too strict for comps driven by BUFGE.
Xilinx Answer #2403 : PAR M1.3 - PAR may fail if an RLOC_RANGE overlaps an RLOC.
Xilinx Answer #2405 : PAR M1.3 - PAR may fail with segmentation fault processing offset constraints.
Xilinx Answer #2407 : PAR M1.X - PAR may crash if guided place and route is mixed with re-entrant routing.
Xilinx Answer #2408 : PAR M1.X - XC4000E designs ported to XC4000XL may have unroutable carry chains.
Xilinx Answer #2411 : COREGEN: Latency of the Variable Multiplier core
Xilinx Answer #2413 : MAP: "ERROR:x4kma-Unable to obey design constraints" with Synplify netlist
Xilinx Answer #2415 : FPGA Express v1.2: LogiBLOX in the FPGA Express v1.2 Verilog or VHDL M1.3 Flow
Xilinx Answer #2416 : M1.4: How to auto-start a floating license on the PC?
Xilinx Answer #2417 : SYNOPSYS: Logical Library does not map to a host directory.
Xilinx Answer #2418 : M1: MAP->"FATAL_ERROR:baste:bastetspec.c:908:1.64 - No pins of NC_SIGNAL ... NC_BEL
Xilinx Answer #2419 : Design Manager/Flow Engine M1: Screen turns black when Flow Engine is invoked on W95/NT
Xilinx Answer #2423 : XC5200: What is the delay setting for the IOB when driving logic instead registers?
Xilinx Answer #2424 : Readback: Performing verification of FPGA configuration while ignoring RAM and FF contents
Xilinx Answer #2426 : Foundation Simulator: high impedence on output of OSC4
Xilinx Answer #2427 : Hardware Debugger: Polarity of Reset signal is active low.
Xilinx Answer #2428 : What is HMGEN?
Xilinx Answer #2430 : Design Manager 6.0.1: Screen goes black during Translate. (DOSGRAB in Win95)
Xilinx Answer #2431 : M1: Powerview/Viewdraw->"vscript: Error 4307: logiblox.vs: Unbound variable-RequireFac"
Xilinx Answer #2432 : NGD2VER: What is needed to do Verilog simulation of 3rd party designs using Xilinx Alliance software?
Xilinx Answer #2435 : M1.5i/2.1i: TRCE/Timing Analyzer: 0 paths analyzed for a TIMESPEC which should have paths
Xilinx Answer #2436 : PPR 5.2.1: error 11221: design name 12345 is illegal
Xilinx Answer #2439 : M1.3 XIL2CDS: ERROR : get_pwr_pin_name -- invalid pin # - '24' on target BGA package
Xilinx Answer #2443 : TRCE M1.3: Paths that include RAMs deeper than 16 address cells not analyzed.
Xilinx Answer #2444 : Hardware Debugger 6.0.1/M1: What points can I probe during in-circuit debugging/readback?
Xilinx Answer #2445 : M1: Win95/NT license, lmutil lmhostid returns hostid of 0 or FFFFFFFF
Xilinx Answer #2446 : FPGA Configuration: Async Periph mode, RDY/BSY state when DONE is held low.
Xilinx Answer #2449 : Basic UCF Syntax Examples for Design Placement and Timing Constraints
Xilinx Answer #2452 : M1.2.11 95288 report file contains additional pins as GND not listed in the databook
Xilinx Answer #2457 : M1.2 MAP: Input flip-flops in a bidirectional I/O get removed due to optimization of an output flip-flop whose input is tied to GND.
Xilinx Answer #2459 : PPR error 1476 :error in mxn file:Illegal mxn name on line <> of file <> in data high.pb
Xilinx Answer #2461 : ** PROMs: Does makeprom have the s-records file format?
Xilinx Answer #2462 : HITOP M1.2.11: nd7331 - Input 'sclk_int' assigned to FCLK1 is used in logic.
Xilinx Answer #2463 : Replacement for the 1700DDD8R (Obsolete) is the 1700DDD8B
Xilinx Answer #2469 : 9500 EZtag download gives error 126: unsupported command
Xilinx Answer #2472 : Hardware Debugger: Setting up printer on Unix Workstations
Xilinx Answer #2473 : Hardware Debugger: Printing and Print Preview causes Illegal Instruction or Application Error
Xilinx Answer #2474 : M1 LOGIBLOX: How to estimate CLB,/area/resource utilization for LogiBLOX modules with Map
Xilinx Answer #2476 : UNISIMS: GSR/GTS behavior does not simulate with STARTUP_VIRTEX Verilog model.
Xilinx Answer #2478 : M1 QuickHDL: How to compile the HDL simprim, LogiBLOX, Unisim, and Coregen libraries (VHDL and Verilog)
Xilinx Answer #2479 : M1.3 install: cp: cannot create /tmp/xilinx/./perl.sol: Permission denied
Xilinx Answer #2480 : M1.3: NODELAY Attribute may be ignored in .ucf file without warnings or errors.
Xilinx Answer #2483 : M1.2/M1.3/M1.4 MAP: Refsite is unavailable / Constraining overlapping RPMs to the same CLB range (RPM "zippering") is not supported
Xilinx Answer #2484 : Foundaton Simulator: 'assign' in command file gives incorrect state value.
Xilinx Answer #2485 : M1 QVHCOM: Could not open library simprim/logiblox/unisim, unknown identifier
Xilinx Answer #2492 : MAP Error: ld.so.1: map: fatal: relocation error: symbol not found:
Xilinx Answer #2493 : M1: Using the MYXILINX environment variable, correcting ld.so errors
Xilinx Answer #2494 : M1: Debugging problems while using Install Shield
Xilinx Answer #2495 : FPGA Express 3.x: No MUX_OP inferred for the case (HDL-380)
Xilinx Answer #2496 : MAKEBITS 5.2.1: Problem with xc5200 devices when Makebits -t option is used.
Xilinx Answer #2498 : HW-130: Cannot reconfigure programmer
Xilinx Answer #2499 : M1.3/A1.4: UNIX environment setup for SunOS, Solaris, and HP using C-shell (csh) or KornShell (ksh).
Xilinx Answer #2500 : SYNOPSYS FPGA/Design Compiler: How to constrain I/O pins in Synopsys designs (I/O pin locking)
Xilinx Answer #2501 : M1: NOCLIP, S, NOMERGE, X and KEEP properties
Xilinx Answer #2502 : XC5200: 5206- Incorrect pinouts for any parts with daycode earlier than 9620
Xilinx Answer #2503 : PG475 - 475 pin ceramic PGA physical dimension drawing
Xilinx Answer #2504 : PAR: WARNING:basdp - The SITE "pin-out" specified in the .PCF file was not found in desgin
Xilinx Answer #2505 : Mixed Voltage Systems: Interfacing 3.3 Volt and 5 Volt devices.
Xilinx Answer #2508 : SYNPLIFY: How to infer Virtex Block SelectRAM+ using the syn_ramstyle attribute?
Xilinx Answer #2509 : Foundation XVHDL: Cannot instantiate the XBlox TRISTATE component without pullups.
Xilinx Answer #2510 : Flow Engine M1: "object disconnected from client" in Flow Engine (RPC Unavailable)
Xilinx Answer #2511 : Workview Office: How to label incrementing/decrementing bus signals
Xilinx Answer #2516 : Exemplar Galileo/Leonardo EDIF files prior to version 4.1.3 are not M1 compatible
Xilinx Answer #2517 : Exemplar: How to instantiate a pullup or pulldown (Galileo and Leonardo) in VHDL
Xilinx Answer #2519 : Programmers: hw-130 Adapters and supported devices.
Xilinx Answer #2520 : Bitgen 1.2: BUFGP sourced from internal logic may produce incorrect bitfile.
Xilinx Answer #2525 : M1.2/M1.3 Design Manager: Object has disconnected from its client
Xilinx Answer #2526 : What are the differences between C,I, M and B products in a package?
Xilinx Answer #2527 : XC4000E: Clarification about the IOB diagram specified on the data book
Xilinx Answer #2529 : XC4000E/EX/XL: The 4KE devices are not bitstream compatible to their equivalent 4KEX/XL devices
Xilinx Answer #2530 : XC4000EX/XL: The 4000EX devices are bitstream compatible to their equivalent 4000XL devices
Xilinx Answer #2531 : Workview Office Viewdraw: "file is locked" while editing schematic.
Xilinx Answer #2532 : Hardware Debugger: Current design does not have RDBACK block connected.
Xilinx Answer #2533 : NGD2VER: How are escaped names handled using the -ne option?
Xilinx Answer #2536 : M1.2, Workview Office: EDIFNETI reports unconnected ports reading TIME_SIM.EDN
Xilinx Answer #2537 : Foundation: Can not load/open Foundation after renaming drive, susie.ini
Xilinx Answer #2538 : CPLD: 9500 - How to invert the global set/reset pin
Xilinx Answer #2539 : M1.3 Installation: Operating System, Memory (RAM), Swap Space and Disk Space Requirements for Targeting Xilinx Devices
Xilinx Answer #2542 : M1: FATAL ERROR BASUT: cname.c:102:1.6 reference count overflow
Xilinx Answer #2544 : bitgen: WARNING:x4kdr - netcheck: no load pins found on signal
Xilinx Answer #2546 : V1.4.0 CORE Generator: Viewlogic Synthesis Flow (VHDL only)
Xilinx Answer #2547 : M1.x: license.dat - basic basnb security errors: (-1,73:2), (-5,116:2), (-2,134:2), (-15,10:10061), (-9,57:2), (-8,130:2), (-15,12:146), (-31,34:2) , (-34,147), (-15,9:1)
Xilinx Answer #2548 : FPGA Configuration: EXPRESS MODE Does Not Work in XC4000EX/XL/XLT FAMILIES.
Xilinx Answer #2551 : PROMs: What are the SMD numbers for 1700d family.
Xilinx Answer #2552 : Eztag: Error 203 Syntax error in bit file
Xilinx Answer #2554 : NC-VERILOG: How to compile the 2.1 Verilog Simprims, LogiBLOX, Unisims, and Coregen libraries?
Xilinx Answer #2556 : M1 Install - Installing M1 software for use with multiple work station platforms.
Xilinx Answer #2558 : M1 VERILOG/VHDL: CLB Flip-flops and latches may have zero setup delay in an SDF netlist for a routed design
Xilinx Answer #2559 : Design Manager M1.3: fatal relocation error: symbol not found: _ex_keylock
Xilinx Answer #2560 : M1: Board-level schematic simulation methodology for QuickSim
Xilinx Answer #2561 : MODELSIM (MTI): How to compile the 2.1 Simprim, LogiBLOX, Unisim, and Coregen HDL libraries?
Xilinx Answer #2565 : M1 DESIGN MANAGER: Wind/U Error (188): Cannot load font set from specification: -adobe-helvetica-medium-r-normal-*-14-*
Xilinx Answer #2566 : Hardware User Guide M1: Incorrectly refers to litefpga design.
Xilinx Answer #2568 : Design Manager M1.5i: Using a User Rules File to add command line switch to netlist reader.
Xilinx Answer #2569 : M1.2/M1.3/M1.4 PAR (MAP): CLB Pin locking is not supported
Xilinx Answer #2570 : M1 CONSTRAINTS: How to specify SAVESIG ("S"), "KEEP", or "X" constraints on nets using a UCF file.
Xilinx Answer #2571 : PROMs: What is the unprogrammed/default state of each byte address in an XC1700 PROM?
Xilinx Answer #2573 : NGD2VER: How to retain design hierarchy in a Verilog simulation netlist generated by NGD2VER
Xilinx Answer #2574 : Foundation XVHDL: How to use READBACK in a VHDL design
Xilinx Answer #2575 : **CPLD : EZtag: "Input passed end of file" message when programming 9572 CPLD
Xilinx Answer #2576 : Cable - Parallel Cable III and Xchecker Cable specs and dimensions for lead connectors and posts
Xilinx Answer #2578 : PAR/FOUNDATION Beta2/Win95: PAR gives "ERROR: FATAL:basut: basutdtime.c:60:1.5 time failure:
Xilinx Answer #2579 : CPLD : 9500: How to utilize the Wired-AND (WAND) in the UIM
Xilinx Answer #2580 : M1.x EPIC: Page Fault in Module LIBBASTW.DLL, Illegal operation, Kernel32 error
Xilinx Answer #2581 : Design Architect: Can the generic libraries (gen_lib) be used to in Xilinx schematics?
Xilinx Answer #2582 : M1.5: Timing Analysis reports 0 items analyzed for IOB flops, IFD, OFD
Xilinx Answer #2583 : PAR 1.4: ERROR: x52ap:111 5200 Design uses to many TBUF's or BUFT's
Xilinx Answer #2584 : Hitop: hi12:[Error]Keyword PIN_FREEZE:servo_cpu_decoder.gyd in the CTL file is invalid.
Xilinx Answer #2585 : XC1700D: Driving inputs when VCC is down should be avoided
Xilinx Answer #2586 : 2.1i: CE/Timing: VIRTEX CLKDLL TIMING for 2.1i
Xilinx Answer #2591 : Foundation XVHDL, F1.3/F1.4: Bidirectional pins must be described in top-level entity
Xilinx Answer #2593 : Foundation XVHDL, NGDBUILD: ERROR: basnu - logical net "net_name_int" has both active and tristate drivers
Xilinx Answer #2594 : Foundation XVHDL, F1.3/F1.4: Do not use 'Macrocell' attribute when instantiating Logiblox
Xilinx Answer #2595 : Foundation XVHDL, F1.3/F1.4: How to instantiate Logiblox components
Xilinx Answer #2596 : Foundation XVHDL, F1.3/F1.4: Hardware key required for XVHDL feature (Programmable C Key)
Xilinx Answer #2599 : Foundation: How to use both XACT6-based and M1-based flows with Foundation
Xilinx Answer #2600 : Foundation: Where to find old Foundation 6.x libraries
Xilinx Answer #2602 : Foundation F1.x: Bus pin names are not visible on Logiblox components
Xilinx Answer #2603 : F1.x Logiblox: Do not change Logiblox symbol parameters on Foundation schematic
Xilinx Answer #2606 : Foundation XVHDL F1.3/F1.4: VHDL compiler synthesizes design twice
Xilinx Answer #2609 : XC4000XL: some devices have a higher VCC pin to GND pin ratio
Xilinx Answer #2610 : Hardware Debugger M1.2: FATAL_ERROR:baspm:baspmdlm.c:174:1.17
Xilinx Answer #2619 : M1.37 ngdbuild - ERROR:bascp - Could not find NET 'NET entry is '%s'
Xilinx Answer #2620 : Foundation Simulator: How can I use a Formula to assign Z to a bus?
Xilinx Answer #2621 : Foundation State Editor: E:#002 Syntax error near "<="
Xilinx Answer #2625 : How to calculate sample rate for SDA filters.
Xilinx Answer #2628 : Prom File Formatter M1.3:Adding 3000, 5200, 4000 devices to daisy chain or prom
Xilinx Answer #2630 : M1 : How to change speed grades (faster or slower) of your placed and routed design? How to recreate simulation and static timing models?
Xilinx Answer #2631 : M1 LOGIBLOX/XBLOX: Naming of RAM Address and Data pins differs in LogiBLOX And X-BLOX
Xilinx Answer #2632 : XC3000A, XC4000/E/X: How to implement flip-flops with both asynchronous preset and clear/reset inputs
Xilinx Answer #2633 : 2.1i PROM FILES: M1 bit mirroring and XACT bit mirroring
Xilinx Answer #2634 : OBSOLETE!!!:3000 family: Bare die, what should the backside (substrate) be connected to?
Xilinx Answer #2636 : M1 - All GUIs (except EPIC) will core dump on HP 9.05 systems at a certain patch level.
Xilinx Answer #2639 : Mentor Graphics Library for XACTstep 5.2.1: DECODE16, DECODE8, and DECODE4 library macros are missing DECODE attribute
Xilinx Answer #2641 : M1.2 MAP: Problems with map3_nt.zip patch when installed in MYXILINX directory on Windows NT and Win95 systems: FATAL_ERROR:baspm:baspmdlm.c fail to open libx4kma.dll
Xilinx Answer #2644 : M1 CONCEPT/CONCEPT2XIL: generating a symbol body for a non-schematic block, using a Verilog .v file as input
Xilinx Answer #2645 : FPGA Configuration: INIT goes low unrelated to frame error.
Xilinx Answer #2646 : Workview Office: VSM Error 222. Could not find wir file XC9000 AND2B1.1
Xilinx Answer #2647 : MAP, PAR, PPR: Constraining signals to unbonded pads in M1 and XACT (naming convention is different)
Xilinx Answer #2648 : Can I run M1 and XACTstep 6.0 software on the same machine?
Xilinx Answer #2649 : SYNPLIFY: How to change the bus-notation using syn_edif_bit_format and syn_edif_scalar_format attributes?
Xilinx Answer #2650 : CONCEPT-HDL 13.5: Sir2edif coredumps on RAMB* components
Xilinx Answer #2653 : CPLD: XC9500/XL : Power estimation for the 9500/XL family devices
Xilinx Answer #2654 : M1.3 CPLD: Synopsys set_pad_type -slewrate command causes disconnected OBUF in CPLD.
Xilinx Answer #2655 : M1 CPLD: Synopsys SCAN tutorial test bench does not initialize registers.
Xilinx Answer #2656 : M1.3.7 - XC4000XL package file patch adds new packages.
Xilinx Answer #2657 : Synopsys FPGA/Design Compiler: Error: The entity 'add_sub_ub' depends on the package 'std_logic_arith' which has been analyzed more recently.
Xilinx Answer #2658 : ** PROMS: Can you use a 1736A as a master to program a 1736D part?
Xilinx Answer #2660 : **M1.3/M1.4 CPLD: Exemplar netlists use IOBUFE which is not expanded by 9k library.
Xilinx Answer #2661 : M1.3 CPLD: Synopsys I/O ports cause xr5100 and nd201 warnings and pin name changes.
Xilinx Answer #2662 : XABEL6, Foundation F1.3/F1.4: OLE server errors when ABEL from other vendor installed (registry).
Xilinx Answer #2663 : XABEL6, Foundation F1.x: EDIF netlists from XABEL in M1/F1 are encrypted.
Xilinx Answer #2666 : MAP: The meaning of the Map packing strategy options
Xilinx Answer #2669 : M1 and XACT: How to determine device utilization of a design without placement and routing
Xilinx Answer #2673 : M1.3/M1.4/M1.5/2.1i: TIMING ANALYZER, XILINX DESIGN MANAGER, LBGUI, PROMFMTR, on Solaris: core dumps may be due to 97A Verilog XNLSPATH settings
Xilinx Answer #2676 : TERADYNE Z1800 ATE SUPPORT FOR XC9500
Xilinx Answer #2680 : M1.3/M1.4: MAP -os and -oe optimization options: When to use them (XABEL, Metamor designs), why results may not improve
Xilinx Answer #2683 : PROMGEN M1.3: M1 vs XACT 6.0.x bit swapping in HEX files.
Xilinx Answer #2684 : UNISIMS: Adding the INIT attribute to VHDL/Verilog based RAM models for RTL simulation?
Xilinx Answer #2686 : M1, ViewSynthesis: SpeedWave may have difficulty analyzing large models
Xilinx Answer #2687 : M1, ViewSynthesis: Analyzing Simprims and Unified libraries with SpeedWave
Xilinx Answer #2688 : M1, ViewSynthesis: Bus Naming and Post-place-and-route Bus Reconstruction
Xilinx Answer #2689 : ViewSynthesis: Flow for black box instantiation
Xilinx Answer #2691 : --OBS--M1.3.7 Timing - XC4000E speed file patch available that correct three problems
Xilinx Answer #2692 : Error: unable to open symbol template file. Logiblox: /sim/datareg0.1
Xilinx Answer #2695 : 2.1i COREGEN, NCO: "WARNING: ...XilinxCoreLib/ncovht.vhd(xx): Function get_factor may complete without a RETURN"
Xilinx Answer #2697 : Bitgen M1.3.7: Device correctly configures but some I/O's do not oscillate.
Xilinx Answer #2699 : Workview Office: How to install Sentinel driver for Windows NT 4.0 (error 8037)
Xilinx Answer #2700 : 1.5i MAP ERROR:basnu - logical block "core/data" of type "INC_DEC_TWO_COMP_6" is unexpanded.
Xilinx Answer #2703 : NGD2VER/NGD2VHDL: How to create HDL simulation files using Alliance Software for FPGAs?
Xilinx Answer #2704 : M1 CPLD: How does the CPLD Auto Device Selection Work
Xilinx Answer #2706 : CPLD DATA BOOK: Jan. 97 edition: The pinout for the 95144 PQ160 package is incorrect
Xilinx Answer #2707 : JTAG BSDL - Is there a generic BSDL file for bypassing non-Xilinx devices with JTAG Programmer?
Xilinx Answer #2709 : DTEXT: Error in file Dynatext.ini. full.lic cannot be located
Xilinx Answer #2710 : How to find the amount of on chip resources used by M1 Implementation software.
Xilinx Answer #2711 : XC4000XL: he pin C8 of xc4044XL BG352 can't be mapped by m1.3.7,
Xilinx Answer #2712 : How to analyze the resources a module or partially completed design consumes?
Xilinx Answer #2713 : SYNPLIFY: How to instantiate a pre-optimized (black-box) netlist (XNF, EDIF, NGC, COREGEN, LOGIBLOX) file in HDL (Verilog/VHDL)?
Xilinx Answer #2714 : M1.3.7-pc: map FATAL_ERROR:basnc:basncsignal.c:262:1.61 - could not find a bel for a signal on pin G2
Xilinx Answer #2715 : PEARL: Support for Cadence's Affirma Pearl Timing Analyzer?
Xilinx Answer #2716 : M1.3/M1.4 CPLD: How to create timing simulation netlist in the XNF format
Xilinx Answer #2717 : CPLD: XC9500/XL : How to control Power Consumption in a CPLD
Xilinx Answer #2719 : CPLD: 9500/XL: How to lock the pins on a CPLD
Xilinx Answer #2720 : PAR M1.3: baspl:291,292 - pullup could not be placed
Xilinx Answer #2721 : Workview Office 7.31: ViewDraw not installed; license-based installer does not work
Xilinx Answer #2722 : Foundation F1.3/F1.4, XVHDL: I/O flip-flops not inferred by VHDL synthesizer
Xilinx Answer #2723 : FPGA Express: Program does not start after double-clicking on icon
Xilinx Answer #2724 : M1.3: FATAL_ERROR:baspm.baspmdlm.c:99:1.17 - dll library <mtrne> does not exist.
Xilinx Answer #2726 : XBLOX: ACCUM - effects of LOAD on C_OUT and OVFL
Xilinx Answer #2727 : M1.3.7 Hitop error: Hitop caused an invalid page fault in module HITOP.EXE at 0137-00436952
Xilinx Answer #2728 : TRCE: How to analyze overall timing constraint performance
Xilinx Answer #2729 : CPLD: 9500/XL : How to control Logic Optimization in a CPLD
Xilinx Answer #2730 : How to connect unused 9500 outputs to known levels
Xilinx Answer #2731 : M1.3 CPLD: taengine - Assertion failed: !i->RetOutput(iot,ZeroIfNew)
Xilinx Answer #2732 : CPLD: XC9500/XL: How to control Timing in a CPLD
Xilinx Answer #2734 : FPGA Express/M1.3: HDL Simulation of HDL only designs synthesized with FPGA Express
Xilinx Answer #2735 : M1.3/1.4 and FPGA Express: M1 Constraints, LogiBLOX, and modules within FPGA Express
Xilinx Answer #2736 : Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc.
Xilinx Answer #2737 : Foundation F1.3/F1.4, XVHDL: How to simulate VHDL designs with instantiated XNF files
Xilinx Answer #2738 : M1.3/FPGA Express v1.2: Modular (Black-Box) Instantiation in Express
Xilinx Answer #2739 : XCHECKER: What should the RST pin be connected to in XC4000 or XC5200 devices?
Xilinx Answer #2740 : TRCE: How to analyze (the longest) nets/paths in timing constraints
Xilinx Answer #2741 : --OBS--M1.3 4kex Timing - Long delays are calculated for TBUFs driving long lines with Pullups.
Xilinx Answer #2742 : How to analyze the delays for a specific path using M1 software?
Xilinx Answer #2744 : Can the Copper Heatsink on the HQ packages be grounded?
Xilinx Answer #2745 : Packages: Some BG256 packages have the (4 x 4) Ground ball matrix.
Xilinx Answer #2746 : Foundation XVHDL: Synthesis error "Wrong number of fields bus on line #__ in .xas file"
Xilinx Answer #2747 : Foundation Schematic: Can I add my own company logo to a Foundation schematic onto the border or table?
Xilinx Answer #2748 : FPGA Configuration: ALL I/O (including DONE) Tristate during configuration.
Xilinx Answer #2749 : M1 ngdbuild error: ngdbuild.exe -entrypoint not found
Xilinx Answer #2750 : VERILOG-XL: SDFA Error: Could not find path IN0 to OUT in instance ""
Xilinx Answer #2752 : M1.3.7 - CPLD patch available for several issues
Xilinx Answer #2753 : M1.3 MAP: On a bidirectional I/O, the INFF and pad are also trimmed even though only the OUTFF is dangling
Xilinx Answer #2754 : Design Manager M1.3/M1.4/M1.5/F2.1i: How to open multiple instances of the Design Manager
Xilinx Answer #2755 : Hardware Debugger 1.4: ld.so.1: hwdebugr: fatal: libbascd.so: can't open file: errno=2
Xilinx Answer #2756 : Foundation XVHDL: How to keep internal signal name so it appears in simulator
Xilinx Answer #2757 : M1.3 JTAG Programmer: Can not print on NT 4.0 parallel port printer after installing the software
Xilinx Answer #2758 : M1.3/M1.4 MAP: unclear messages about FDCEs being "covered by optimization" in the MAP .mrp file when the -os option is specified
Xilinx Answer #2759 : Foundation F1.x, Logiblox: Invalid Vendor 'fndtn' on command line. Unable to continue execution
Xilinx Answer #2760 : Are 4000XL/XV I/O Thresholds Programable to TTL or CMOS Compatibility?
Xilinx Answer #2765 : Considerations for choosing external PULLDOWN resistor values for FPGA pins.
Xilinx Answer #2766 : CONCEPT2XIL: How to obtain the Cadence Concept netlister?
Xilinx Answer #2770 : M1, CONCEPT2XIL, HDL DIRECT, CADENCE 97A: Problem with CONFIG, PART, TIMESPEC AND TNM properties not being translated to the EDIF file.
Xilinx Answer #2772 : FATAL_ERROR:basnc:basncsignal.c:262:1.61 mapping with -k switch
Xilinx Answer #2773 : CONCEPT2XIL/SIR2EDF: Error! Cannot open property file
Xilinx Answer #2774 : Installing M1.3 on a Solaris 2.4 machine may not complete sucessfully
Xilinx Answer #2776 : Foundation F1.x XABEL: How to generate .PLD (Plusasm) file from XABEL
Xilinx Answer #2777 : M1.5 PAR/EPIC: Both say that BEL doesn't exist in the NCD, but it does.
Xilinx Answer #2778 : XC3000/XC4000/XC5200: impedance IOBs pullups for different devices
Xilinx Answer #2780 : XC9500: Logic erroneously trimmed away when using HDL macros in 9k schematic design
Xilinx Answer #2781 : M1 NGDBUILD: ERROR:bascp:69 and/or WARNING:basts:19 on Mentor TIMEGRPs
Xilinx Answer #2782 : M1.3.7, M1.4.12 LOGIBLOX: rloc_orgin properties attached to Logiblox ADD/SUB modules are ignored by place and route tools.
Xilinx Answer #2783 : M1.3/M1.4 PAR: The signal "GLOBAL_LOGIC0" is not completely routed--messages about unrouted nets that are not in the input design
Xilinx Answer #2784 : How can the 4000XL/XV device talk to a 5V CMOS level device?
Xilinx Answer #2786 : M1.3 Install (Win95 CD): "Windows cannot find file setup.exe" or "Setup is unable to locate script file d:\setup.ins", error 107
Xilinx Answer #2787 : --OBS--M1.3.7 - Timing Analyzer - Number of analyzed paths changes with report paths not covered filter
Xilinx Answer #2788 : --OBS--M1.3.7 Speed Files - New speed files are available for M1.3.7 XC4000XL and XC4000EX.
Xilinx Answer #2789 : M1.3.7 Timing Analyzer - "Report Paths not Covered by Timing Constraints" feature does not work.
Xilinx Answer #2790 : M1.3.7 TRCE - Doing a TIG in the UCF file on a signal which is the output of a tristate buffer does not work.
Xilinx Answer #2794 : M1: Taengine -> abnormal program termination
Xilinx Answer #2795 : M1 License :FLEXlm error message: Invalid returned data from license server(-12,122)
Xilinx Answer #2796 : M1.3.7 Lab Install: invoke hwdebugr returns "ld.so.1 fatal: libbasfc.so can not open file errno=2"
Xilinx Answer #2798 : M1.5, M1.4, M1.3 LogiBLOX: Bus order reversed on LogiBLOX MUX macro symbols
Xilinx Answer #2799 : EDIF2NGD 1.5, 2.1: Application Error EDIF2NGD caused an invalid page fault in module EDIF2NGD.exe
Xilinx Answer #2800 : XC3000: XNFPREP 5.2.1: Segmentation Fault(core dumped)
Xilinx Answer #2801 : M1.3 GUIs: "Warning: Can't load Codeset file 'c', using internal fallback" while loading
Xilinx Answer #2803 : M1.3.7 Hardware Debugger fails during Readback/Verify on PC.
Xilinx Answer #2805 : SYNPLIFY: How to instantiate Boundary Scan (BSCAN) in HDL (Verilog/VHDL)?
Xilinx Answer #2806 : Foundation F1.3: Lmacs cannot find <project_name>.id file -- SC: LM_Put_Symbol - error #702
Xilinx Answer #2807 : Foundation F1.3: Lmacs: the record has a key field containing a duplicate key value -- Sc: LM_Put_Symbol - error #5
Xilinx Answer #2808 : M1.3.7 Map - Inverter is incorrectly pushed into a closed FMAP.
Xilinx Answer #2809 : M1.3.7 Map - Wrong LUT is connected to FF resulting in corrupt logic.
Xilinx Answer #2810 : M1.3.7 Map - FATAL_ERROR:baste:bastetspec.c:946:1.64 - No NC_SIGNAL for TECHMAP_SIG on BEL...
Xilinx Answer #2811 : M1.3.7 Map - Map fails with seg fault on a particular design
Xilinx Answer #2812 : Map M1.3.7 - Map fails with page fault when run from Design Manager for a paticular design
Xilinx Answer #2813 : M1.3.7 Map - Map incorrectly complains about .FFX RLOC property in coregen multiplier
Xilinx Answer #2814 : M1.3.7 Map - FATAL_ERROR:x4kma:x4kmamerge.c:2371:1.120 Too many signals to move...
Xilinx Answer #2815 : M1.3.7 Map - Map incorrectly configures a CIN net.
Xilinx Answer #2816 : M1.3.7 Map - Map incorrectly optimizes FDC to VCC.
Xilinx Answer #2817 : M1.3 Map - Map incorrectly handles CLB latches from Logiblox
Xilinx Answer #2818 : M1.3.7 Map - FATAL_ERROR:x4kma:x4kmacarry.c:2456:1.96 - Illegal call to swap.
Xilinx Answer #2819 : M1.3.7 Map - Map doesn't preserve the logic for Logiblox 4-bit binary down counter.
Xilinx Answer #2820 : M1.3.7 - Map swaps two bits of a bus corrupting logic
Xilinx Answer #2821 : M1.3.7 Map - Guided map operation fails with core dump
Xilinx Answer #2822 : M1.3.7 Map - FATAL_ERROR:basnc:basnccomp.c:3221:1.90.14.3 - Cannot find other bel...
Xilinx Answer #2824 : M1.3.7 Map - Map seg faults on a particular design
Xilinx Answer #2825 : M1.3.7 Map - Map doesn't pass a TPTHRU consraint to .pcf file to relax constraint
Xilinx Answer #2826 : M1.3.7 Map - Map writes bad data to .ngm file corupting simulation results
Xilinx Answer #2827 : M1.3.7 Map - Map incorrectly trims an INFF that is combined with unused OFDT
Xilinx Answer #2828 : M1.3.7 TRCE - Timing constraint does not relax period constraint
Xilinx Answer #2830 : --OBS--M1.3.7 Timing Analyzer - Patch available for four issues
Xilinx Answer #2831 : SYNPLIFY: How to force an IOB NODELAY latch or flip-flop in HDL (Verilog/VHDL)?
Xilinx Answer #2832 : M1.3: Warning: basdp: 52 / basdp: 48
Xilinx Answer #2834 : XABEL, Foundation F1.3: Internal Error 0001: assert event at line 274 in file Z:\fit\blif2net\TSOINTER.CXX
Xilinx Answer #2837 : ** OBSOLETE ** COREGEN: Rice FFT (DFT) Data Sheets
Xilinx Answer #2839 : Dynatext: How to contact Dynatext technical support?
Xilinx Answer #2841 : FPGA Configuration: SSM - DONE doesn't go HIGH if CCLK starts Low.
Xilinx Answer #2842 : Workview Office: License platform restriction errors (1055, 8031, 8052)
Xilinx Answer #2843 : FPGA Express v1.2: Script to convert EXT records to SIG records for module generation
Xilinx Answer #2844 : M1.3 and M1.4: Flexlm - all the files that is associated with flexlm 5.0
Xilinx Answer #2847 : M1 QuickHDL: VHDL/VITAL RAMs do not simulate properly or respond to stimuli on HP-UX systems
Xilinx Answer #2849 : M1.5i/2.1i: Timing Analyzer: How to save path filters for automatic processing?
Xilinx Answer #2850 : M1.3/M1.4/F1.5/F1.5i: Instructions on how to install and run the license manager standalone on win95/winNT4.0
Xilinx Answer #2851 : M1.4/M1.5: Instructions on how to install and run the license manager standalone on sun/solaris/hp workstations
Xilinx Answer #2853 : M1.x, Powerview, How to create logiblox symbols in powerview6.x
Xilinx Answer #2855 : Design Manager/Prom File Formatter/etc... M1: Segmentation Fault, Bus Error (core dump) when invoking GUI
Xilinx Answer #2858 : XC5200: Speed files are now available on the web
Xilinx Answer #2861 : ** OBSOLETE ** ALPHA v3.0.x COREGEN, FOUNDATION F1.3: problems generating Foundation symbol in Windows 95 and NT
Xilinx Answer #2863 : FATAL_ERROR:basbd:basbdbool.c:393:1.5 - Signal unassigned to variable encountered. Process will terminate. Please call Xilinx support.
Xilinx Answer #2864 : M1.4, 1.3 LogiBLOX, NGDBUILD/MAP: Warning/Error:basnu - logical block "<instance_name>" of type "<logiblox_module>" is unexpanded
Xilinx Answer #2865 : FPGA/Design Compiler: How to instantiate LogiBLOX in the Synopsys VHDL or Verilog Flow
Xilinx Answer #2866 : GSR and GTS pads don't work in SXNF netlists from Synopsys for CPLDs.
Xilinx Answer #2867 : SYNPLIFY: How to force IOB flip-flops vs a CLB flip-flops using xc_ioff?
Xilinx Answer #2870 : M1.4/M1.3 NGDBUILD, FOUNDATION. M1.4 COREGEN: ERRORS: basnu - logical net...has multiple drivers, illegal connection, no legal driver, no driver...
Xilinx Answer #2871 : Foundation F1.x, XABEL: Error:hi301 - cannot fit the design into any of the specified devices
Xilinx Answer #2872 : WARNING:baspl:291 - The TBUF component "XXX" could not be placed. (How to count the number of TBUF driven nets in a design.)
Xilinx Answer #2873 : Foundation/Viewlogic simulator does not properly simulate the CK_DIV or OSC52 symbols Error 8030 or 8031
Xilinx Answer #2874 : XACTstep wir2xnf 5.2.1 may fail with WIR files created by Powerview 6.1
Xilinx Answer #2875 : CPLD: XC9500: Maximum Icc by package type
Xilinx Answer #2876 : CPLD: XC9500: What type of drivers does the 9500 output buffers use?
Xilinx Answer #2877 : Viewsim/Viewtrace: vector is specified in command file and wfm statement but shows up as XXXX in Viewtrace
Xilinx Answer #2879 : M1.3: Windows95 Install: Installing software to run from a network drive
Xilinx Answer #2880 : WorkView Office: Viewdraw error vipc -e -1347 unable to connect to vnsd and vipc init()
Xilinx Answer #2881 : JTAG Programmer: Possible cause of Boundary Scan Chain Integrity error
Xilinx Answer #2883 : Viewlogic Pre-Unified Libraries (hm4000, mx3000, mx4000) available on the WEB/FTP site
Xilinx Answer #2884 : ** OBSOLETE ** M1.3: Map removes IBUF along with unused OBUFT in a bidirectional I/O
Xilinx Answer #2886 : M1 Design Architect: LogiBLOX fails with "newer symbol database version has been encountered"
Xilinx Answer #2887 : 2.1i/1.5i Design Manager: FPGA Multi-Pass Place and Route (MPPR) greyed out
Xilinx Answer #2888 : FPGA Express 1.2, 2.0: XC4000 Global Buffer constraints: ERROR:baste:263
Xilinx Answer #2889 : PAR: Routing pwr/gnd nets takes an extremely long time to complete
Xilinx Answer #2890 : Foundation F1.x Schematic: Symbols are removed or disappear after adding symbols. PM message symbol not added, not enough memory to complete this operation
Xilinx Answer #2891 : PAR: Error: rpc server is unavailable
Xilinx Answer #2892 : M1.4: TIMESPEC paths originating from .NMC macros (physical macros) do not get written by Map to the .PCF file
Xilinx Answer #2893 : M1.4 Map: DROP_SPEC property takes priority over other TIMESPECs regardless of where it is specified in the flow
Xilinx Answer #2895 : Foundation F1.x Schematic: How to lock down I/O pins for IPAD4/8/16, OPAD4/8/16, IOPAD/4/8/16
Xilinx Answer #2896 : M1.4: TRCE reports large delay on net driven by TBUFs with PULLUP
Xilinx Answer #2897 : The detail timing report contains some signals with a .Q extension.
Xilinx Answer #2898 : How to ignore/remove LOC constraints on PADS?
Xilinx Answer #2899 : M1: QuickSim functional simulation of a Mentor schematic with instantiated XNF (From Coregen 1.4 or other sources)
Xilinx Answer #2900 : M1.4: FATAL_ERROR:basut:basutarray.c Element out of range
Xilinx Answer #2906 : M1.4 CPLD: How to reserve a pin or a macrocell for future use?
Xilinx Answer #2910 : M1.4 CPLD: Some designs which used to fit in M1.3 failed with M1.4.
Xilinx Answer #2911 : NGDBUILD M1.4: DC2NCF is not invoked automatically for .sedif and .sxnf files
Xilinx Answer #2912 : M1.3/M1.4 NGDBUILD: ERROR:basxn:68 - The XNF file does not contain a valid PART
Xilinx Answer #2913 : M1.4 CPLD: The OFFSET timing constraint does not force the fitter to use global clocks
Xilinx Answer #2914 : ** DUPLICATE of 2337 ** M1.2/M1.3/M1.4 MAP: Map complains about incompatible site types when expanding wildcard constraints--ERROR:x4kma - IBUF symbol `$1I89' is unable to combine with IO RESET
Xilinx Answer #2915 : M1.4 MAP/PAR: PAR ERROR:baspr - SSLex0105e: Invalid token, Line 13, Offset 38, ,
Xilinx Answer #2916 : M1.x: EPIC - ERROR: baspr - A parsing error has occured at line 6, token ";"
Xilinx Answer #2917 : M1.x: EPIC - scripts->playback, ERROR:basep - Site "CLB_R1C8" is occupied.
Xilinx Answer #2921 : MAP: BUFG net attached to a BUF with an X attribute gets distributed using local routing instead of being driven directly by a BUFG
Xilinx Answer #2922 : Workview Office 7.3x: The symbol wizard in viewdraw gives a Dr. Watson vsec: Error 8002(vseccode.vmb)
Xilinx Answer #2923 : Powerview 6.0, Edif Netlist Reader V2.3: BNF Parser Error Internal stack overflow
Xilinx Answer #2924 : M1.3/M1.4: Solaris, Powerview/logiblox: lbgui process is left running after exiting ViewDraw
Xilinx Answer #2926 : ViewSim and M1.2: Loading func_sim.xmm gives error that none of the RAM instances are found.
Xilinx Answer #2930 : MAP M1.3/M1.4: "MAP = PUO" is ignored on HMAPs (HMAPs are always closed)
Xilinx Answer #2931 : NGD2VER: How to simulate the XC3000 family simulation netlists?
Xilinx Answer #2932 : What is an IBIS model, (as opposed to a SPICE model)?
Xilinx Answer #2933 : NGDBUILD: ERROR:basnb - SECURITY ERROR -- Unable to lock license for ngdbuild: No such feature exists (-5,116:2) No such file or directory.
Xilinx Answer #2935 : Converting pre-Unified library schematic designs to Unified libraries
Xilinx Answer #2937 : Foundation F1.x, XABEL 6: XABEL cannot be run from the network
Xilinx Answer #2938 : A1.4/A1.5: logical block reported as 'unexpanded' by ngdbuild
Xilinx Answer #2939 : EZTAG: Basic debugging techniques for downloading design
Xilinx Answer #2942 : 2.1i/1.5i Design Manager - My input design netlist has moved locations/drives, how do I transfer/restore my project information ?
Xilinx Answer #2943 : XIL2CDS: How to obtain the Cadence Concept board-level integration tool?
Xilinx Answer #2944 : XC9500: Can I Hot Sync my XC9500 device
Xilinx Answer #2945 : TRCE: How does TRCE calculate worst case timing values if it is unaware of the temperature grade for a part?
Xilinx Answer #2946 : M1.4: XC4000X schematic libraries must be used to target XC4000EX, XC4000XL, or XC4000XV designs
Xilinx Answer #2947 : VIEWLOGIC: Converting pre-Unified library schematic designs to Unified libraries
Xilinx Answer #2948 : M1.3 CPLD: Fitter patch causing timespecs to dissappear
Xilinx Answer #2950 : Design Manager/Ngdbuild M1: Can't find files accross Novell network
Xilinx Answer #2951 : XABEL/Foundation F1.3/Alliance: Using F1.3's XABEL with Alliance packages (mentor, viewlogic)
Xilinx Answer #2953 : JTAG - Latched instruction in the Test-Logic-Reset state of XC4K/XC5K/XC9K parts
Xilinx Answer #2954 : Foundation F1.3/F1.4 XVHDL : I/O flip-flops (IFDX1) instantiation
Xilinx Answer #2955 : V1.5 COREGEN: What architectures are supported?
Xilinx Answer #2956 : M1.4 CPLD: Interactive Timing Analyzer gives unhelpful messages when invoked on a 7K design
Xilinx Answer #2958 : Foundation F1.x, XABEL: DIOEDA errors involving abl2edif
Xilinx Answer #2959 : Foundation Project Manager: Hierarchical, Error xr57 - Input signal drives more than one input buffer.
Xilinx Answer #2960 : M1.3 JTAG Programmer: Communications with the cable could not be established
Xilinx Answer #2961 : XABEL should support Xilinx property 'LOC=FBnn'
Xilinx Answer #2962 : Foundation F1.3/F1.4 XVHDL: Using Input/Output latches
Xilinx Answer #2963 : Timing: How to find the paths not covered by Constraints/Advanced Analysis? i.e. coverage < 100%, i.e. 0 items analyzed
Xilinx Answer #2964 : m1.x ngdbuild. ERROR basut - Problem parsing '_'.
Xilinx Answer #2965 : Foundation F1.3, XABEL: Online Help shows incorrect syntax for XABEL LOC = FBnn property.
Xilinx Answer #2966 : XC2000/XC3000/XC4000/XC5200: Tying two output pins to enhance current drive
Xilinx Answer #2968 : FPGA Express: Where the IEEE and SYNOPSYS VHDL Libraries are located
Xilinx Answer #2975 : XC95108: Are Programmable grounds supported?
Xilinx Answer #2977 : SYNPLIFY: How to use the syn_useenables attribute?
Xilinx Answer #2979 : M1.x: EPIC: How to add a probe or route out a signal
Xilinx Answer #2980 : M1: Undocumented environment variables for the Xilinx GUIs (XIL_*)
Xilinx Answer #2983 : M1.4 Timing Analyzer: Failed to open document (Win95)
Xilinx Answer #2984 : **Obsolete**Foundation F1.3, XC5200: Incorrect polarity of pins in AND2B1, etc components
Xilinx Answer #2988 : Foundation F1.x XABEL: XEPLD/Plusasm 'Partition' property not supported
Xilinx Answer #2989 : Foundation F1.3, XVHDL 3.0.2: Error L20/CO: The Xilinx 4ke library does not contain a latch (#480 Constraint)
Xilinx Answer #2993 : M1.3 MAP: OPTX error -- ERROR: x4kdr: 7 (Foundation F1.3 specific)
Xilinx Answer #2994 : M1.3.7 EPIC crashes on xc4062xl when trying to add opads.
Xilinx Answer #2995 : Workview Office 7.31: Cannot open Project Manager.
Xilinx Answer #2996 : dc2ncf: How do you use the set_max_delay as a substitute for the set_multicycle_path command?
Xilinx Answer #2997 : XC9500: Corrected model from LMG now available
Xilinx Answer #3000 : CPLD: XC9500/XL: Why do the XC9500/XL libraries have pull-up elements?
Xilinx Answer #3001 : Foundation F1.3, XVHDL: XVHDL (Metamor) v3.0.3 Upgrade available on Web Answers page
Xilinx Answer #3002 : Foundation F1.x Project Manager: Very slow when launching under Win95
Xilinx Answer #3003 : Synopsys FPGA Compiler: Error code "VE-0" from analyze command in dc_shell
Xilinx Answer #3006 : CPLD: How to calculate the timing accross a latch in a 9K device
Xilinx Answer #3007 : XABEL, Foundation F1.x: AHDL2BLF or BLIFOPTstep runs indefinitely during ABL2EDIF
Xilinx Answer #3008 : CPLD: CPLD command-line does not support reading PART attribute from netlist.
Xilinx Answer #3009 : dsgnmgr: Core dumps using Exceed/W
Xilinx Answer #3010 : FPGA Express: Instantiating an EDIF from a Foundation Schematic into a top-level FPGA Express Verilog or VHDL Design
Xilinx Answer #3011 : M1.5i/2.1i: NGDBUILD: UCF constraint on element with special char. gives "ERROR:baspr - SSLex0105e: Invalid token"
Xilinx Answer #3013 : FPGA Express 1.2/Foundation 1.3: Creating HDL Macros with FPGA Express 1.2 for Placement on a Foundation 1.3 Top-Level Schematic
Xilinx Answer #3014 : M1.5i/2.1i: TRCE: "HIGH" or "LOW" keyword for PERIOD may not work as expected with OFFSET
Xilinx Answer #3015 : M1 PERIOD placed on net between PAD and IBUF not analyzed
Xilinx Answer #3016 : M1 TNM placed on net between PAD and BUFG/IBUF not forward traced
Xilinx Answer #3017 : Configuration: Dynamic Re-ordering of Daisy-Chain configurations.
Xilinx Answer #3018 : FPGA Express v1.2/Foundation 1.3: Simulating with FPGA Express v1.2 HDL and F1.3 Logic Simulator
Xilinx Answer #3019 : What is Dr. Watson?
Xilinx Answer #3020 : Foundation, XABEL: Supported 'Xilinx Property' for CPLDs with XABEL6
Xilinx Answer #3021 : Foundation F1.x/ XABEL: XEPLD/Plusasm Properties not supported with EDIF-based Abel flow
Xilinx Answer #3022 : M1.3 JTAG Programmer: How to read 3rd party BSDL files
Xilinx Answer #3023 : Foundation State Editor: How to modify encoding scheme for State Machines (ie, one-hot)?
Xilinx Answer #3024 : DATA BOOK: Timing data applied to Commercial, Industrial, and Military devices
Xilinx Answer #3026 : CPLD: 9500* : Usage of internal pullup in IOB
Xilinx Answer #3027 : XABEL6, Foundation F1.x, NGDBUILD: Warning- logical net VCC_net (or GND_net) has no load
Xilinx Answer #3029 : CONCEPT-HDL 13.5: In a mixed-flow, Xilinx primitives are listed in the "resource file" list of Synplify
Xilinx Answer #3030 : Foundation XVHDL, XC9500: How to set an output to high impedance (Hi-Z)
Xilinx Answer #3031 : V1.5, V1.4 COREGEN, WORKVIEW OFFICE, M1: Implemented module has much higher CLB counts than specified in the datasheet
Xilinx Answer #3034 : Foundation Simulator: How to print a specific range of the simulation waveform
Xilinx Answer #3036 : M1.3 Map - Map will not push buffer (or logic optimized to buffer) forward into closed FMAP (MAP=PUC or PLC)
Xilinx Answer #3037 : M1 PLD_EDIF2SIM/XNF2SIM/EDIF2TIM: Error: Could Not find the External part "$SIMPRIMS/___"
Xilinx Answer #3038 : Design Manager M1.3/M1.4/M1.5 - How to specify a cost table level in the M1 Design Manager GUI (MPPR)
Xilinx Answer #3040 : V1.5, V1.4 COREGEN: sample COREGen .COE coefficient files for a PDA FIR filter, RAM and ROM.
Xilinx Answer #3041 : Foundation F1.3, F1.4: How to add Generic Project Type for Board Level Simulation
Xilinx Answer #3043 : Foundation F1.3, Logiblox: TNM attributes on Logiblox in schematic do not pass to EDIF file
Xilinx Answer #3046 : M1: QuickSim functional simulation of a Mentor schematic with instantiated EDIF (without XNF)(From Coregen 1.5 or later, or other sources)
Xilinx Answer #3048 : Foundation F1.x, Design Manager, XABEL: DM doesn't read PLD (Plusasm) or EDN file if flow is changed
Xilinx Answer #3050 : SIMPRIMS: Why do the models for the X_RAMD16 have only one output port?
Xilinx Answer #3051 : Translating lattice LDF file to Xilinx XABEL format
Xilinx Answer #3052 : Hardware Debugger M1_3.7: XCHECKER Self Check Fails in Windows 95 & NT...
Xilinx Answer #3055 : M1.3/M1.4 CPLD: Fitter incorrectly trimming pin from macro which is driving multiple outputs
Xilinx Answer #3059 : LOGIBLOX, NGD2EDIF, WIN95: ERROR:basut - Unexpected argument[7] "module_name" found.
Xilinx Answer #3060 : LogiBLOX, NGD2EDIF, WINDOWS NT: ERROR:basxb:41 - Cannot open temporary output file "C:/TEMP /module_name.ngd"
Xilinx Answer #3061 : Hardware Debugger M1_3.7: Stand alone download and readback software.
Xilinx Answer #3062 : M1.3/1.4 - Fatal Error:basnp:basnpdevice.c:533.1.17 bad nph file (from map and other applications)
Xilinx Answer #3064 : M1.3 Translate: OPTX error:x4kdr: 7 ---netcheck: Macros instantiated in ABEL.
Xilinx Answer #3066 : 96 DATA BOOK: XC3064A/L, XC3164A/L, XC3O90A/L, XC3190A/L I/O pins misprint
Xilinx Answer #3067 : Migrating XBLOX designs to M1: XBLOX2M1 archive now exists on ftp site
Xilinx Answer #3068 : Hardware Debugger M1.4: Readback Capture displays wrong data.
Xilinx Answer #3070 : Modifying path of the dynatext.ini file
Xilinx Answer #3072 : M1 LOGIBLOX: How to LOC or constrain a data register to a range of CLB's
Xilinx Answer #3073 : Foundation F1.x/F2.x, XABEL: Error: Could not find the file xxx.jhd, xxx.bl0
Xilinx Answer #3074 : A1.5/1.4: Cadenece Concept and Verilog-XL: Functional simulation with Mode and Boundary Scan pins in schematic
Xilinx Answer #3076 : Foundation F1.3/F1.4, XC9500, XVHDL: Macro pass-through signals trimmed away or tied to VCC/GND.
Xilinx Answer #3077 : XC4000XL/XLT: Differences between the 4000XL and 4000XLT
Xilinx Answer #3078 : M1.4,Powerview 6: vanlibcreate gives linker error compiling Logiblox VHDL library
Xilinx Answer #3079 : A1.4/1.5/2.1i: ViewDraw Check Project: "Could not load schematic sheet" error for LogiBLOX or COREGen module
Xilinx Answer #3080 : M1.3/M1.4: Viewlogic board level simulation methodology
Xilinx Answer #3081 : Workview Office 7.4, Powerview 6.1 EDIFNETI: viewbase error 413: Pin not on symbol error
Xilinx Answer #3082 : CPLD : XC9500: obtaining Fcnt (operating freq for 16 bit counters)
Xilinx Answer #3083 : M1 Map - ERROR - No more route-throughs available
Xilinx Answer #3085 : M1.3: TIMING: Page Fault in Win95, FATAL_ERROR:baspp:basppphys on Workstations
Xilinx Answer #3086 : M1.3 MAP:x4kma:x4kmagrclapse.c illegal situation for H1 pack:<block>
Xilinx Answer #3090 : FPGA Configuration: Run times for configuration rates and CPLD programming.
Xilinx Answer #3091 : Foundation F1.x, Timing Simulator: Same bus name with different indices gives 'X' outputs
Xilinx Answer #3092 : Foundation F1.3 State Editor: when selecting HOLD for Unsatisfied Conditions, selection not kept.
Xilinx Answer #3094 : ** OBSOLETE ** ALPHA 1.1 COREGEN: Warning: Your directory path <directory_path> should not contain any directory names longer than 8 characters.
Xilinx Answer #3096 : M1: How to convert an existing XACTstep 5.x design to use the M1.x tools
Xilinx Answer #3098 : XABEL: Does Foundation need to be installed to use XABEL with Alliance software?
Xilinx Answer #3099 : LogiCORE PCI32 4000: Verilog synthesis/simulation with PCI LogiCORE v2.0, FPGA Compiler v1997.08, VerilogXL v2.5, and M1.3.7
Xilinx Answer #3100 : Foundation Project Manager, WinNT: "lmacs: ...unable to access transaction control file" in WINNT
Xilinx Answer #3101 : XABEL 6: Feedback signals interpreted differently in M1 (EDIF) than XACT (PLD)
Xilinx Answer #3102 : M1.x: EPIC - How to use EPIC commands to globally lock components.
Xilinx Answer #3103 : LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Compiler & VSS v1997.08, and M1.3.7
Xilinx Answer #3105 : LogiCORE PCI32 4000: Verilog synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v1.2, & M1.3.7
Xilinx Answer #3106 : Hardware Debugger M1_3.7: Is XC5200 supported?
Xilinx Answer #3107 : M1.3 LOGIBLOX WinNT w/ Number Nine video card may crash when component is created; N9I128V2.dll
Xilinx Answer #3108 : LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v1.2, & M1.3.7
Xilinx Answer #3109 : Viewlogic: ViewDraw 7.31 is missing BAF2VL.EXE, cannot run XREF
Xilinx Answer #3111 : M1.4 PAR - Turns engine requires explicit use of -pl and -rl switches to work.
Xilinx Answer #3114 : HardWire: Where to get speed files?
Xilinx Answer #3115 : XC2000: Considerations when Migrating an XC2000 Design to a Newer Device Family
Xilinx Answer #3116 : Typical I/V Characteristics of XC9500 Outputs
Xilinx Answer #3119 : Is it possible to run more than one version, multiple versions of lmgrd/flexlm at one time?
Xilinx Answer #3120 : Foundation Simulation seems to hang, or takes a long time before showing the waveform
Xilinx Answer #3121 : HITOP: xr52:[Warning]NET 'xxxx' is driven by 'yyy' and 'zzz'.
Xilinx Answer #3122 : CPLD: 9500/XL :How do the BUFGSR, BUFG, OE buffers work on the 9500/XL?
Xilinx Answer #3123 : CPLD XC9500/XL : How are initial states of flip-flops determined on the 9500 CPLD's?
Xilinx Answer #3124 : Foundation F1.x Simulator: Selective preset feature may disrupt the operation of counters, state machines
Xilinx Answer #3125 : M1.4 CPLD: Automatic Local Feedback optimization not yet supported for XC9500
Xilinx Answer #3126 : M1.4 CPLD: A fitter crash may result from properties applied to wrong objects
Xilinx Answer #3127 : M1.4 CPLD: Possible solution for excessive run time of Bus Error problems with the fitter
Xilinx Answer #3128 : M1.4 JTAG Programmer: Long JEDEC/BSDL file names obscured in the display
Xilinx Answer #3129 : M1.4 JTAG Programmer: Context-Sensitive help does not work.
Xilinx Answer #3134 : A1.5/1.4: How to import a VHDL, Verilog, or LogiBLOX generated netlist into a Concept schematic
Xilinx Answer #3135 : M1.4 GUI: 'Optimize & Map' tab for 5k implementation template has an incorrect option
Xilinx Answer #3136 : How does the XILINX_PATHLIMIT environment variable work?
Xilinx Answer #3137 : Hardware Debugger M1.3: FATAL_ERROR:baspm:baspmdlm.c:187:1.18 - dll open failed...
Xilinx Answer #3138 : Foundation F1.x Logic Simulator: ASCII test vector, cannot use u or p option for timing
Xilinx Answer #3139 : dc2ncf: ERROR [#154]: Invalid argument -max for set_input_delay constraint at line x
Xilinx Answer #3142 : TAENGINE M1.3: ERROR:hi402 there is no original clock signal to clock pin *.CLKF
Xilinx Answer #3143 : M1.5i/2.1i: TRCE: Path tracing behavior for RAMs
Xilinx Answer #3144 : Exemplar/M1 NGDBUILD: ERROR:basnb:79 (pin mismatch) and ERROR:basnu:93 (unexpanded) design with instantiated modules
Xilinx Answer #3145 : Foundation XVHDL, NGDBuild: Warning:basnu-The input pad net "<nonclk signal>" is driving one or more clock loads, but is not using a dedicated clock buffer
Xilinx Answer #3150 : Foundation F1.3 State Editor, XABEL: Error APP_95 "<file>.edf does not exist" when creating macro
Xilinx Answer #3151 : Foundation State Editor F1.x, XABEL: One-hot state machine is created "Cold"
Xilinx Answer #3152 : XABEL, Foundation F1.x: ref_2_inst: dangling port (message during synthesis)
Xilinx Answer #3153 : XABEL, Foundation F1.x: Internal Error 18911 in Blif2net (abl2edif)
Xilinx Answer #3155 : Ngdbuild: ERROR:basnu-The signal "GSR" in block "<component>" uses a Xilinx reserved global signal name
Xilinx Answer #3156 : --OBS--Timing Analyzer: Failed to open document when analyzing paths
Xilinx Answer #3157 : PAR: Error: baspw: 134 Input design is empty.
Xilinx Answer #3158 : NGDANNO : Warning: basna: 22 - NGDANNO found physical components for which...
Xilinx Answer #3160 : HW130 v4.1.0, 9572: Verify failures on 9572-PC44 devices
Xilinx Answer #3161 : Foundation F1.x Simulator: How much memory does a simulation require?
Xilinx Answer #3162 : CPLD: XC9500: What is the Maximum Junction Temperature allowed in the CPLDs
Xilinx Answer #3163 : NGD2VHDL, NGD2VER, NGD2XNF, NGD2EDIF: ERROR:basut:79 - File system full!
Xilinx Answer #3164 : Can not open books in dynatext
Xilinx Answer #3165 : XC4000EX/XL: Some BUFGEs (Eearly buffers) are faster than others
Xilinx Answer #3167 : VERILOG-XL: How to have NGD2VER automatically specify the addition of the `uselib directive and path to the SIMPRIMS libraries?
Xilinx Answer #3168 : M1.3 Performance Pack: HWDEBUGR patch not installed correctly
Xilinx Answer #3169 : M1.3 Performance Pack: Usage of Lab Install
Xilinx Answer #3171 : XC4000EX/XL/XV/XLT: How to accurately locate BUFGLS and BUFGE components
Xilinx Answer #3173 : JTAG - How to read SVF files.
Xilinx Answer #3174 : Foundation F1.3, XVHDL 3.0.2/3.0.3: Using a dedicated input pad for an instantiated global buffer (bufg)
Xilinx Answer #3175 : Foundation F1.3, Logic Simulator: Simulator will hang if status line has been deselected
Xilinx Answer #3176 : Foundation F1.3, 3K/5K Early Access Libraries
Xilinx Answer #3177 : JTAG - How to co-relate the states in the SVF file to TAP controller states?
Xilinx Answer #3178 : M1.4 ngd2edif: ERROR:basng - (NGD-internal) bFATAL_ERROR:baspp:basppres.c:828:1.15
Xilinx Answer #3180 : V1.5, V1.4 COREGEN, VIEWLOGIC: Error: Could not read symbol file <path_to_SYM_dir>\SYM\<modulename>.1 java.io.File NotFoundException: <path_to_SYM_dir>\SYM\<modulename>.1
Xilinx Answer #3181 : M1.3, Dynatext, Xilinx Books: After installing Dynatext, no books are available.
Xilinx Answer #3182 : M1.4 EPIC: EPIC may crash on some systems with the autorouter turned on
Xilinx Answer #3183 : Design Manager 1.5i/2.1i: WS ONLY - Selecting browse button hangs the DM, Flow Engine doesn't appear but is running
Xilinx Answer #3186 : Foundation F1.3 XABEL: BLIF2OPT hangs or gives virtual memory overflow error
Xilinx Answer #3187 : Foundation F1.3 XABEL: Heavily constrained designs may cause fitter to core dump
Xilinx Answer #3188 : Foundation F1.3 XABEL: Ambiguous interpretation of feedback signals
Xilinx Answer #3190 : Install : Why is administrative priviledges required to install the Xilinx tools on Windows NT?
Xilinx Answer #3192 : M1.3 Performance Pack: How to install
Xilinx Answer #3193 : CONCEPT-HDL 13.5: User defined constraints are not passed from the schematic to Synplify
Xilinx Answer #3194 : CPLD: XC9500/XL: What is the polarity for the tri-state enable for CPLDs?
Xilinx Answer #3196 : M1 MAP: What is an MDF file?
Xilinx Answer #3197 : M1 Logiblox: Error - Bus Conflicts during Foundation simulation
Xilinx Answer #3202 : Foundation F1.4: Foundation Library format issues
Xilinx Answer #3203 : JTAG - General description of the TAP controller states.
Xilinx Answer #3204 : M1.4, Map, 5200,-r ,-pr , basut: Error:basut - Switch "-r" is not allowed.
Xilinx Answer #3205 : Foundation F1.4, F1.5. Logic simulator: Bus ordering reversed after bus has been flattened, then combined
Xilinx Answer #3206 : Foundation F1.4 Project Manager: "Update HDL Macros" option in Project Manager Document menu not found
Xilinx Answer #3207 : M1.3 Hitop - Unnecessary warning about 95108 UPGs not supported
Xilinx Answer #3208 : M1.3.7 Hitop - Hitop crashes if there are more than 20 timespecs in the .ncf file.
Xilinx Answer #3209 : M1.4 PAR - PAR does not run any cleanup passes by default in M1.4.
Xilinx Answer #3210 : M1.3 CPLD - The XC95144 pinout has changed
Xilinx Answer #3213 : M1.3 Hitop - Hitop core dumps on a specific case.
Xilinx Answer #3214 : CPLD: XC9500: Difference between all the checksums for the XC9500 family
Xilinx Answer #3216 : M1.3.7 PAR: UCF LOC constraint on net does not override conflicting schematic pad constraint.
Xilinx Answer #3217 : M1.3/M1.4 MAP - Map crashes due to an illegal pad configuration.
Xilinx Answer #3219 : Foundation F1.4 Simulator, XC3000: Outputs are undefined in Timing Simulation
Xilinx Answer #3221 : Foundation F1.4 Project Manager: Netlist creation error if path has a dot (.) character
Xilinx Answer #3223 : Foundation F1.4 Simulator: Last line ignored inside a command/script file
Xilinx Answer #3224 : FPGA Express 2.x/3.0: Comparators may not infer carry logic
Xilinx Answer #3225 : Foundation F1.4 Schematic Editor: Library symbol SR8RLED is different size in 3k library
Xilinx Answer #3226 : CPLD: XC9500: What are the recommended maximum rise times for inputs?
Xilinx Answer #3227 : Foundation F1.x: Project cannot have same name as macro (circular reference)
Xilinx Answer #3228 : Foundation F1.x State Editor: Logical Error 1002: Source line length exceeds 150 character
Xilinx Answer #3230 : 2.1i Design Manager - Win95 ONLY - Entering "Xilinx" at a DOS prompt yields "OFF"
Xilinx Answer #3231 : Foundation F1.4: Uninstall program will preserve user projects, but remove sample projects
Xilinx Answer #3232 : Hardware Debugger, M1.3 & M1.4 Lab Install, Error Baspm:Baspmdllm 174 & 187 dll open of library libx4xbs.dll
Xilinx Answer #3233 : Viewlogic: Aurora Synthesis 7.4 produces global GND and VDD instances in schematics; NGDBUILD fails
Xilinx Answer #3234 : Foundation XVHDL: Using mode pins (MD0, MD1, MD2) for general I/O
Xilinx Answer #3235 : F1.4, FPGA Express 2.0: Inverting Pin on HDL instantiation does not work
Xilinx Answer #3236 : M1.4 Spartan - A patch is available to provide the PQ208 package for Spartan s20, s30 and s40 devices.
Xilinx Answer #3237 : M1.3 CPLD - Fitter drops inverter from Express XNF when IBUF drives OBUFT.
Xilinx Answer #3238 : M1.3 CPLD - CPLD Patch available for several issues
Xilinx Answer #3239 : M1.3 CPLD - A -6 speed grade has been added for XC9536.
Xilinx Answer #3240 : M1.3 CPLD - There have been pinout changes for the XC95144 device.
Xilinx Answer #3241 : M1.3 CPLD - Bitmap is incorrect for XC95288.
Xilinx Answer #3242 : M1.3 Hitop - Fitter fails to meet Period timespec for easy design.
Xilinx Answer #3243 : M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.
Xilinx Answer #3244 : M1.4 Map - FATAL_ERROR:x4kma:x4kmamerge.c:1879:1.145
Xilinx Answer #3245 : M1.4 Map - Mapper unable to merge a RAM and Flop with opposite clock polarities
Xilinx Answer #3246 : M1.4 Map - FATAL_ERROR:x4kma:x4kmamerge.c:2585:1.145.12.2 - Too many signals to move..
Xilinx Answer #3247 : M1.4 Map - FATAL_ERROR:baste:bastecomp.c:564:1.72 - Moving BEL from U7451 to occupied belsite ...
Xilinx Answer #3248 : M1.4 Core Tools - All M1.4 bug fixes available in M1.4 Core Tools Patch on the Xilinx Download Area.
Xilinx Answer #3250 : M1.4 Map - FATAL_ERROR:x4kma:x4kmacarry.c:2703:1.122 - Illegal call to swap.
Xilinx Answer #3251 : M1.4 Map - Mapper fails with Application Fault on EX and XL Devices on PC only.
Xilinx Answer #3252 : XC9500: Miscellaneous programming questions
Xilinx Answer #3253 : XABEL, M1.4: Using XABEL with M1.4 Alliance software
Xilinx Answer #3254 : EZTAG: XC9500: How to create a single SVF file from multiple SVF files for devices in a single chain?
Xilinx Answer #3255 : XC9500: How to program mulitple devices in a single chain using the HP3070 tester?
Xilinx Answer #3256 : M1.5i/2.1i: NGDBUILD: OFFSET constraint gives "ERROR:basts:69 - NET CLK ... is not a pad-related net"
Xilinx Answer #3259 : Foundation/F1.3, MAP, baste Error: baste 164:components with same name...uniquifying.
Xilinx Answer #3260 : M1.3, PAR, baspw, Error: baspw:97 PAR: Not all timing constraints could be satisfied.
Xilinx Answer #3263 : M1.x: EPIC: How to select an entire net
Xilinx Answer #3265 : M1.4 LogiBLOX: Discrepancy between Dual Port RAM simulation behavior and Dynatext documentation.
Xilinx Answer #3267 : LogiCORE PCI32 4000: Verilog synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v2.0.2, & M1.4.12
Xilinx Answer #3268 : LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v2.0.2, & M1.4.12
Xilinx Answer #3269 : M1.4 MAP: NMC hard macro cannot be LOC'd from the UCF file
Xilinx Answer #3271 : M1.4 General - A patch is available to add CB228 package to XC4028EX.
Xilinx Answer #3272 : M1.4: How to set up LM_LICENSE_FILE when using Veribest and WorkView Office
Xilinx Answer #3273 : SPARTAN: Explanation of speedgrades in Spartan
Xilinx Answer #3275 : CPLD M1.3(patch),M1.4: Pin location assignments for 9500 designs are not seen
Xilinx Answer #3276 : Foundation F1.x Schematic, NGDBUILD: ERROR: basnu - logical net "net_name_int" has both active and tristate drivers
Xilinx Answer #3278 : XABEL: how to implement a bidirectional bus in abel
Xilinx Answer #3279 : Foundation F1.4 Simulator, XC5200: Outputs are undefined in Timing Simulation
Xilinx Answer #3280 : OBSOLETE!!!!!!!!!!!!
Xilinx Answer #3281 : M1.4 General - A patch is available to add the CB228 package to XC4036XL and XC4062XL devices and BG432 to XC4085XL device..
Xilinx Answer #3283 : XC4000XL/XV: XV vs XL Architectural Differences
Xilinx Answer #3284 : XC5200: Power on delay of 4mS is too fast for power supplies
Xilinx Answer #3285 : M1.5i/2.1i: Timing Analyzer reports "0 items analyzed" on a period constraint.
Xilinx Answer #3288 : Foundation XABEL/ABL2EDIF: Logical Error 18823: Enable 'signal.OE' is only allowed when top_level specified.
Xilinx Answer #3289 : PROM File Formatter M1.3: basbs 189- Cannot load from an address other than 0 with a serial PROM.
Xilinx Answer #3291 : F1.5, NGDBUILD: FATAL_ERROR:basnb:basnbctxt.c:140:1.14.1.2 - design 'ROOT' has invalid CAE_VENDOR property 'metamor'
Xilinx Answer #3292 : Foundation PCM reports JEDEC-to-ABEL conversion failed after normal completion
Xilinx Answer #3293 : MAP terminates abnormally after successfully writing output files (.ncd and .mrp).
Xilinx Answer #3294 : M1 JTAGPGMR: Basic debugging techniques for downloading design
Xilinx Answer #3295 : M1.4,F1.5,2.1i Security: How can I get the license manager to run as a service on NT?
Xilinx Answer #3296 : FPGA Express 2.x/3.x: Optimization gives FE-PADMAP-3 error
Xilinx Answer #3299 : F1.3: SIMUL caused a general protection fault, will shut down.
Xilinx Answer #3300 : FPGA Express 2.0: Errors/Warnings/Messages window does not always work correctly
Xilinx Answer #3301 : FPGA Express 2.0/Foundation 1.4: Creating HDL Macros with FPGA Express 2.0 for Placement on a Foundation 1.4 Top-Level Schematic
Xilinx Answer #3302 : CPLD: What are negative setup times in CPLD Performance report?
Xilinx Answer #3303 : Workview Office 7.31, 7.4, 7.5: Initialization Error written to viewdraw.err while starting ViewDraw
Xilinx Answer #3305 : M1.3/M1.4 ngd2xnf does not support 4000EX/XL/XV
Xilinx Answer #3306 : Design Manager M1/2.1i: GUI does not start/come up under Solaris 2.5.x/2.6/2.7
Xilinx Answer #3307 : M1.3/M1.4 hplusas6: JEDEC File generator not writing ABEL test vectors in the JED file
Xilinx Answer #3308 : FPGA Express 2.0: Turbo Mode may cause Alliance version of FPGA Express to crash
Xilinx Answer #3311 : M1.4 Map - Optimization of OFDT symbol results in dangling tri-state control pin
Xilinx Answer #3312 : M1.4 Map - ERROR:baste:262 - Bad format for LOC constraint
Xilinx Answer #3313 : XVHDL F1.3: XVHDL caused an invalid page fault in module XVHDL.EXE
Xilinx Answer #3314 : M1.4 Map - Map crashes trying to push buffer/inverter into hard macro (.nmc).
Xilinx Answer #3316 : M1.4 PAR - PAR fails with Arithmetic Exception on a hard maco design.
Xilinx Answer #3317 : M1.4 PAR - PAR core dumps during Initial Timing Analysis.
Xilinx Answer #3319 : M1 LOGIBLOX, NGD2EDIF: Security, Error:basne-security error-unable to lock license...
Xilinx Answer #3320 : ViewSim - "Error: Could not find memory component U1" when loading XMM file
Xilinx Answer #3321 : CPLD : XC9500/XL:Is there a reset or a done pin for CPLDs to determine if the device runs correctly?
Xilinx Answer #3322 : CPLD: Can the 9500 output buffer drive the load of several 9500s?
Xilinx Answer #3323 : SYNPLIFY: How to instantiate the STARTUP for a XC5200?
Xilinx Answer #3324 : NGDBUILD/MAP 1.5i/2.1i: "Unexpanded block" warnings/errors with design from a third party entry tool (e.g. Orcad, Protel, Synario) (basnu:93).
Xilinx Answer #3325 : V1.5.0, V1.4.0 COREGEN: java.lang.OutOfMemoryError "Out of memory" errors on very large cores
Xilinx Answer #3327 : COREGEN: When are TBUFs used for muxing in ROMs, single port RAMs, and dual port RAMs?
Xilinx Answer #3328 : 98 DATA BOOK: BGA352/BGA432 package outline error on page 10-34
Xilinx Answer #3329 : ngd2vhdl M1.3/M1.4: Why does ngd2vhdl create a data type called std_logic_vector2?
Xilinx Answer #3330 : Foundation F1.3, FPGA Express: Functionality incorrect for Express modules on Schematics
Xilinx Answer #3331 : Y2K: Xilinx Software YEAR 2000 Compliance (including information about PC / WS Operating Systems and EDA Vendors)
Xilinx Answer #3332 : M1.3/1.4 TRACE: A DPRAM DPO to destination FROM:TO constraint is not analyzed
Xilinx Answer #3333 : M1.5i/2.1i TRACE: What to do about tilded values (~46ns) in the report
Xilinx Answer #3336 : Orcad Express 7.1x does not pass attributes to edif file
Xilinx Answer #3339 : Foundation XVHDL: Instantiating OSC52 in a 5200 design
Xilinx Answer #3342 : M1.4 PAR - Mode pins and TDO do not show up in pad report for FPGAs
Xilinx Answer #3344 : M1.4 Turns Engine: ERROR - PING cannot reach node 'node_name'
Xilinx Answer #3345 : A1.4: What's new in A1.4 XSI
Xilinx Answer #3350 : M1.4 JTAG Programmer: Problems communicating to the serial port on HP-UX
Xilinx Answer #3357 : M1.4 Map - Incorrect mapping leads to DRC warning about component pin with no signal attached.
Xilinx Answer #3358 : XABEL: How to lock down (constrain) pins through ABEL code
Xilinx Answer #3359 : What kinds of information IBIS Models do and don't provide.
Xilinx Answer #3362 : JTAG Programmer - Part is not an SPROM, usercode cannot be specified on the command line, will be ignored
Xilinx Answer #3364 : Foundation BASE package: Dynatext browser not installed by default
Xilinx Answer #3365 : Foundation F1.3/F1.4 XVHDL: How to use the numeric_std package
Xilinx Answer #3371 : M1.x; EPIC:: ERROR: basep: This component is part of a macro/Cannot swap macro component.
Xilinx Answer #3372 : SYNPLIFY: How to synthesize the OE FF in the SpartanXL, XC4000XLA/XV, and Virtex IOB?
Xilinx Answer #3374 : M1.5i/2.1i: WARNING:bastw:174- The current connection evalutation limit of 1000 caused ....
Xilinx Answer #3377 : EXEMPLAR: Instantiating a pulldown/pullup in Verilog?
Xilinx Answer #3378 : PAR M1.4: FATAL_ERROR:basrt:basrtsanity.c:167:1.3 - Process will terminate.
Xilinx Answer #3379 : M1.4, Map, Error: FATAL_ERROR:x4kma:x4kmamerge.c:2460:1.145...
Xilinx Answer #3380 : Licensing the Alliance version 1.4 software (PC and UNIX)
Xilinx Answer #3381 : M1.4 Map - FATAL_ERROR:x4ema:x4emaclb.c:663:1.44:5.2 - Flop in Y found
Xilinx Answer #3384 : XABEL M1.3 - Slew rate property does not work with EPLD patches
Xilinx Answer #3385 : M1.4,NT,Map,FATAL_ERROR:x4kma:x4kmagrclapse.c:1953:1.90.12.2 - No pin for sig...
Xilinx Answer #3386 : M1.4: Fatal error: basnc:basncgrid.c:129:1.5: grid file from xilinx:5200:5210: is corrupted
Xilinx Answer #3387 : M1.3/M1.4: Hitop, Done: Failed with exit code: 002
Xilinx Answer #3389 : M1 docs., library guide,X74_168: Fig. 12.12, shown cascading counter is wrong.
Xilinx Answer #3391 : M1.4, NT, PAR, INTERNAL_ERROR:baspl:basplbscore.c:553:1.17
Xilinx Answer #3392 : M1.3 Map - FATAL ERROR:x4kma:x4kmacarry.c:681:1.96.10.4 - COUTO...
Xilinx Answer #3393 : Hardwire: What package are available in Hardwire for FPGA?
Xilinx Answer #3395 : Foundation F1.x: LMACS, Btrieve and Library Access errors
Xilinx Answer #3396 : M1.4 PAR - XC4000 design crashes after starting the Initial Timing Analysis.
Xilinx Answer #3399 : 2.1i, V1.5, V1.4 COREGEN: How to debug COREGEN hang and startup problems
Xilinx Answer #3400 : ** M1.4 CPLD: C1244, internal error, corrupted partition product term.
Xilinx Answer #3401 : Workview Office 7.4, Windows NT: Path to LogiBLOX under tools menu is incorrect
Xilinx Answer #3402 : FPGA Express 1.2/2.0/F1.5 : clock buffer not inserted if clock net sources RAMs or Black Boxes
Xilinx Answer #3403 : A1.4/F1.4: Some figures in the 1.4 Hardware User Guide are incorrect
Xilinx Answer #3404 : 2.1i CPLD: How to use programmable grounds for unused pins in 9500/XL devices
Xilinx Answer #3405 : M1.4 Map - Map will sometimes run FLUT to Flop connection through an HLUT routethru.
Xilinx Answer #3406 : EZTAG: How to generate a .svf file?
Xilinx Answer #3407 : M1.4 MAP:ERROR:x4kma:371 - IBUF symbol "symbol_name" is unable to combine with ...
Xilinx Answer #3409 : Foundation Simulator: End of time error
Xilinx Answer #3410 : Design Mangager/ngdbuild M1.4: Application error/Invalid Page Fault in module mfc40.dll
Xilinx Answer #3411 : M1.4: Spartan devices do not appear in the Part Selector dialog box
Xilinx Answer #3414 : LogiCORE PCI32 4000: 4062XLT BG432 -09 Ping example: Timing simulation using VSS causes failure
Xilinx Answer #3416 : Constraints: How to specify a specific CLB to LOC an instance to.
Xilinx Answer #3417 : CPLD, M1.3/M1.4: How to run the JTAG Programmer, Hardware Debugger and PROM File Formatter as a stand alone?
Xilinx Answer #3418 : Cable - Is there a schematic for the Parallel Cable III (JTAG Cable)?
Xilinx Answer #3419 : M1.4 License: lmutil lmhostid returns hostid of all zeros
Xilinx Answer #3421 : M1.4 MAP: ERROR: x4kma:111 -- Design is empty
Xilinx Answer #3423 : 96/98 DATA BOOK: RAM: Write enable pulse width following active edge of WCLK.
Xilinx Answer #3427 : M1.4 MAP: ERROR:x52ma:250 This type of signal is not supported by the XC5200 ...
Xilinx Answer #3431 : M1.4 MAP/PAR: BUFG is not routed properly for 3164Apc84 package.
Xilinx Answer #3432 : V1.5.x, V1.4 COREGEN: Not all processing output is logged to the coregen.log file.
Xilinx Answer #3436 : FPGA Express: Instantiations in HDL are UNLINKED (FE-CHECK-4) (FE-LINK-2)
Xilinx Answer #3438 : A1.4/F1.4 Bitgen - Bad 5200 bitstream is created for IOB routethrus and CLB latches
Xilinx Answer #3440 : Map M1.4.12 ERROR:basut:162 - This Xilinx application has run out of memory
Xilinx Answer #3442 : M1.4 CPLD - A patch is available for several issues.
Xilinx Answer #3444 : NGDBUILD: Could not find NET " " in design " " with Cadence Concept design
Xilinx Answer #3445 : Floorplanner-XACT: Core dumps on HP-UX 10.xx
Xilinx Answer #3447 : MAP FATAL ERROR: Illegal situation for H1 pack.
Xilinx Answer #3448 : M1.4 Map - Map crashes for a specific case. A patch is available.
Xilinx Answer #3449 : M1.4 MAP:FATAL_ERROR:basnc:basncsignal.c:262:1.62
Xilinx Answer #3450 : MAP M1.4: ERROR:x4kma:312 - The following symbols could not be constrained...
Xilinx Answer #3451 : M1.4 Map - If mapper has errors, the map report (.mrp) doesn't contain trim information.
Xilinx Answer #3452 : FATAL_ERROR: baste:bastecomp.c:1943:1.61.9.3 - idx not found.
Xilinx Answer #3453 : Alliance 1.4/1.5: Operating system, disk space, memory and swap space requirements
Xilinx Answer #3454 : Foundation F1.3/F1.4, XVHDL, Synthesis, grayed, Error: Hde: Foundation option in xilinx, Keylock not found. (Sentinel driver)
Xilinx Answer #3455 : M1.4 Ngdanno - ERROR : Non numeric pin number 'P90' found.
Xilinx Answer #3456 : M1.4 PAR - Some xc5200 designs core dump.
Xilinx Answer #3457 : M1.4 PAR - The xc3000 and xc5200 routers will incorrectly use route-thrus in unused bonded pads.
Xilinx Answer #3458 : core dump on Win95 platform during fplan run
Xilinx Answer #3459 : M1.4 Ngdanno - Timing discrepency between Trce and back annotated timing for EQN logic.
Xilinx Answer #3460 : M1.4 NGDANNO - Ngdanno fails to properly annotate back to logical representation.
Xilinx Answer #3461 : M1.4 PAR - PAR runs out of memory during placement of design with hard macros (.nmc's) that contain routing information.
Xilinx Answer #3462 : M1.4 PAR - PAR crashes on a specific xc5200 case.
Xilinx Answer #3463 : M1.4 PAR - PAR hangs when using a PCF to LOC single component hard macros (.nmc's).
Xilinx Answer #3465 : Foundation Schematic Editor F1.x: How to print all black schematics (instead of grey scale).
Xilinx Answer #3466 : Constraints/UCF/TRCE: How fine can the resolution be on timing constraints?
Xilinx Answer #3469 : M1.x Install: Windows protection error (caused by 3com network board running OSR2)
Xilinx Answer #3470 : M1.4 Constraints: LOC'ing a PAD to an edge or multiple sites
Xilinx Answer #3473 : Spartan: Pinouts on the Version 0.6 of the data sheet are incorrect.
Xilinx Answer #3474 : M1.3/M1.4 Map FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL U3/N1304 belong
Xilinx Answer #3476 : M1.x EPIC - How to make use of history substitution on the EPIC command line.
Xilinx Answer #3477 : Foundation Express 2.0: Module compile inserts STARTUP and clock buffers (BUFG)
Xilinx Answer #3480 : Foundation F1.4: Upgrading your Foundation Express license to 2.0.x
Xilinx Answer #3482 : M1.4 LogiBLOX: How to constrain a 4KE/X LogiBLOX Counter
Xilinx Answer #3483 : floating license: While running M1.x dialup networking is evoked several times
Xilinx Answer #3486 : SYNPLIFY: How are asynchronous set/reset flip-flops (DFFRS) handled?
Xilinx Answer #3487 : The HW-112 Programmer is also known as the PP1 (and PP2)
Xilinx Answer #3488 : M1: What is in the $XILINX/xc4500e directory?
Xilinx Answer #3490 : Workview Office: Calc tutorial needs newer commmand (.CMD) files
Xilinx Answer #3491 : M1.4 JTAG Programmer: How to Create SVF files that support BULK Erase
Xilinx Answer #3493 : 2.1i, V1.5, V1.4 COREGEN, XC4000: Incorrect data on output of 4K PDA FIR and SDA FIR cores when maximum output width is not selected
Xilinx Answer #3494 : Workview Office 7.4: Tutorial in "Getting Started" guide will not work with Xilinx license
Xilinx Answer #3496 : SYNPLIFY: How to instantiate the mode pins (MD0, MD1, MD2) in HDL (Verilog/VHDL)?
Xilinx Answer #3497 : F1.x State Machine Editor: Syntax Error 1031: Undefined identifier name 'SREG0'
Xilinx Answer #3498 : V1.5, V1.4 COREGEN: Does COREGen support floating point values in the .COE coefficient files?
Xilinx Answer #3499 : M1.4 PAR: ERROR: x45dr - netcheck: / Warning: basrt
Xilinx Answer #3506 : Foundation\FPGA Express: Adding new libraries for Express projects
Xilinx Answer #3508 : MAP: CY4 Symbol Errors. FPGA Express: Reading xnf or edf netlists into project.
Xilinx Answer #3509 : M1.4 Win95 - A patch is available to address slow runtimes for applications that load/write .ngd files.
Xilinx Answer #3512 : Viewlogic: Inverted signals (with tilde, ~) can be used with M1
Xilinx Answer #3513 : M1.5i/2.1i: NGDBUILD: invalid NCF/UCF file entry value "~" detected on line ##.
Xilinx Answer #3514 : Will the heatsink on the bottom of the HQ240 (or smaller packages such as HQ160) short signals on the board.
Xilinx Answer #3516 : M1.4 Timing: Do NOT use the FTP patch M1.3.7 speed files for EX
Xilinx Answer #3517 : M1.4 TRACE: Do NOT activate CMOS level timing for XL family
Xilinx Answer #3518 : CPLD: 9500: What are the differences between reset lines in simulation and on the device
Xilinx Answer #3519 : M1.4 XC3000/3100: The signal "<signal between ipad and bufg>" is unused and has been removed.
Xilinx Answer #3522 : M1.4: Error in bitgen: error:basbs no bfd file specified
Xilinx Answer #3523 : V1.5, V1.4 COREGEN: Required license features for Viewlogic Viewdraw interface executables used by COREGen v1.4.0 (EDIFNETI, EDIFNETO, VHDL2SYM)
Xilinx Answer #3524 : M1.4 Map - Map creates an illegal IOB configuration with conflicting EC pin and OMUX usage.
Xilinx Answer #3525 : M1.4 Map - 5200: Map is not trimming global reset signals
Xilinx Answer #3526 : MAP M1.4 - Application error on XC4000E design during the "Optimizing" phase.
Xilinx Answer #3527 : M1.4 Map - FATAL_ERROR:basnc:basncsignal.c:262:1.62 - Could not find a bel for a signal...
Xilinx Answer #3528 : M1.4 PAR - PAR core dumps when trying to place a large xc4000xv design
Xilinx Answer #3531 : Foundation F1.4 Install: Not all 4000XL devices installed by default
Xilinx Answer #3532 : A1.4/F1.4 - List of all Software Updates with dependencies
Xilinx Answer #3533 : A1.4/F1.4 CPLD - List of all CPLD patches available in A1.4/F1.4.
Xilinx Answer #3534 : M1.5i/2.1i: How to preserve the pinout of a previous PAR run (pad2ucf)
Xilinx Answer #3535 : Foundation Logic Simulator: WARNING: More than one normal (Totem_Pole) output in the folloing node...
Xilinx Answer #3536 : M1.4 hwdebugr: Hardware Debugger does not load FPGA bit files successfully in Lab Install environment.
Xilinx Answer #3540 : Foundation Simulator, Logiblox, F1.4: Async_Val not simulated at power-up or GSR.
Xilinx Answer #3541 : F1.4, Demo License, Docs, Features: Demo license prevents use of Constraints GUI in Express
Xilinx Answer #3543 : LogiCORE PCI: Why can't an I/O Base Address Register be set to > 256 bytes on an x86 processor?
Xilinx Answer #3544 : LogiCORE PCI32 4000: XC4000XLT Clamp (Vtt) diode specification
Xilinx Answer #3547 : LogiCORE PCI32 4000: VHDL/Verilog synthesis/simulation with PCI LogiCORE v2.0, Synplify 5.0 & M1.4.12
Xilinx Answer #3549 : LogiCORE PCI: Base Address Register attributes
Xilinx Answer #3552 : LogiCORE PCI: Power Management - Description of Function Power States
Xilinx Answer #3553 : LogiCORE PCI32 4000: MAP ERROR:x4kma:312 or x4kma:387- the following symbols could not be constrained to a single CLB
Xilinx Answer #3558 : C1.5., C1.4 COREGEN: cannot expand module folders by double clicking them on Openwindows
Xilinx Answer #3560 : Foundation F1.4: Xilinx Online Books (Dynatext) not installed by default
Xilinx Answer #3561 : Spartan: What is the comparison between Spartan and 4000E families?
Xilinx Answer #3562 : Foundation F1.x, XABEL: Xabel.exe not found
Xilinx Answer #3563 : XC3000A: Map ignores LOC on pads driving BUFG
Xilinx Answer #3564 : FPGA Express 2.0: Selecting Synthesis->Options causes Express to crash
Xilinx Answer #3566 : FPGA Express 2.0, Foundation Express 1.4: Patch version 2.0.3 available
Xilinx Answer #3567 : CPLD: 9500/XL :Sourcing internal logic with a global buffer
Xilinx Answer #3568 : Foundation Simulator F1.4: Keyboard toggle may not work
Xilinx Answer #3569 : SPARTAN: Pinouts for XCS20 and XCS30 in PQ208 package are incorrect in 1998 Databook
Xilinx Answer #3570 : A1.4/F1.4 PAR - PAR introduces DRC error: "ERROR:x45dr - netcheck: Signal <net> is routed to the O pin of block <comp> on routing which is not available because the EC pin is using the Logic Ze ro option.
Xilinx Answer #3571 : XC95108 with date code of 9717 is not configuring
Xilinx Answer #3575 : M1.4 : Dynatext gives Dynatext 3.0 Config Error 5055
Xilinx Answer #3577 : 3100 F1.4/A1.4: NGDANNO: FATAL_ERROR:basna:basnasite.c:131.1.3 - cannot find BEL delay TCKI...
Xilinx Answer #3578 : Design Manager M1: eXceed - Invoking the GUI produces wind/u error 192: X-Resource: DefaultGUIFontSpec
Xilinx Answer #3579 : CPLD: 9500: What are the checksums in a JEDEC file and how do I read it?
Xilinx Answer #3580 : Foundation F1.5: Is it year 2000 compliant?
Xilinx Answer #3581 : EZTAG 6.0.1: How to Program without Erasing from the command line.
Xilinx Answer #3582 : Quick Start Guide for Xilinx Alliance Series 1.4: where to find it on the web?
Xilinx Answer #3583 : FPGA Express: How to avoid latch inferences
Xilinx Answer #3584 : SYNPLIFY: How to use OSC5, OSC52, and CK_DIV cells for the XC5200 in HDL?
Xilinx Answer #3585 : M1 PAR: Is there a way to prevent route-thrus?
Xilinx Answer #3588 : Design Manager/Template Manager M1.4: Customized options not added to template.
Xilinx Answer #3590 : Foundation XVHDL, CPLD: How to set global signals (tristate, set/reset, clock)
Xilinx Answer #3592 : Spartan: What library components in the 4000E library are not supported by spartan devices
Xilinx Answer #3593 : M1.5i: TRCE/Timing Analyzer: 0 items analyzed for OFFSET timespec
Xilinx Answer #3594 : SYNPLIFY: How to invert the reset (GSR/GR) pin on the STARTUP block in HDL?
Xilinx Answer #3595 : NGDBUILD: "logical block ' ' of type 'READBACK' is unexpanded" with a Synplify netlist
Xilinx Answer #3596 : CPLD: XC9500/XL : What cables and voltages can I use to program a CPLD?
Xilinx Answer #3597 : Fatal_error:x3kma:x3kmarmunused.c:120:1.8 remove input sig U9/$Net00047_ from comp U9/$I67 causes empty F func.
Xilinx Answer #3599 : Foundation F1.x HDL Editor: Bus pins not created for ABEL macros
Xilinx Answer #3604 : HDL Editor: Saving file opens Real Player
Xilinx Answer #3605 : Foundation F1.x, XABEL: ahdl2blf exited with error code 1
Xilinx Answer #3606 : Foundation F1.4: PDF versions of Quickstart Guide, Express User Guide, Release Notes (docs)
Xilinx Answer #3608 : M1.5/2.1i JTAG Programmer: How to create an SVF file
Xilinx Answer #3610 : Design Manager M1/6.0.1: How to change properties of the default Web Browser/Report Browser/ Editor
Xilinx Answer #3611 : NGDBUILD: "logical block" of type 'DFFRSE' is unexpanded with a Synplify netlist
Xilinx Answer #3615 : MAP M1.4.12: FATAL_ERROR:x4kma:x4kmaclkbuf.c:591:1.25 - No input sig on CLKBUF inst_name.
Xilinx Answer #3616 : A1.4/F1.4 Map - Map runs out of memory on designs containing more than 64K logic primitives.
Xilinx Answer #3617 : A1.4/F1.4 Map - Map causes an invalid page fault inmodule libbaste.dll at...
Xilinx Answer #3618 : A1.4/F1.4 Map - Map enhancement to add support for guiding BUFGP/S for floorplanning
Xilinx Answer #3619 : A1.4/F1.4 DC2NCF: set_output_delay command affects following set_max_delay command
Xilinx Answer #3622 : Workview Office: Required License file not found (Errror 8030)
Xilinx Answer #3624 : FPGA Express v2.x (Foundation & Alliance): How to install FPGA Express v2.x for use on a PC network
Xilinx Answer #3625 : V1.5, V1.4 COREGEN: How VLLINK.BATand VLLINK are invoked by the COREGEN GUI in v1.4 and v1.5 / debugging problems with VLLINK
Xilinx Answer #3627 : 2.1i, V1.5, V1.4 COREGEN GUI: Hourglass "busy" cursor lingers indefinitely until mouse is moved
Xilinx Answer #3628 : V1.5, V1.4 COREGEN: Errors when loading spec sheets in Acrobat 2.1
Xilinx Answer #3629 : V1.5, V1.4: COREGEN VIEWLOGIC: PINORDER property/attribute is visible on Viewlogic symbols generated by COREGen
Xilinx Answer #3630 : Cable - Can I use the Parallel Cable III (JTAG Cable) to configure an FPGA?
Xilinx Answer #3631 : FPGA Configuration: Unconnected MODE pins may result in failed configuration for 4000/X devices
Xilinx Answer #3632 : M1.4:FATAL_ERROR:baste:bastetspec.c:1333:1.69 - TNM TI_H1 on NET 'TI_H1' has a reference that has no NC_BEL and no TECHMAP_SIGNAL
Xilinx Answer #3633 : V1.5, V1.4 COREGEN: How to uninstall it
Xilinx Answer #3635 : Naming restrictions for CORE Generator modules (upper case names are illegal)
Xilinx Answer #3639 : V1.5, V1.4 COREGEN: How do I get my COREGen module implementation to match the performance / speed specified in the COREGen spec sheet?
Xilinx Answer #3641 : A1.4, F1.4, MTI: VHDL Timing Simulation produces "Error: a positive value of WIDTH must be specified"
Xilinx Answer #3649 : Foundation F1.4: Incorrect pin name in symbol editor
Xilinx Answer #3650 : JTAG - Using ATEs ( hp3070, teradyne, generad ) to program Xilinx devices. General debugging.
Xilinx Answer #3652 : JTAG - Troubleshooting hints for the Embedded microprocessor ISP programming
Xilinx Answer #3653 : CPLD: XC9500: Device fails to erase when used in an embedded or ATE environment
Xilinx Answer #3654 : A1.4/F1.4 PAR - Problems with placement of Wide Edge Decoders or associated Pullups.
Xilinx Answer #3655 : M1.4 MAP: FATAL_ERROR:x4kma:x4kmamerge.c:4429:1.145.12.5 - Missing signal on pin 10
Xilinx Answer #3656 : XC9500: IDCODE instruction fails when used in an embedded or ATE environment using svf files
Xilinx Answer #3657 : MAP, PAR: Does Map or PAR insert global buffers on high fanout nets and/or unbuffered clock nets?
Xilinx Answer #3658 : V1.4.0 COREGEN: Known Problems / Issues (README file / release document).
Xilinx Answer #3661 : M1.4, map, Readback, NT, Dr.Watson: Exception: access violation...
Xilinx Answer #3662 : M1.4, map, Fatal_Error:x4kma:x4kmacarry.c:2946:1.130 - Illegal call to swap...
Xilinx Answer #3663 : Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R
Xilinx Answer #3664 : M1.3/M1.4 Map: FATAL_ERROR:baste:bastetspec.c:1737:1.69
Xilinx Answer #3665 : fatal error in map on a 4052xl design.
Xilinx Answer #3666 : M1.4 Bitgen -- Output using OMUX2 stuck low...
Xilinx Answer #3668 : V1.5, V1.4 COREGEN: How to determine the build version of the CORE Generator GUI
Xilinx Answer #3669 : Flow Engine M1: Error in reading flow definition file; unable to continue
Xilinx Answer #3670 : COREGen v1.4.0, Windows: Blank / empty warning message boxes pop up when warning message is too long on 800x600 video resolution (e.g., Viewlogic, PDA FIR)
Xilinx Answer #3672 : Hardware Debugger: Readback verification disabled in XC5200 designs...
Xilinx Answer #3673 : 2.1i, V1.5, V1.4.x COREGEN: Solaris Stopwatch "busy" cursor or Windows hourglass cursor lingers (seems to hang) after an operation is completed.
Xilinx Answer #3674 : ** OBSOLETE ** V1.4.0 COREGEN: Can v1.4.0 be installed over the Alpha 3.0.x release?
Xilinx Answer #3675 : V1.5, V1.4 COREGEN: Which cores / modules are being shipped in these releases?
Xilinx Answer #3676 : COREGEN v1.4.0: How can I get a copy of the CORE Generator v1.4.0 CD?
Xilinx Answer #3677 : V1.5, V1.4 COREGEN: How can I install AcroRead on a Solaris system if it is not already installed?
Xilinx Answer #3678 : Foundation F1.4: Project Manager slow to open in Windows NT
Xilinx Answer #3679 : FPGA Express 2.0/Synopsys: RISING_EDGE vhdl syntax not supported. (VHDL-2204)
Xilinx Answer #3681 : V1.5, V1.4 COREGEN, LOGIBLOX: Differences between COREGen and LogiBLOX, which modules are generated as RPMs
Xilinx Answer #3682 : Foundation F1.4: Error when opening: "pcm:file timecore.cpp, line 58"
Xilinx Answer #3684 : FPGA Configuration: DONE Pin does not go HIGH...
Xilinx Answer #3686 : M1.4: FATAL_ERROR:baslo:basloglobal.c:35:1.9 - on line 972 of file "baslodriver.c"
Xilinx Answer #3687 : M1.4 Floorplanner - ACD files changes needed for xc4000.acd, xc4000e.acd, xc4500e.acd for Floorplanner
Xilinx Answer #3690 : M1 Par or HITOP, ERROR: /usr/lib/dld.sl: Unresolved symbol: seekoff_9streambuf... libbasrw.sl running Xilinx DM through Mentor B.1-B.4
Xilinx Answer #3692 : M1.4 XC4000XV Speed Files - A Patch is available with new 40125XV speeds files.
Xilinx Answer #3693 : CONCEPT: How to LOC global buffers in Concept schematic for the XC4000 family?
Xilinx Answer #3694 : V1.5, V1.4 COREGEN: Limitations on running the CORE Generator over networks on UNIX & Win95 platforms
Xilinx Answer #3695 : V1.4 COREGEN, VIEWLOGIC: "The VLLINK.BAT file has a line that is longer than 254 characters."
Xilinx Answer #3696 : COREGen v1.4.0: COREGen overwrites files in the working or project directory without checking with the user
Xilinx Answer #3697 : V1.5, V1.4 COREGEN: COREGen does not release CPU after generating a core module
Xilinx Answer #3699 : Flexlm, security, TCP/IP, modem, ISP: License server only works when ISP is connected to through a modem.
Xilinx Answer #3700 : V1.4.0 COREGEN, VIEWLOGIC: "ERROR starting PM. Missing LIBBASUT.DLL"
Xilinx Answer #3701 : Hardware Debugger: Configuring FPGA with Parallel Cable fails, Serial Cable works.
Xilinx Answer #3702 : V1.5, V1.4 COREGEN: Parameter File Information tables in the COREGen datasheets
Xilinx Answer #3703 : FPGA Configuration: XC4000XL internal signal stuck LOW.
Xilinx Answer #3704 : M1.4: Prom File Formatter uses different format for byte-wide prom sizes
Xilinx Answer #3705 : Foundation Express, XC9500: Recommended synthesis and fitter options for CPLDs
Xilinx Answer #3706 : Foundation 1.4, MAP: ERROR:basnu:93 - logical block <instance number> of type "OBUF" is unexpanded... when OMUX2 is used in XNF netlist
Xilinx Answer #3707 : WINDOWS NT: General debugging suggestions on handling Dr. Watson Errors
Xilinx Answer #3708 : A1.4 Install: Possible problem with BASE install and Spartan
Xilinx Answer #3709 : XC4010E CB196: pin locations for the XC4010E CB196 are incorrect
Xilinx Answer #3710 : M1.4:Setting Up Dynatext Browser or OnLine Books if not installed (PC)
Xilinx Answer #3711 : Foundation F1.3/F1.4: Cannot select 4000EX/4000XL, Spartan devices when creating new project
Xilinx Answer #3712 : Foundation F1.4: Sentinal Driver Causes Conflict with Printer Driver
Xilinx Answer #3713 : V1.4 COREGEN: Integer arithmetic overflow during VHDL behavioral simulation of SQRT (square root) function
Xilinx Answer #3715 : 2.1i JTAG Programmer - ... too many mismatches ... or ... frame # ...
Xilinx Answer #3716 : Foundation F1.4 Project Manager: Restore Project returns a blank window under Win95
Xilinx Answer #3717 : How to import Synplify's XNF netlist into the Foundation schematic?
Xilinx Answer #3719 : XABEL (DS-371) and Alliance software; workstation support
Xilinx Answer #3720 : M1.3/M1.4: Hitop hangs for 9500 design
Xilinx Answer #3721 : Foundation F1.4: Symbol references conflict assigned to same symbol
Xilinx Answer #3722 : A1.4/F1.4 Map - XC5200 combinatorial latch implemented wrong in a f5_mux.
Xilinx Answer #3723 : A1.4/F1.4 Map - Map crashes with segmentation fault for a particular case.
Xilinx Answer #3724 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...
Xilinx Answer #3725 : A1.4/F1.4 Map - FATAL_ERROR:x4kma:x4kmamerge.c:1561:1.145.12.7 - No flop rt available.
Xilinx Answer #3726 : A1.4/F1.4 MAP: Map corruption during logic replication loses HLUT connection.
Xilinx Answer #3727 : A1.4/F1.4 Bitgen - ERROR:x4kbs:18 - Tiedown failed. 2 untied nodes.
Xilinx Answer #3728 : A1.4/F1.4 EPIC - Several fixes have been added to fix EPIC crash problems.
Xilinx Answer #3729 : COREGen v1.4.0: MS-DOS box on the Windows 95 taskbar does not terminate when you exit COREGen
Xilinx Answer #3730 : M1.4 CPLD Fitter: Combinatorial logic duplicated with multilevel logic optimization
Xilinx Answer #3732 : M1.4 Hitop - hitop error: Error:rg119
Xilinx Answer #3733 : M1.4 Hitop - Optimization disregards that control signals can have only 1 pterm.
Xilinx Answer #3734 : When using Turns Engine, you are unable to nice the PARs that are spawned off
Xilinx Answer #3735 : FPGA Express: Concatenating select bits of mux causes error VSS-1029
Xilinx Answer #3737 : M1.4 Ngd2vhdl - The TOC cell created by ngd2vhdl does not contain WIDTH generic.
Xilinx Answer #3738 : M1.4 Ngd2vhdl - 2-dimensional array used in .vhd file but type not declared
Xilinx Answer #3739 : M1.4 Back Annotation - List of all software updates available for M1.4 back annotation.
Xilinx Answer #3741 : A1.4 - Problems reading Answers Book from Dynatext viewer
Xilinx Answer #3742 : A1.4/F1.4 PAR - PAR tries to insert bogus route-thru in clock IOB.
Xilinx Answer #3746 : What is the dimension of the heatsink area in the HQ208 package
Xilinx Answer #3747 : M1.3 Mentor calc_sot tutorial is missing VHDL source files
Xilinx Answer #3748 : CPLD: XC9500/XL: Generic XC9500/XL IBIS (I/O Buffer Information Specification) model is on the FTP site
Xilinx Answer #3749 : M1 PAR: Multi-Pass Place and Route: The Design Score and what it means
Xilinx Answer #3753 : M1.5i/2.1i: Constraints: UCF to PCF conversion examples
Xilinx Answer #3754 : V1.5, V1.4 COREGEN: Xilinx M1.4 and Viewlogic must be installed first for Viewlogic users, and Foundation must be installed for Foundation users
Xilinx Answer #3755 : XABEL, F1.4: App Note available for using XABEL with F1.4
Xilinx Answer #3756 : FSM Editor F1.4: Vhdl code synthesis errors, Enum_encoding not declared
Xilinx Answer #3757 : Map: Removes logic that is tied to pads locked to Unbonded pins.
Xilinx Answer #3759 : CPLD: XC9500/XL/XV: Which XC9500 devices are electrically compliant to PCI specification?
Xilinx Answer #3760 : A1.4/F1.4 Map - FATAL_ERROR:basnc:basncsignal.c:262:1.62 - Could not find a
Xilinx Answer #3761 : A1.4/F1.4 Map - MAP introduces DRC problem: WARNING:x4kdr:82 - Blockcheck: The pin "F1"...
Xilinx Answer #3762 : LogiCORE PCI: What is the functionality of latency timer?
Xilinx Answer #3766 : MAP M1.4: x4kma:312 - The following symbols could not be constrained to a single CLB (Two F-LUT's, an H-LUT, and carry logic).
Xilinx Answer #3767 : A1.4 and Modelsim: How to use the OSC4 component with VHDL simulation (Functional and Timing)
Xilinx Answer #3768 : MAP M1.4: ABEL blocks in FPGA not optimized, result in high utilization (ERROR:x4kma:253 - The design is too large for the given device...)
Xilinx Answer #3769 : 98 Databook: PG68 package diagram on page 10-36 has missing pin information.
Xilinx Answer #3770 : A1.4/F1.4 - Installation of Software Updates.
Xilinx Answer #3772 : A1.4/F1.4 Map - Map connects xc5200 readback symbol incorrectly.
Xilinx Answer #3773 : M1.4 PAR, TRCE, Timing - How to invoke the "KPATHS" timing algorithm.
Xilinx Answer #3774 : JTAG Cable cannot be used for FPGA configuration with PROG pin connected.
Xilinx Answer #3779 : SPROMs (XC1700): How to program reset polarity on Xilinx SPROMs
Xilinx Answer #3781 : FPGA Express: "XNF Bus style" checkbox in Synthesis->Options->Project defined
Xilinx Answer #3782 : Foundation F1.4: Moving pin on a logiblox symbol in Symbol Editor does not update symbol.
Xilinx Answer #3785 : V1.4 COREGEN: Blank DOS box appears when COREGen is invoked with Windows Display set to "True Color", entire program hangs; Windows NT.
Xilinx Answer #3786 : M1.4 Map - How to produce map reports with full details.
Xilinx Answer #3787 : EZTAG/JTAG Programmer: How to create a SVF file that performs a blank check operation?
Xilinx Answer #3790 : V1.4.0 COREGEN: Output Options dialog box background color is two shades of gray instead of one uniform shade
Xilinx Answer #3791 : 2.1i, V1.5, V1.4 COREGEN: 4K Synchronous FIFO LogiCORE output is only valid when RE is enabled
Xilinx Answer #3792 : Exemplar Leonardo 4.x: How to instantiate READBACK using RDBK and RDCLK
Xilinx Answer #3793 : Foundation 1.4: Timing violation message in foundation timing simulation for 9500
Xilinx Answer #3794 : M1.4 PAR: FATAL_ERROR:basnd:basndutils.c:130:1.6 - Internal Error - signal has a loop
Xilinx Answer #3798 : MAP WARNING:x4kma:78 - STARTUP symbol "$I1" (output signal=<none>) conflicts with other symbol connections on the clock signal
Xilinx Answer #3799 : ngd2vhdl v1.4p ---Latest patch fixes 2-dimensional array problem and ROC pulse width
Xilinx Answer #3801 : M1.4 CPLD - A software update is available to support the new CSP48 package in the XC9000 family.
Xilinx Answer #3802 : M1.4 CPLD - Timing violation: Slow simulation model produced with the "Use Local Macrocell Feedback" switch
Xilinx Answer #3803 : M1.4 CPLD - Fitter report & timing simulation (F1.4) gives incorrect equations.
Xilinx Answer #3804 : M1.X JTAG Programmer: Clicking icon makes hourglass appear, then goes away
Xilinx Answer #3805 : EZTag: SVF file generation mode doesn't work when data protection option is enabled.
Xilinx Answer #3807 : XACT-CPLD: Listing of all the Fitter patches
Xilinx Answer #3808 : EZTAG v6.x: List of various fixes available in the latest patch
Xilinx Answer #3809 : XACT-CPLD: Mentor & Cadence interface patches available for the XC9500 family
Xilinx Answer #3810 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...
Xilinx Answer #3811 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:1333:1.69
Xilinx Answer #3812 : M1.4 PAR - Nodes list for Turns Engine doesn't accept special characters
Xilinx Answer #3813 : 1.5i, 2.1i XC4000XL PAR - Router duplicates registers for use as output to output route-thrus.
Xilinx Answer #3814 : A1.4/F1.4 PAR - PAR crashes during placement of XC4000XL device.
Xilinx Answer #3815 : A1.4/F1.4 Ngdanno - INTERNAL_ERROR:basnb:basnbconv.c:546:1.21
Xilinx Answer #3817 : M1.x: EPIC: How to change modes in EPIC?
Xilinx Answer #3818 : F1.4 General - Chinese, Korean and Japanese encodings corrupted by US Foundation Design Entry CD
Xilinx Answer #3819 : V1.4.0 COREGEN: CD jacket has an error in path to workstation install--/cdrom.cdrom0/install should be /cdrom/cdrom0/install
Xilinx Answer #3820 : CONCEPT: How to place a TIG property on a net in your schematic?
Xilinx Answer #3821 : Foundation, MAP: Excessive logic removed (trimmed) from a design captured in Foundation schematic.
Xilinx Answer #3822 : A1.4/F1.4 Map - Guided map crashes
Xilinx Answer #3825 : M1 NGDBUILD error based51: on or above line ... in design.edf, using Mentor flow
Xilinx Answer #3826 : Spartan: Are Spartan devices footprint compatible with 4000E/XL devices?
Xilinx Answer #3827 : Workview Office EDIFNETO: Error opening project from ygraflib
Xilinx Answer #3829 : M1.4: ngd2edif: FATAL_ERROR:baspm:baspmdlm.c:99:1.18 - dll library <vwlne> does not exist
Xilinx Answer #3830 : A1.5: Cadence Concept 9604 and 97a: How to target a Spartan device
Xilinx Answer #3831 : M1.4 LOGIBLOX: MAP may convert 5K Logiblox adder CY_MUX's to FG muxes and leaves buffers in.
Xilinx Answer #3832 : 98 DATA BOOK: Package drawing of BG352, BG432 on page 10-34 shows incorrect pin order
Xilinx Answer #3833 : F1.4 Schematic: How to import and edit a macro without affecting the original source file
Xilinx Answer #3839 : V1.5, V1.4 COREGEN, NGD2EDIF: ngd2edif: FATAL_ERROR:baspm:baspmdlm.c:99:1.18 - dll library <vwlne> does not exist
Xilinx Answer #3840 : V1.5, V1.4 COREGEN: How to obtain the latest COREs, software enhancements, and patches / SDA FIR Filter module available in v1.4.0p1 patch supplement
Xilinx Answer #3843 : A1.4/F1.4 Map - FATAL_ERROR:x4kmamerge.c:2858:1.145.12.11 - Too many signals to move..
Xilinx Answer #3845 : BG-432 package pinout info error
Xilinx Answer #3846 : COREGEN: Tips on simulating the SDA FIR filter
Xilinx Answer #3847 : WVO7.4, M1.4, 5200:ERROR: baste:266-An extension is required on the "RLOC" parameter for CY_MUX/FDCE
Xilinx Answer #3848 : Cannot Read 1998 Q1 Applinx CD on Workstations running Solaris. <file> not found
Xilinx Answer #3850 : V1.4.0 COREGEN: What's new in the v1.4.0 release
Xilinx Answer #3851 : Foundation, Esperan VHDL Tutorial: Cannot be installed/used over a networked CD ROM drive
Xilinx Answer #3852 : NGD2VER/NGD2VHDL: Bus indexes are always declared in descending order within simulation netlist
Xilinx Answer #3856 : HW-130: 1701/17512 programming problem with the 4.30 version of the algorithm
Xilinx Answer #3857 : Power sequencing issue forXC3100L, XC3000L, XC4000XL and Spartan-XL : where can we find the information
Xilinx Answer #3859 : M1.4 Flexlm license manager: Auto-start does not work on Win95 PC
Xilinx Answer #3860 : Foundation Simulator: How to fit more simulation time in one page when printing it.
Xilinx Answer #3862 : V1.4.0 COREGEN: "Parameter value is not in allowed range"
Xilinx Answer #3863 : 2.1i, V1.5, V1.4 COREGEN, FOUNDATION EXPRESS: How to generate Foundation functional simulation files for a VHDL design
Xilinx Answer #3867 : M1.5i/2.1i: Timing Analyzer: No default physical constraints file "\...\map.pcf" was found.
Xilinx Answer #3868 : M1.4 Map - FATAL_ERROR:baspm:baspmdevkey.c - Unable to load file or override file "mapl2ppins.acd"
Xilinx Answer #3872 : COREGEN V1.4.0, FOUNDATION F1.3: "Invalid call to .DLL" error during netlist creation in Foundation F1.3 after installing COREGen v1.4.0
Xilinx Answer #3873 : 2.1i COREGEN, WORDPAD: "The document xxxx is in use by another application and cannot be accessed." / The CORE Generator does not release its "lock" on an XCO file
Xilinx Answer #3874 : Foundation Schematic F1.4 : Options->Replace Symbol replaces all instances of symbol
Xilinx Answer #3875 : A1.4/F1.4 Map - Map connects wrong LUT output to FFY D input
Xilinx Answer #3876 : A1.4/F1.4 5200 Map - FATAL_ERROR:baste:basteparse.c:333:1.1
Xilinx Answer #3877 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...
Xilinx Answer #3879 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:982:1.69.14.2 - NC_BEL ...
Xilinx Answer #3880 : A1.4/F1.4 - PC only PAR crash during placement of high density devices (>= 4085XL).
Xilinx Answer #3883 : 2.1i, 1.5, V1.4 COREGEN: How to permanently set the default output format for COREGen
Xilinx Answer #3884 : 2.1i, V1.5, V1.4 COREGEN:: versions of third party CAE platforms and M1 supported by COREGEN
Xilinx Answer #3888 : M1.5i/2.1i: TRCE : How does trce list the number of timing errors?
Xilinx Answer #3889 : M1.x: EPIC: Can an Epic script be launched without invoking the GUI?
Xilinx Answer #3891 : COREGEN: What is "SystemView" from Elanix, and how can I get more information on it?
Xilinx Answer #3892 : How to start the license manager automatically at boot time (Unix workstation)?
Xilinx Answer #3895 : Foundation F1.4, Translate: Where does the &__A__ net name in my warning come from?
Xilinx Answer #3897 : Foundation F1.4, XC95144-20: XC95144-20 device is available from Design Entry but not Implementation
Xilinx Answer #3898 : M1, ngdbuild, Error: basnu:94 - logical root block ... of type ... is unexpanded.
Xilinx Answer #3900 : FPGA Express VHDL: Type mismatch on left and/or righ operand of binary operator. (VSS-523)
Xilinx Answer #3903 : M1.4 Map - FATAL ERROR: Too many signals to move and not enough slots on comp
Xilinx Answer #3904 : M1.5 LOGIBLOX introduces .ngc as new file extension for the implementation netlist
Xilinx Answer #3905 : Workstation Install: How to mount Xilinx CD-ROM on workstations
Xilinx Answer #3908 : LOGIBLOX: Legal ranges reported by LogiBLOX for base 2 and base 4 numbers are incorrect.
Xilinx Answer #3909 : M1.4: WARNING:basts:75 - TPTHRU "IBUS_PATH" is on NET "IBUS2", which is notconnected to any drivers.
Xilinx Answer #3912 : F1.4, F1.5 Project Manager: After unarchiving (restoring) project, design changes are not reflected in the implementation.
Xilinx Answer #3913 : 2.1i LOGIBLOX: Bus Width - "Other" setting does not work correctly on UNIX platforms.
Xilinx Answer #3914 : UNISIMS/SIMPRIMS: Usage of GSR_SIGNAL, GR_SIGNAL, PRLD_SIGNAL, and GTS_SIGNAL text macros in Verilog simulation?
Xilinx Answer #3915 : V1.4.0 COREGEN: 30-bit bus input width limit on COREGEN modules / Cannot specify 32-bit input bus widths / integer arithmetic overflow
Xilinx Answer #3916 : Cable - What is the part number for Parallel cable III
Xilinx Answer #3923 : Aldec Active-VHDL: Key inactivates Foundation install (puts into evaluation mode)
Xilinx Answer #3924 : SYNPLIFY: How to instantiate an FMAP or HMAP (RLOC) in the HDL code?
Xilinx Answer #3926 : Bitgen M1.4: -t tie option still uses critical nets for tying.
Xilinx Answer #3927 : Design Manager/Flow Engine M1.4: Incorrect DonePin value for Bitgen (XC3000A ONLY)
Xilinx Answer #3928 : Foundation F1.4 XVHDL: Using JTAG pins (TDI, TDO, TCK, TMS) for general I/O
Xilinx Answer #3929 : FPGA Configuration: Connecting PROM for master-serial configuration.
Xilinx Answer #3930 : SIMPRIMS: An X_FF waveform does not look correct and may be mistaken for a latch in Verilog SIMPRIMS simulation
Xilinx Answer #3931 : F1.4,docs,base,device_support: Incorrect list of supported devices in F1.4 Release Document
Xilinx Answer #3932 : Foundation F1.4 Simulator: Explanations of Functional and Timing modes in Simulator
Xilinx Answer #3933 : F1.4,M1.4,Map,license,Error: basse ... No such feature exists (-5,116)
Xilinx Answer #3934 : FlexLM,security,network: How setup floating license on dummy ethernet card?
Xilinx Answer #3935 : WEBLINX: Problems with Xilinx WebLINX or CoreLINX passwords, logging on, or registering on WebLINX
Xilinx Answer #3937 : M1.4 TSIM - ERROR:basnu:115 - logical net "b_reset" has both active and tristate drivers.
Xilinx Answer #3938 : F1.4, F1.5, Timing Simulator: '-' in signal names converted to '_'
Xilinx Answer #3939 : M1.4 Map - WARNING:baspl:291 - The IOB component "io<0>" could not be placed.
Xilinx Answer #3940 : M1.4 Speed Files - New Spartan Speed Files are available.
Xilinx Answer #3941 : NGDBUILD 1.4/1.5: basnb: 79- Pin mismatch with FPGA Express XNF instantiated in Foundation schematic
Xilinx Answer #3943 : M1.4 map:ERROR:x52ap:13 - The comp (mapped physical logic cell) "blah" is not placed.
Xilinx Answer #3946 : Foundation F1.4 Schematic Editor: 'Print all macros' command does not print correctly
Xilinx Answer #3947 : Coregen v1.4: Exemplar flow (with and without LogiBLOX) (basnb:79 - Pin mismatch, basnu:93 - Unexpanded...).
Xilinx Answer #3949 : COREGEN: Registered Scaled Adder: What is the "floor()" function mentioned in the data sheet?
Xilinx Answer #3953 : Foundation XVHDL: mmvhdl.exe not found when synthesizing
Xilinx Answer #3955 : F1.4, Simulator: Probes from schematic macro don't appear in Simulator.
Xilinx Answer #3957 : The readback bitstream in Dynatext is unclear.
Xilinx Answer #3959 : Foundation 1.4: Logiblox will not open from Schematic Editor or Project Manager
Xilinx Answer #3964 : XC4000E/EX/XL/XV: Is it possible to implement a "true" dual port RAM in a Xilinx FPGA?
Xilinx Answer #3965 : V1.5, V1.4.0 COREGEN: COREGen may create .VHX, XNF(v1.4)/EDN(v1.5) and .XSF output files even when not directed to do so
Xilinx Answer #3967 : Can you create test vectors in EZtag?
Xilinx Answer #3969 : M1.4 Bitgen - Tie fails (1 untied node)
Xilinx Answer #3970 : M1.4 Speed files - Pullup res. for x4002xl and wire segment res. for x4085 is incorrect
Xilinx Answer #3971 : M1.4 Speed Files - An M1.4 XC4000XL speed file update is available that also includes bitgen updates.
Xilinx Answer #3978 : A1.4 ngd2edif -v mentor on a PC gives FATAL_ERROR:baspm:baspmdlm.c:99:1.18 dll library <mtrne> does not exist
Xilinx Answer #3979 : How to startup Galileo Extreme from a command line with Leonardo software and license?
Xilinx Answer #3980 : FPGA Express: Instantiating I/O in VHDL.
Xilinx Answer #3982 : FPGA Hardware: Where to get ESD information.
Xilinx Answer #3984 : XABEL, Foundation F1.4: XABEL patch available on Web site
Xilinx Answer #3986 : Design Manager M1: The specified part is either invalid or not supported (XC95***/XL)
Xilinx Answer #3988 : M1.4/M1.5 Map - Error: x4kma:215-the component AAA is a synchronous RAM, which is not available in the xc4000 architecture
Xilinx Answer #3992 : FPGA Express: How to implement a Synchronous Reset in VHDL or Verilog
Xilinx Answer #3993 : A1.4/A1.5 XSI: What to do when insert_pads fails in FPGA Compiler
Xilinx Answer #3996 : Foundation F1.4 LogiBLOX: Invoking LogiBLOX through Foundation F1.4 for 4000XL designs uses 4000EX family.
Xilinx Answer #3999 : FPGA Express 2.0.x: Instantiating I/O in Verilog.
Xilinx Answer #4001 : M1.4.12: TNM does not get attached to all FFS (FDCE)
Xilinx Answer #4005 : M1.x: EPIC: Arc x/y offset file <unknown> not found
Xilinx Answer #4006 : M1.x: EPIC: How to manually route signals
Xilinx Answer #4007 : HW-130/Third party programmers (such as DATA IO, BP): Supported file formats .mcs, .exo, .tek but not .bit
Xilinx Answer #4008 : M1.x: EPIC vs. XDE and other useful EPIC Tidbits
Xilinx Answer #4009 : V1.5, 1.4 COREGEN, VHDL: where is the UL_UTILS.vhd library for behavioral simulation
Xilinx Answer #4011 : V1.5 COREGEN: coregen.ini variables
Xilinx Answer #4016 : F1.4: How to add parameters to Foundation Symbols Parameters list
Xilinx Answer #4017 : COREGEN: What is SystemLINX?
Xilinx Answer #4020 : V1.5 COREGEN, FOUNDATION: Version of Foundation compatible with COREGEN V1.5
Xilinx Answer #4024 : DESIGN MANAGER/LOGIBLOX/etc... M1.5 versions of XILINX GUI-based programs issue an error about an old version of the windu_registryd program (WS ONLY)
Xilinx Answer #4025 : M1.4 Map - FATAL_ERROR:x4kma:x4kmawritengd.c:82:1.17 - F-LUT in map
Xilinx Answer #4026 : M1.5, M1.4 MAP, COREGEN - ERROR:x4kma:387 - Unable to obey design constraints which require the combination of the following symbols into a single CLB: on RLOC'd Coregen RAM, FIFO's
Xilinx Answer #4028 : M1.5i/2.1i :Post Layout Timing Report: No skew warning given for internal clocks
Xilinx Answer #4029 : 98 DATABOOK: Does Xilinx have XC4028EX or X4036EX parts in -1 Speed grade?
Xilinx Answer #4031 : M1.4 General - XC4000XL speed file upgrade adds -08 speed grade for 4013XL, 4036XL and 4062XL.
Xilinx Answer #4034 : SYNPLIFY: Conditions of "Force GSR Usage" - to generate the STARTUP block?
Xilinx Answer #4038 : SYNPLIFY: How to change the colors used in HDL Analyst?
Xilinx Answer #4041 : V1.5.x COREGEN, NGDBUILD, (VIRTEX BLOCK RAM): "ERROR: BASNB Pin mismatch". COREGEN does not allow you to select the netlist bus delimiter format if one of your selections is VHDL or Verilog I nstantiation Template.
Xilinx Answer #4043 : Foundation Schematic: Why does the Date in Table Setup always change when you use UNDO
Xilinx Answer #4046 : Foundation Schematic Editor: Does Schematic Editor have multiple Undo capability?
Xilinx Answer #4047 : FPGA Express: Constraints GUI uses lower level heirarchical clock name
Xilinx Answer #4048 : M1.4 Fitter/Hitop - Incorrect logic generated.
Xilinx Answer #4049 : MTI: Functional simulation with STARTBUF not connected properly may cause errors
Xilinx Answer #4050 : NGDBUILD, XNF2NGD, and EDIF2NGD: "Bad part type" errors
Xilinx Answer #4051 : M1.4 CPLD(9500): FPGA-EXPRESS - VHDL, Input to toggle control of FF inverted instead of the output.
Xilinx Answer #4056 : SPROMS: XC1700E/EL are the replacements for the XC1700D/L (up to the 17256D/L commericial and industrial grades)
Xilinx Answer #4060 : M1.4 Map - Map creates TIMEGRPs in PCF file that are incorrect.
Xilinx Answer #4061 : M1.4 Map - Unable to RLOC tbufs to column 0: ERROR:baste:117 - RLOC_ORIGIN value ...
Xilinx Answer #4062 : F1.4, F1.5 Simulator: Not all signals are listed in Component Selection window; how to show all signals
Xilinx Answer #4063 : F1.4 Schematic: "Create schematic from netlist" loses INV from symbols in XNF file
Xilinx Answer #4064 : M! Design Manager: What command line options can be used to invoke the Design Manager ?
Xilinx Answer #4065 : M1.5: NGDBUILD/CSTTRANS: Why INST can sometimes be used instead on NET for Pad LOCs
Xilinx Answer #4066 : EZTAG help:Help file is not installed or not installed properly
Xilinx Answer #4067 : M1.4 EPLD-FIT (1.4): Dr. Watson for Windows NT: hitop.exe
Xilinx Answer #4071 : Can an FPGA be used in combination with an external crystal oscillator as an amplifier?
Xilinx Answer #4072 : M1.4: WARNING:x4edr:21 - Blockcheck: CLB "frfi3_alism_fiCtr_upDown" is configured to use the G LUT as RAM, but the D1 and WE lines use the same pin, which will likely cause a D->WE setup vi olation.
Xilinx Answer #4073 : TRCE M1.4.12: Incorrect minimum period and maximum frequency reported.
Xilinx Answer #4074 : M1.4 PAR - DRC incorrectly posts warning about DPRAM D1 pin when it is unused.
Xilinx Answer #4075 : SYNPLIFY: How to infer synchronous (single-port/dual-port) RAM in HDL (Verilog/VHDL)?
Xilinx Answer #4080 : M1.4 Map - FATAL_ERROR:x4kma:x4kmacarry.c:2842:1.122.12.8 - Illegal call to swap
Xilinx Answer #4081 : 1.5i, 2.1i Map- FATAL_ERROR:x4kma:x4kmaclkinfo.c:786:1.24 - Clkinfo: sitearray overrun: page1$1p/page1$i135.
Xilinx Answer #4082 : M1.4 Map - Input signal driving two paths is corrupted.
Xilinx Answer #4084 : SYNPLIFY: How to disable clock buffer (BUFG) insertion?
Xilinx Answer #4085 : M1.x: Is there a way to access vertical longlines in FPGA (with ucf or pcf constraint)?
Xilinx Answer #4086 : CONCEPT-HDL: Is Cadence's PE 13.x Concept-HDL supported?
Xilinx Answer #4088 : M1.4 XC4000XV - Package File Update adds BG432 package to the XC40125XV device.
Xilinx Answer #4089 : How to simulate Exemplar written VHDL in MTI or QuickHDL. Post synthesis pre NGDBuild
Xilinx Answer #4090 : ERROR:time_sim.vhd(132):Cannot assign to object with mode IN:ce. MTI timing simulation
Xilinx Answer #4092 : F1.4, F1.5 Simulation: How to create an LED (7 seg) drawing on the schematic that lights during simulation.
Xilinx Answer #4093 : 2.1i: 9500/XL: What does TIE and PGND mean in the fitter report?
Xilinx Answer #4098 : NGD2VER: Using the -ism to embed simulation models into the Verilog simulation netlist
Xilinx Answer #4099 : V1.4.0 COREGEN, VF1.3 Foundation: "Call to Undefined Dynalink" while generating a core in COREGen
Xilinx Answer #4109 : V1.4.0 COREGEN, Install, French Windows95: "a file .dll required, MSVCRT.DLL has not been found"
Xilinx Answer #4112 : M1.4 Map - FATAL_ERROR:x4kma:x4kmagrclapse.c:1001:1.90.12.8 - No route-thru available in pack_lutflop() to swap with H input pin 8:
Xilinx Answer #4113 : A1.4/M1.4 PAR - FATAL ERROR:x45nc:x45ncinfo.c:1307:1.25 - Bel PWR_GND_241 found unpacked...
Xilinx Answer #4116 : Cable - The Parallel Cable III (JTAG Cable) will accept 5V or 3V or 2.5V as power supply.
Xilinx Answer #4117 : Mentor, pld_edif2tim: error line 2 illegal identifier "15 encountered from synthesis
Xilinx Answer #4118 : BITGEN M1.4: WARNING:x4kdr:23 - Blockcheck: The comp (mapped physical logic cell) "<comp_name>" does not have any pins that are being used.
Xilinx Answer #4119 : Orcad Express: Timed simulation for Xilinx M1 does not include global reset by default
Xilinx Answer #4120 : Orcad Express: ROM outputs remain low in functional simulation
Xilinx Answer #4121 : Orcad simulation: "Translation failed" when using "Convert XNF to VHDL"
Xilinx Answer #4122 : FPGA Express: Subpaths containing pads grouping incorrectly written by Express
Xilinx Answer #4123 : V1.5 COREGEN, LOGIBLOX, VIRTEX: Virtex ROMs and SelectRAM (distributed RAM, dual port RAM, single port RAM, synchronous RAM) generation support
Xilinx Answer #4124 : Orcad Simulate: Error: "Cannot create file..." occurs when converting XNF to VHDL
Xilinx Answer #4126 : Orcad: Taking a design from Capture, through XACTStep6, to Simulate
Xilinx Answer #4127 : F1.4, F1.5 State Editor: Referencing the same state multiple times by name
Xilinx Answer #4129 : MAP: baste:263- The LOC contraint is not valid for IPAD symbol, which is being mapped to the following site types: CLKIOB
Xilinx Answer #4131 : Design Manager M1.5: New version is created instead of new revision even though the input design netlist has not changed
Xilinx Answer #4132 : M1.5: Constraints Editor: Will not create new ucf file in Solaris. Need to create one from outside DM gui.
Xilinx Answer #4134 : Orcad Express: Assigning Pin location constraints and other Xilinx attributes.
Xilinx Answer #4136 : 2.1i: How to initialize the contents of a RAM primitive via a constraint file
Xilinx Answer #4137 : Design Manager M1.5: Multi-pass place and route (MPPR) naming convention has changed (ex - p1_rev_2_3_4)
Xilinx Answer #4138 : Orcad Capture: Recommended design flow with Capture v7.10 and Xilinx M1
Xilinx Answer #4139 : Orcad Capture: DRC reports port mismatch error in Xilinx design
Xilinx Answer #4140 : Orcad, XNFmerge, XMAKE: Failed to find user defined subhierarchy
Xilinx Answer #4141 : Orcad Express: Using TIMESPEC to set global attributes in Xilinx
Xilinx Answer #4142 : Orcad: Adding third-party Xilinx cores to an Express project
Xilinx Answer #4143 : Orcad Simulate: Simulation error message: [Load085] entity 'xxxx' not found
Xilinx Answer #4144 : Orcad Express: Using Xilinx Alliance Series with Express
Xilinx Answer #4146 : M1.4/M1.5 Map - FATAL_ERROR:x4kma:x4kmaaclk.c:145:1.16.12.2 - More than one driver on clock net.
Xilinx Answer #4147 : Design Manager/Template Manager M1.5: Cannot delete the program/option within Template Manager
Xilinx Answer #4151 : V1.5 COREGEN: Can V1.5 be installed over the V1.4 release?
Xilinx Answer #4152 : V1.5 COREGEN: Which cores / modules are being shipped in this release?
Xilinx Answer #4153 : Orcad Express: DRC check gives error on PULLUP and PULLDOWN components
Xilinx Answer #4156 : M1.5 Timing analysis doesn't use TPTHRU as more specific than FROM:TO
Xilinx Answer #4157 : V1.5 COREGEN: None of the AllianceCore Cores are grayed out when Virtex is selected as the target architecture
Xilinx Answer #4158 : V1.4 COREGEN: How to install the pre-C1.5 version of the DFT/FFT core zip archive
Xilinx Answer #4159 : Mentor Graphics/M1/A1 - Recommendations for improving Cross probing into hierarchy
Xilinx Answer #4160 : A1.4/F1.4 Bitgen - Bitgen crashes on designs with extremely long equation strings in LUTs
Xilinx Answer #4161 : M1.5i/2.1i: Cannot TIMESPEC the TDO/MD1 pin on XC4000E/X FPGAs.
Xilinx Answer #4162 : M1.5i/2.1i: TRCE reports timing loop for Virtex designs with DLL's
Xilinx Answer #4164 : V1.5, V1.4 COREGEN, HP: Folder icons are not displayed when COREGEN is invoked on an HP and GUI is displayed on Solaris
Xilinx Answer #4165 : A1.4/F1.4 MAP - ERROR: x4kma:312 - Following symbols could not be constrained
Xilinx Answer #4166 : V1.5 COREGEN: What's new in the v1.5 release
Xilinx Answer #4168 : Spartan data sheet missing page 41
Xilinx Answer #4172 : Foundation F1.4 Install: Can't find Setup.exe
Xilinx Answer #4174 : 1.5i 9500/XL Fitter - Uses 2 macrocells instead of 1 for combinatorial latch
Xilinx Answer #4179 : C1.4 COREGEN Installation gives message "The Register is Not Properly Configured for CORE Generator. Please Reinstall Original Software."
Xilinx Answer #4181 : M1/Exemplar: How to instantiate Logiblox modules
Xilinx Answer #4182 : M1.4/M1.5: ngdbuild/map:INCDEC-G-0 (cy4_34) is instantiated, got error on INCDEC-G-CI
Xilinx Answer #4184 : A1.5/F1.5 XC3000 Map - GCLK is connected to non clock pin error - ERROR:x3kma:192
Xilinx Answer #4185 : FPGA Express: How to disable clock period specification
Xilinx Answer #4187 : Foundation Schematic Editor: LMACS: The chunk offset is too big
Xilinx Answer #4188 : M1.5i/2.1i: Timing Report: There is no negative offset, setup, or hold time
Xilinx Answer #4190 : FPGA Configuration: State of Dout pin before configuration.
Xilinx Answer #4191 : V1.5 COREGEN: Sample .COE files for Virtex block RAM
Xilinx Answer #4193 : M1.5: Trce core dumps or causes an application error
Xilinx Answer #4194 : 1.5 4KXL PAR- PAR will not utilize "lone" OFFSET constraints
Xilinx Answer #4198 : F1.4 State Editor: Copying and pasting detaches the condition/action text
Xilinx Answer #4200 : FPGA Express 2.x, 3.x: Constraints Editor will not allow assignment of more than 4 BUFGs
Xilinx Answer #4201 : M1.x: BSCAN pins (TDO, TDI, TCK, TMS) are not reported for a 5200 device.
Xilinx Answer #4204 : 4000ex/xl : Can bufge and bufclk be driven in parallel?
Xilinx Answer #4205 : M1.5i/2.1i: TRCE reports only three paths per timing constraint by default/no limit: How to increase it.
Xilinx Answer #4207 : V1.5 COREGEN: Some columns are blank in the (performance/speed) characterization data tables for -08 speed grade parts.
Xilinx Answer #4208 : V1.5, V1.4 COREGEN, FOUNDATION: symbol pin ordering may be inconsistent between the V1.4 and V1.5 releases
Xilinx Answer #4209 : V1.4, V1.5 COREGEN, VIEWLOGIC, FOUNDATION: symbols generated by COREGen do not match those shown in the datasheets for the core.
Xilinx Answer #4211 : A1.4/F1.4 MAP - FATAL_ERROR:x4kma:x4kmagrclapse.c:1001:1.90.12.8 - No route-thru available in pack_lutflop() to swap with H input pin 8
Xilinx Answer #4212 : V1.5, V1.4 COREGEN: Clarification on bus naming convention in COREGEN datasheet tables and block diagrams--N, n, M & m indices
Xilinx Answer #4213 : V1.4.0, V1.5.0 COREGEN: Warning: Your directory path <directory_path> should not contain any directory names longer than 8 characters.
Xilinx Answer #4214 : M1.5: TRCE: Internal constant used to represent NODELAY conflicts with negative delays.
Xilinx Answer #4215 : HQ PACKAGE: What is the lead finish for this package
Xilinx Answer #4216 : F1.4, F1.5 Timing Simulation: Preserving Hierarchy for Foundation timing simulation
Xilinx Answer #4220 : 2.1i COREGEN: "ERROR: SETPROJECT command failed"
Xilinx Answer #4223 : M1.4 5200: TRCE reports "0 items analyzed" on FROM:THRU:TO timespec
Xilinx Answer #4224 : V1.5, V1.4 COREGEN: Cursor (arrow) keys produce numbers when NumLock key is active on Solaris
Xilinx Answer #4225 : 2.1i, V1.5, V1.4 COREGEN: "WARNING: Core 12x12_Multiplier (8x8_Multiplier) did not generate product VerilogSim"
Xilinx Answer #4226 : V1.5, V1.4 COREGEN: Disk full condition may cause Coregen infinite loop (ERROR: java.io.IOException: write error)
Xilinx Answer #4227 : V1.5 COREGEN: Data width is limited to 31 or less for some CORE Generator functions (Single Port RAM, Dual Port RAM, ROM, PDA FIR Filter)
Xilinx Answer #4228 : V1.5 COREGEN: "View Init Values Button" is not supported for Virtex Block RAM
Xilinx Answer #4229 : V1.5, V1.4 COREGEN, SOLARIS: "Load Coefficients" browser displays all files instead of just files with a .coe extension
Xilinx Answer #4232 : V1.5, V1.4 COREGEN: Fixed point Speed-Optimized Multipliers lack CE pin.
Xilinx Answer #4233 : F1.4 Simulator: Deletes Formulae when "Simulate Single Component" option is selected
Xilinx Answer #4235 : M1.4: What temperature was used to obtain the results in the Timing Analyzer/Databook?
Xilinx Answer #4239 : A 1.4 UNISIM XDW : INC_DEC_UBIN_6 does not simulate correctly
Xilinx Answer #4240 : A1.4/F1.4 MAP - Connection to TDO pad lost when signal is merged (WARNING::x4kdr:23 - Blockcheck: The comp (mapped physical logic cell) "DIA_RSCI" does not have any pins that are being used)
Xilinx Answer #4242 : V1.5 COREGEN: Wrong (fixed) time stamp / date in EDIF generated by COREGEN
Xilinx Answer #4244 : Leonardo: How to change the slew rate from Leonardo.(Fast, Nodelay)
Xilinx Answer #4245 : V1.5 COREGEN, VIEWLOGIC, HP: "ERROR: ViewlogicInterface Exiting due to IOException:java.io.IOException: Not enough space" on HP-UX platform
Xilinx Answer #4246 : M1.5 9500/XLConstraints Editor: Clock pads using BUFG symbol not visible in Constraint Editor
Xilinx Answer #4248 : A1.4/F1.4 Map - Map drops internal CLB connection, corrupting logic.
Xilinx Answer #4252 : Design Manager/Template Manager M1.5: Flow Engine reads incorrect settings if a default template is customized
Xilinx Answer #4253 : A1.4/F1.4 Bitgen - Bitgen with TIE Down incorrectly causes some pins (IOB) to be tristated.
Xilinx Answer #4255 : HW-112: Which devices were supported on this Xilinx programmer?
Xilinx Answer #4256 : M1.x: Epic: Adding Readback capability
Xilinx Answer #4257 : Foundation F1.4: 5200 design with xact give xnfprep error 3701: INIT parameter not supported
Xilinx Answer #4258 : SIMPRIMS: Alliance 2.1 changes from 1.5i (or older) for Verilog SIMPRIMS simulation
Xilinx Answer #4260 : A1.4/F1.4 Map - FATAL_ERROR:x4kma:x4kmacarry.c:1134:1.122.12.11
Xilinx Answer #4261 : F1.4, F1.5: Preference changes are carried over to other projects as well
Xilinx Answer #4262 : Databook 1998: Land Width documentation error on page 10-2
Xilinx Answer #4263 : F1.4, F1.5 Schematic: Hierarchy Descent in Annotation is disabled
Xilinx Answer #4264 : Databook 1998: Pin location for 4000E/X disagrees w/ pinouts
Xilinx Answer #4266 : A1.4 Par - Use of -m (use multiple nodes) requires that "ping" command be available in path.
Xilinx Answer #4267 : F1.5 Project Archive: Archive may take a few minutes to begin on Windows NT
Xilinx Answer #4270 : 2.1i, V1.5 COREGEN, JAVA: "NoclassDefFoundError: xilinx/widget/frame/PaneListener"
Xilinx Answer #4272 : SYNPLIFY 5.x: bus notation differs across XNF, EDIF, and UCF
Xilinx Answer #4275 : M1.5: WARNING:basts:158 - PERIOD TIMESPEC 'xxx' has TIMEGRP 'xxx' which contains only PAD elements. Or mixture of PADs and synchronous elements.
Xilinx Answer #4276 : A1.4/F1.4 PAR - PAR crashed during placement of xc40125xv when using Leveraged Guide.
Xilinx Answer #4277 : F1.5/M1.5 XABEL: ABEL compiler does not run when installed on a network drive
Xilinx Answer #4278 : M1.4 PAR - FPGA Express 2.1.1 designs with incomplete RLOC specifications fail in PAR.
Xilinx Answer #4281 : Foundation F1.5: Changing Synthesis Options gives ambiguous "force updated" message
Xilinx Answer #4283 : F1.4 Simulator: Simulating FPGA Express Netlist returns Warning 9218: unknown pin name
Xilinx Answer #4285 : Design Manager M1: What are the recommended set of files to be archived in order to restore an M1 design?
Xilinx Answer #4288 : CPLD: XC9500/XL Programming: Write Security can be overriden in JTAG Programmer but not Hw-130 or third party programmer.
Xilinx Answer #4289 : V1.5 COREGEN: How to get a copy of the CORE Generator v1.5 CD-ROM
Xilinx Answer #4290 : V1.5.0 COREGEN: Known Problems / Issues (README file / release document).
Xilinx Answer #4291 : FPGA Express 2.x: fatal error may occur when modifying existing project in newer version of Express
Xilinx Answer #4292 : Foundation F2.1i, F1.5i: Adding Schematics to HDL Flow Projects
Xilinx Answer #4293 : Galileo , M1.4 : Error :x4kma : 239 - EQN symbol "mtt_modgen_2_modgen_67_ix84"(output signal = mtt_modgen_2_nx358) - The attribute RLOC has been placed on wrong type of symbol.
Xilinx Answer #4294 : A1.4/F1.4 PAR - PAR crashes during placement on HP work stations only.
Xilinx Answer #4296 : Configuration: FPGA controlling their own reconfiguration
Xilinx Answer #4298 : M1.5 Install: ComponentMoveData Error - 103/113/115 (PC ONLY)
Xilinx Answer #4299 : A1.5/F1.5 XC3000 Map - FATAL_ERROR:x3kma:x3kmabel.c:752:1.15 - Didn't find out signal on bel 10 of comp A0_1
Xilinx Answer #4300 : F1.4,F1.5 Simulator: Possible System Oscillations; please wait or press stop button.
Xilinx Answer #4301 : INTERNAL_ERROR:baste:bastetspec.c:2325:1.69.14.3 - TE_TS_SIG object associated with NET EVNT_EVEN1 has no associated NC_SIGNAL.
Xilinx Answer #4304 : FPGA Express v2.0.3: Express reports that "Export of Chip Failed" or similar message when trying to export XNF netlist
Xilinx Answer #4306 : V1.5, V1.4 COREGEN INSTALL, WINDOWS NT: uninstall "setup failed to initialize" error when installing on Windows NT
Xilinx Answer #4307 : valid identifier in an edif file for xilinx
Xilinx Answer #4308 : LogiCORE PCI32 Spartan (v2.0.3): PAR can not meet timing for the Spartan core
Xilinx Answer #4309 : A1.4/F1.4 Bitgen: TIEing design leaves unused IOBs floating.
Xilinx Answer #4310 : A1.4/F1.4 Bitgen - 5200 bitgen with TIE option crashes on PCs only.
Xilinx Answer #4311 : A1.4/F1.4 Lca2ncd - ERROR: xildr - netcheck signal "bla" contains invalid routing at...
Xilinx Answer #4312 : A1.4/F1.4 Lca2ncd - Re-entrant par of lca2ncd'd design leave partially configured route-thrus behind.
Xilinx Answer #4313 : Timing Summary: What do the design statistics mean, maximum/minimum arrival input/output time
Xilinx Answer #4315 : JTAG - EXTEST instruction in XC4000/XC5000/Spartan series devices with INTEST
Xilinx Answer #4316 : V1.5, V1.4 COREGEN, VIEWLOGIC SPEEDWAVE, ACTIVE-VHDL, SUMMIT, VHDL-93 support: COREGEN Sync FIFO FULL and EMPTY outputs stuck high on VHDL-93 simulators
Xilinx Answer #4317 : V1.5, V1.4 COREGEN: directory and project naming restrictions
Xilinx Answer #4318 : 2.1i/1.5 VIEWLOGIC: Viewsim direct gate level schematic simulation of Virtex designs is partially supported
Xilinx Answer #4319 : A1.4/F1.4 Speed files - Incorrect speed models on two wires of the Spartan device family.
Xilinx Answer #4321 : Synopsys, M1.4 ngdbuild : WARNING:basxn:70 - 870 obsolete timing specification(s) was/were found:
Xilinx Answer #4325 : Foundation XABEL F1.4/F1.5/F1.5i: ERROR:basnu:93 - logical block "<>" of type "FDP" is unexpanded.
Xilinx Answer #4327 : JTAG - Can I configure FPGAs and CPLDs in a mixed JTAG chain?
Xilinx Answer #4328 : Exemplar: How to initialize RAM or ROM in VHDL code
Xilinx Answer #4329 : Examplar: How to get a listing of the components and port for a given technology.
Xilinx Answer #4330 : Exemplar: How to force a clock signal to use an IBUF instead of the tools insert of BUFG
Xilinx Answer #4331 : Exemplar: How to force some outputs FAST and some SLOW
Xilinx Answer #4333 : M1.5/2.1i: EPIC/FPGA Editor and TRACE gives different names for Superbels and Components
Xilinx Answer #4334 : CST to UCF Conversion: Is there a utility I can use?
Xilinx Answer #4335 : FPGA Express: Use of predefined attributes with non-static alias range is not supported
Xilinx Answer #4338 : M1.5 LOGIBLOX: What's new in LogiBLOX M1.5?
Xilinx Answer #4341 : M1 NGDBUILD: ERROR:basnb:79 (pin mismatch) and ERROR:basnu:93 (unexpanded) on Synopsys Design Compiler design with instantiated Coregen or Logiblox modules.
Xilinx Answer #4343 : Foundation F1.5, Timing Simulation: Must backstep out of Timing to generate Timing Simulation Data
Xilinx Answer #4344 : Foundation F1.5 Project Manager: Green checkmark for Implementation requires BIT file be present
Xilinx Answer #4345 : FPGA Compiler Verilog: Example of how to infer "set" flip-flop when GSR is asserted
Xilinx Answer #4346 : F1.4 XABEL: Xilinx Property 'Initialstate' passes INIT property, which isn't supported
Xilinx Answer #4347 : Foundation F1.5 Simulation, Coregen: Must create Foundation Schematic Symbol in Coregen to Functionally Simulate
Xilinx Answer #4348 : M1.5: EPIC: How to read the equation inside of a LUT in FPGAs
Xilinx Answer #4349 : Foundation F1.5: Windows NT Service Pack 3 required. (Automation caused exception, exit code 0)
Xilinx Answer #4350 : Foundation F1.5, Project Manager: Automation Caused an Exception; Exit Code 0.
Xilinx Answer #4352 : M1.5: Timing Analyzer: Delete xil_# files in temp directory
Xilinx Answer #4353 : Foundation F1.5, ABEL: Use" Schematic" Project Flow for top-level ABEL designs
Xilinx Answer #4354 : Foundation F1.5, ABEL: Can't synthesize or add ABEL file to HDL project
Xilinx Answer #4355 : Foundation F1.5: "Cannot copy Xilinx project with different name" when copying Foundation project
Xilinx Answer #4359 : F1.4 Project Manager: Netlist creation failed. Try exporting netlist to edif in schematic editor.
Xilinx Answer #4360 : F1.4 Project Manager: On starting Foundation, the mesage "cannot find c:\fndtn\bin\nt\command.com" appears.
Xilinx Answer #4363 : Foundation F1.5: Upgrading/migrating a pre-F1.5 project to F1.5
Xilinx Answer #4365 : Foundation F1.5, HDL Editor: Can't synthesize top-level VHDL or Verilog file from HDL Editor
Xilinx Answer #4366 : Foundation Express F1.5: Migrating Express projects from 1.4 to 1.5
Xilinx Answer #4367 : M1.5i/2.1i: TRACE: Information about Circuit loops reported TRCE/Timing Analyzer
Xilinx Answer #4368 : F1.5: Project Manager appears to hang when invoking Implementation
Xilinx Answer #4372 : Foundation F1.5: How to run Multi-Pass P&R and how to use Guide files with F1.5
Xilinx Answer #4373 : A1.4/F1.4 - An environment variable has been added to 3k mapper to make map ignore invalid CLBMAPs rather than fatal error.
Xilinx Answer #4374 : A1.4/F1.4 Map - Map terminates abnormally on an XC4000XL design.
Xilinx Answer #4375 : M1.x: EPIC: How to add a probe to PROHIBITED iob
Xilinx Answer #4376 : FPGA Express: How to assign standard logic vectors as Hex or Octal values
Xilinx Answer #4377 : FPGA Express VHDL: Which libraries are needed for std_logic_vector addition/subtraction?
Xilinx Answer #4378 : M1.5: Constraints Editor: Entering Fast/Slow after sorting any PORT tab column gives Dr. Watson error
Xilinx Answer #4379 : F1.4, XABEL: Warning L0/C0 : only <x> out of <y> vectors passed Which files contains test vector results?
Xilinx Answer #4382 : M1.5: Constraints Editor: Pressing F1 gives message that help file is out of date.
Xilinx Answer #4385 : FPGA Express: How to instantiate Xilinx Library elements (primitives or macros) in your HDL
Xilinx Answer #4388 : F1.4 Schematic Capture: Valid characters for signal and instance names
Xilinx Answer #4390 : M1 Jtag Programmer: Same source files produce different checksum
Xilinx Answer #4391 : F1.5: Virtex Configuration Stage - Project Manager reports Implementation Errors
Xilinx Answer #4392 : Foundation Express: Attribute passing is available beginning with version 3.0
Xilinx Answer #4393 : Mentor Graphics: PLD_DA: How to enter a TIG constraint
Xilinx Answer #4394 : Foundation F1.5: Selecting the default FSM encoding scheme for Express HDL designs
Xilinx Answer #4395 : Express does not preserve instantiated FMAP / HMAP / LUT primitives
Xilinx Answer #4396 : F1.4/1.5: Modifying libraries when moving from Metamor (XVHDL) to Express
Xilinx Answer #4398 : Foundation F1.5 Simulator, Virtex: Virtex simulation with Foundation Simulator not fully operational.
Xilinx Answer #4399 : Foundation F1.5: Default Simulation Template set to "Generic EDIF"
Xilinx Answer #4401 : Foundation F1.5: Standalone Design Manager doesn't show current project status
Xilinx Answer #4402 : Foundation F1.5, State Editor: After migrating design from F1.4 to F1.5, incorrect VHDL libraries used
Xilinx Answer #4403 : Synopsys 1998.02: compile_fix_multiple_port_nets variable is obsoleted.
Xilinx Answer #4406 : 2.1i, M1.5, M1.4 MAP, LOGIBLOX: Map:ERROR:x4kma:179 - <symbolname> symbol "instance" cannot be packed into an IOB
Xilinx Answer #4407 : FPGA Express: leaving pins open on VHDL component instantiations (VSS-538, VSS-544)
Xilinx Answer #4408 : A1.4/F1.4 MAP - 3K mapper incorrectly reports unconnected inputs to IFDs and then trims the component.
Xilinx Answer #4409 : SYNPLIFY: How to disable RAM inference using the syn_ramstyle attribute?
Xilinx Answer #4410 : A1.4/F1.4 Map - ERROR:baste:312 - Multiple signals named "GND" detected.
Xilinx Answer #4413 : ModelSim: ERROR (line number): Subprogram is ambiguous use -explicit option to disable
Xilinx Answer #4415 : PPR WARNING 7028: How to set Flagblk CLB_Disable_SR_Q on Flops in Xdelay
Xilinx Answer #4416 : A1.5/F1.5 MAP - Design Summary report includes Avg insigs,outsigs, and lambda. What are they?
Xilinx Answer #4417 : XXACTD: fatal error 1062 :license checkout for feature ppr-hppa failed, expired
Xilinx Answer #4419 : M1.4: Map FATAL_ERROR:baste:bastetspec.c:2402:1.69.14.3 - NET OFFSET 'IN1 IN : 20000.00 pS : BEFORE : CLK' has no data IOBCOMP.
Xilinx Answer #4420 : Error "Not Enough Free Disk Space" installing Foundation/Alliance/CPLD Kit Software
Xilinx Answer #4422 : NGD2VER/NGD2VHDL: The SDF file (Standard Delay Format) file contains Minimum, Typical and Maximum of all the same value. Why?
Xilinx Answer #4423 : JTAG - Testing support in Xilinx software & third party JTAG software suppliers
Xilinx Answer #4424 : JTAGPROG 1.4: Opgroup command improper usage (Assertion failed:name, file basjztagsvf.c, line 51 Abort (coredump))
Xilinx Answer #4427 : 2.1i, 1.5, 1.4 COREGEN: How the PDA FIR Filter module calculates its full precision output width.
Xilinx Answer #4430 : Foundation F1.4 Simulator: Error 9523: Incorrect EDIF file. Cannot find top level netlist data.
Xilinx Answer #4431 : Foundation Simulator: How to copy waveforms as bitmaps to other applications like MS Word
Xilinx Answer #4433 : M1.5 LOGIBLOX: XC4000XLA does not show up as a target device family option in lbgui
Xilinx Answer #4434 : Foundation, Spartan: Why can MD1 be placed in schematic, but causes error in implementation?
Xilinx Answer #4435 : F1.4, Express, security: Error$: Feature license file format or misspelling...(-90,313)
Xilinx Answer #4436 : Databook (1/98), 3k, config, pg 4-321: Need pullup on 3k Init?
Xilinx Answer #4437 : M1.4 XC3000 Map - When using pack IOB flops option, the CE net is removed.
Xilinx Answer #4440 : F1.5, JTAG Programmer: JTAG Programmer for FPGAs must be invoked stand-alone
Xilinx Answer #4442 : M1.4 NGDBUILD: ERROR:bascc:64 - decoder symbol 'i_8': Missing "CONFIG" property on LogiBLOX and COREGEN modules.
Xilinx Answer #4443 : Foundation Express F1.5: Instantiation of output cell with non-LVTTL voltage standard crashes Express
Xilinx Answer #4445 : M1.5, M1.4 COREGEN, ORCAD: bus delimiter setting in COREGEN XNF for Orcad designs
Xilinx Answer #4449 : 9500: GENRAD ATE, Using DSM (Deep Serial Memory) to reduce DTS file size
Xilinx Answer #4453 : XC4000E: What is the maximum continuous sourcing current?
Xilinx Answer #4456 : Foundation Schematic Editor Help v1.4: Importing Netlist help refers to invalid menu pick
Xilinx Answer #4457 : LogiCORE PCI32 4000/Spartan: Timing not met due to PAR effort level set to 2 (default)
Xilinx Answer #4459 : A1.4/F1.4 Map - FATAL_ERROR:x4kma:x4kmagrclapse.c:1001:1.90.12.8 - No route-thru available ...
Xilinx Answer #4461 : 2.1i: Constraint Editor: Can't find Clock Enable net when All Nets is selected.
Xilinx Answer #4462 : Cable - Software package VS download cable (jtag, xchecker)
Xilinx Answer #4463 : M1.5: Map gives "invalid target architecture"
Xilinx Answer #4466 : A1.4/F1.4 Map - FATAL_ERROR :baste:bastephook.c:159:1.8 - cannot copy pinhook to itself Process will terminate. Please call Xilinx support.
Xilinx Answer #4467 : Foundation F1.5: When opening F1.4-type HDL projects in F1.5, device and Simprims libraries not shown
Xilinx Answer #4468 : F1.5, XVHDL: Using Metamor (XVHDL) with Foundation F1.5
Xilinx Answer #4469 : A1.4/F1.4 CPLD - The XC9500 timing table has been updated due to improved speed of the XC9500
Xilinx Answer #4472 : Workview Office, Viewdraw: How to change color settings in Viewdraw
Xilinx Answer #4473 : Foundation F1.4 Simulator, Coregen1.4: Simulator gives Page Fault with large bus Sine/Cosine core.
Xilinx Answer #4475 : CPLD: XC9500: What is the erase time required by all 9500 devices
Xilinx Answer #4477 : A1.5: TRCE/ PAR - Timing related applications (par, trce) may run out of memory.
Xilinx Answer #4478 : A1.5/F1.5 PAR - Core dump involving PAR using Leveraged Guide.
Xilinx Answer #4479 : A1.5 Timing Analyzer: OFFSET contraints on TIMEGRPs cannot be disabled using the Disable Timing Constraints Dialog.
Xilinx Answer #4480 : F1.5 Schematic Capture: How to create a macro from a netlist
Xilinx Answer #4483 : Foundation Express: How to instantiate OSC4 in HDL (XC4000E/EX/XL, Spartan/XL)
Xilinx Answer #4488 : Exemplar: How to Preset or initialize a flop to a '1', on powerup only, FPGA's
Xilinx Answer #4489 : A1.5/XSI: Updated XC4000XLA-09 XSI synthesis and simulation files are available on the Xilinx FTP site 12/8/98
Xilinx Answer #4490 : A1.5 XSI Application Note: Synopsys/Xilinx High Density Design Methodology Using FPGA Compiler
Xilinx Answer #4491 : A1.5 XSI: Makeucf is a PERL utility that simplifies the creation of timespecs for FPGA Compiler users
Xilinx Answer #4492 : FPGA Express: Cannot have complex expression in always block sensitivity list (VE-92)
Xilinx Answer #4493 : A1.5/F1.5 X3KA Map - ERROR:baspw:96 - The physical constraint resolution process is unable to resolve all placement constraints
Xilinx Answer #4496 : Orcad Capture v6.11 components with inverted pins do not show inversion in XNF netlist
Xilinx Answer #4500 : Mentor Quicksim M1.5: Which Simulation Program Template to use.
Xilinx Answer #4501 : Foundation F1.5: HDL macro compilation uses 4000e part when checking syntax
Xilinx Answer #4502 : Foundation F1.5: Where can I find a list of Foundation file types' extensions?
Xilinx Answer #4503 : 98 DATA BOOK: BG352: Vcc and Gnd pin locations appear invalid based on the package drawing
Xilinx Answer #4504 : COREGEN, DSP, WEBLINX: DSP brochure on WebLINX indicates that Xilinx supports Sine/Cosine/Arctan LUTs of any width and table depth.
Xilinx Answer #4505 : M1.5/2.1i: Constraints Editor: PORTS window doesn't scroll properly (vertically)
Xilinx Answer #4506 : M1.5i/2.1i: Timing Report: Minimum Delay Reporting "-s min" for Timing Analyzer, TRCE, and NGDANNO
Xilinx Answer #4508 : SYNPLIFY: How to selectively disable IBUF/OBUF insertion using .ispad or black_box_pad_pin?
Xilinx Answer #4512 : Exemplar:Tips on how to use blackbox EDIF and XNF netlists in HDL. (Coregen)
Xilinx Answer #4514 : F1.5 Answers Book: Answers Book must be installed to be used (cannot run from CD)
Xilinx Answer #4516 : Installing A1.5 using SUNOS is not supported.
Xilinx Answer #4517 : ngdbuild : basnu:93, unexpanded logical block.
Xilinx Answer #4520 : HPUX 10.20, M1.5 executables : /usr/lib/aCC/dld.sl: Can't open shared library
Xilinx Answer #4521 : V1.5 COREGEN, FOUNDATION, XC4000, SPARTAN: "Warning 9199: Unknown component - B998, TBUF" when loading Foundation design containing COREGEN SINE-COSINE LUT, FIFOs, ROMs, or RAMs into the F1.5 Foundation simulator
Xilinx Answer #4522 : M1.5: Constraints Editor: User created TPTHRUs are not selectable in advanced tab
Xilinx Answer #4523 : M1.5, HPUX 10.20: /lib/dld.sl: Unresolved symbol: [Vtable]key:__dt__21__versioned_type_infoFv (data) from $XILINX/bin/hp/libbasut.sl
Xilinx Answer #4524 : M1.5, Docs: Error in Install/Release Docs regarding install of CAE Libs on PC
Xilinx Answer #4525 : Foundation 1.5 Install: Space required by installer may be inaccurate
Xilinx Answer #4528 : A1.4/F1.4 Speed Files - Preliminary -08 speed grade data available for xc4000xl
Xilinx Answer #4532 : 5200 power dissipation: What is the K factor for 5200?
Xilinx Answer #4534 : Foundation F1.5: Base or Base-Express install for XC3100L requires XC3000L; automation exception 800706BA, 80010104
Xilinx Answer #4536 : A1.5/F1.5 Map - SET set_name rloc_origin = R3C4 constraint is not applied correctly by map.
Xilinx Answer #4540 : Foundation F1.4 Symbol Editor: Symbol Editor caused general protection fault (GPF) in module SCLM_BIN.DLL
Xilinx Answer #4542 : A1.5/F1.5 Map - Map may crash when RLOCs specificy rows and columns greater than the maximum nuber available.
Xilinx Answer #4543 : V1.5, V1.4 COREGEN: Only the 24 LSBs of a cascade mode SDA FIR output are defined in a Verilog behavioral simulation
Xilinx Answer #4544 : A1.5 CPLD - CPLD update is available with faster speed grades and other changes.
Xilinx Answer #4545 : Foundation F1.5: Important information about source and revision control in HDL projects
Xilinx Answer #4546 : MAP: Error x4kma:195 Problems were found processing RPMs in the design.
Xilinx Answer #4549 : Is 4085xl BG560 footprint(pin) compatible with 40125xv ? (4000xl, 4000xv)
Xilinx Answer #4554 : Page 1-3 of the Alliance Series 1.5 Install and release document is misleading in Table 1-3, CAE Interface CD ROM Contents
Xilinx Answer #4556 : M1.5 Constraints Editor Software Update Available on web site
Xilinx Answer #4557 : Foundation F1.5: Simulation of HDL tutorials (Stopwatch) requires manually toggling Global Reset
Xilinx Answer #4560 : 3000, 4000E/X, 5200, 9500/X: Measuring die temperature
Xilinx Answer #4561 : M1.5 Map - M1.5 optimization performance decreases compared to M1.4 (CLB count increases in 1.5).
Xilinx Answer #4562 : M1.5: Floorplanner: Selecting File -> Print Preview causes Floorplanner to core dump.
Xilinx Answer #4563 : 2.1i/1.5i Design Manager: Wind/U Warning (240): Unknown locale specified locale:C LANGUAGE: UNDEFINED SUBLANGUAGE:
Xilinx Answer #4564 : LogiCORE PCI Virtex: What is the LPCILOGIC and RPCILOGIC?
Xilinx Answer #4567 : M1.5: Constraint editor: UCF files that contain 'EXCEPT' causes Dr. Watson error or program crash
Xilinx Answer #4570 : A1.4/XSI: XC40125XV XSI synthesis and designware files are available on the Xilinx FTP site
Xilinx Answer #4572 : XABEL: abl2edif.exe failed <abel_file_name>.EDN was not created. Error report not available
Xilinx Answer #4576 : ngd2edif: ERROR: Baspm:19 - Unable to open Xilinx Data file ..."viewlog"
Xilinx Answer #4577 : A1.5/F1.5 PAR : bus error (core dumped) after starting constructive placer
Xilinx Answer #4578 : F1.5 Install: Uninstall of Docs uninstalls entire Foundation environment
Xilinx Answer #4579 : F1.5, XABEL: Problem with functional simulation of ABEL designs following CPLD Quick Install.
Xilinx Answer #4581 : M1.5 ngd2edif with ngm abnormally terminated after: WARNING:baspp:39 - Hierarchical block "i0_ix196/i3" has been flattened.
Xilinx Answer #4583 : F1.5, Install: How to add support for additional devices or families.
Xilinx Answer #4585 : Recommended replacement parts for discontinued XC4000A parts
Xilinx Answer #4587 : Foundation F1.5: Upgrading your Foundation Express license to 2.1.x
Xilinx Answer #4588 : FPGA Express 2.x: Express ignores SRL instantiations for Virtex designs.
Xilinx Answer #4591 : M1.5: NET PERIOD constraints are incorrectly interpreted by the Constraint Editor
Xilinx Answer #4592 : FPGA Express: Using don't cares in VHDL
Xilinx Answer #4595 : Synopsys Design Compiler: How to specify the INIT attribute on instantiated ROM/RAM primitives
Xilinx Answer #4596 : Design Manager M1.5i: Setting up your Web Browser Preferences so that multiple browsers are not invoked (Workstation ONLY)
Xilinx Answer #4597 : M1.5: Constraint Editor: Valid TIMESPEC name beginning with "TS" is required.
Xilinx Answer #4599 : F1.5: State Editor generates incorrect one-hot encoded VHDL with a trap state exit logic
Xilinx Answer #4601 : CONCEPT2XIL v4.0; VAN, SIR2EDF 9504: *E,3120: SIR file is wrong version or machine type: sch_lib.sch:hdl.
Xilinx Answer #4602 : LOGIBLOX: How a divide-by-8 LogiBLOX CLOCK DIVIDER is implemented
Xilinx Answer #4606 : 1.5i 4K MAP: ERROR:x4kma:387 - Unable to obey design constraints
Xilinx Answer #4607 : M1.5 Floorplanner: Cannot floorplan BUFGLS and BUFGE for XL and EX devices
Xilinx Answer #4610 : COREGEN: How to calculate the clock/pipeline latency of the COREGEN PDA FIR filter
Xilinx Answer #4611 : VCS: time_sim.sdf:2901, SDF Error: Cannot find timing check (accSetup) in type X_FF,
Xilinx Answer #4614 : M1.5 LCA2NCD: Error: baslc 30:can't load LCA: bad design record (part_number)
Xilinx Answer #4615 : M1.5: Floorplanner: n2f command line looks for wrong FNF file
Xilinx Answer #4616 : A1.5 xc3090l-tq176 - ERROR:baste:262 - Bad format for LOC constraint P128 on OPAD symbol ...
Xilinx Answer #4618 : M1.5i Timing - Nets with TIGs are incorrectly being included in some timespecs.
Xilinx Answer #4619 : FPGA Configuration: INIT goes low on a certain frame, possible causes.
Xilinx Answer #4622 : Foundation: Is there a workstation version of Foundation available?
Xilinx Answer #4623 : MAP1.5 FATAL_ERROR:x4ema:x4emamerge.c:2994:1.43 - Pin 15 already occupied .....
Xilinx Answer #4624 : M1.5i/2.1i: Timing Analyser cannot be used to analyse a path through the asych PRE/CLR of an XC9500 FDCP
Xilinx Answer #4626 : A1.5 Par - Design hangs in PAR after optimization.
Xilinx Answer #4627 : Program latency (Tpl) Time between Program going high and INIT going high
Xilinx Answer #4629 : FPGA Express 2.1.3: Error: Clock variable is being used as data (HDL-175).
Xilinx Answer #4631 : 2.1i, V1.5, V1.4 COREGEN, FOUNDATION: How to invoke NET2SYM in command line mode
Xilinx Answer #4635 : SYNPLIFY: Why is an IBUF inferred between the BUFGDLL/IBUFG and clock-pad?
Xilinx Answer #4640 : F1.5/F1.5i XABEL: the executable ahdl2blf exited with error code 2
Xilinx Answer #4641 : SYNPLIFY: How to instantiate the JTAG pins (TDI, TDO, TCK, TMS) in HDL as general I/O?
Xilinx Answer #4642 : M1.5,bufg,vhdl: Logic trimmed when all buffers instantiated rather than placed by Express.
Xilinx Answer #4643 : Foundation F1.5: CPLD update available on FTP site
Xilinx Answer #4644 : FPGA Express: CONV_STD_LOGIC_VECTOR converts integers to signed values only (HDL-71)
Xilinx Answer #4646 : How to change XC4000XLA, XC4000XV, SpartanXL, and VIRTEX output drive current
Xilinx Answer #4647 : LogiCORE PCI32 4000: VHDL synthesis/simulation with PCI LogiCORE v2.0, Exemplar Leonardo v4.2.2 & M1.4.12
Xilinx Answer #4649 : POWERVIEW 6.1 : Primitive symbols (AND2, OR2, etc) appear as empty box in schematics
Xilinx Answer #4650 : V1.5, V1.4 COREGEN: Cannot start up COREGEN from Desktop and Start Menu shortcut on some PC's
Xilinx Answer #4653 : Foundation F1.5: Cannot show 'Create Version' dialog -- automation caused exception, exit code 80010105
Xilinx Answer #4657 : M1.5 MAP : PAR fails to meet timing in M1.5 when it had in M1.4.
Xilinx Answer #4658 : A1.5/F1.5 5200 PAR - Problems with placement of TBUFs when the F5_MUX is used.
Xilinx Answer #4660 : M1.5/2.1i: Constraints Editor: baste:262-bad format for LOC constraint
Xilinx Answer #4661 : M1.5 Release Document Error: CAE libraries CD cannot be installed on the PC
Xilinx Answer #4663 : F1.5 Schematic Editor: Is it possible to cut and paste schematics into other applications?
Xilinx Answer #4666 : XSI_LIBS A1.5: Updated Virtex libraries availible for Synopsys FPGA/Design Compiler availible on FTP site
Xilinx Answer #4669 : A1.5/F1.5 PAR - FATAL_ERROR:basnd:basndutils.c:132:1.7 - Internal Error - signal has a loop
Xilinx Answer #4671 : A1.5, XSI, Virtex: Error: Either a NOR, or an AND and an OR gate (two-input) is required for mapping.
Xilinx Answer #4672 : What is the composition of the BGA solder balls? What is their diameter?
Xilinx Answer #4673 : SYNPLIFY: How to change the initialization state of a flip-flop using INIT?
Xilinx Answer #4675 : COREGEN: How to do an impulse response simulation of a SINGLE cascade mode SDA FIR filter
Xilinx Answer #4677 : PAR M1.5: Pad report for XC3100A does not report the use of TCLKIN pin
Xilinx Answer #4678 : map 1.4:ERROR:baste:263 - The LOC constraint "P21" (a IOB location) is not valid..
Xilinx Answer #4679 : A1.5/F1.5 Virtex Map reports that an output is not connected, but does not trim the logic: Warning:xvkdr - blockcheck
Xilinx Answer #4681 : BitGen M1.5: Startup Clock can be specified by options or read from design
Xilinx Answer #4685 : UNISIMS: Adding the INIT attribute to VHDL/Verilog based FD models for RTL simulation?
Xilinx Answer #4686 : How to use the VHDL ROC (Reset On Configuration) Component
Xilinx Answer #4688 : Foundation Express: Warning during synthesis: L0/C0 another process already started. Operation cancelled.
Xilinx Answer #4689 : FPGA Express 2.x, HDL-178: Bus slices are not supported in sensitivity list
Xilinx Answer #4692 : Floorplanner: General Design Flows
Xilinx Answer #4694 : A1.5/F1.5 Map - Map segmentation faults in x1_5.19. Ran okay in x1_4.12p.
Xilinx Answer #4695 : A1.5/F1.5 - Fatal Error in map, xvkma:xvkmapper.c:955:1.77 - Can't Satisfy LOC/RLOC constraint.
Xilinx Answer #4696 : M1.x/2.1i: FLOORPLANNER- STARTUP, READBACK, of BSCAN symbols are not shown
Xilinx Answer #4697 : F1.4, XVHDL: Assigning power mode to output signals in VHDL
Xilinx Answer #4699 : V1.5, V1.4 LOGIBLOX: MAXIMUM SPEED style for Comparators uses TBUFs when comparator only check for equality
Xilinx Answer #4700 : Foundation F1.5: SC caused a GPF in module SC_LIBR.DLL when saving symbol
Xilinx Answer #4706 : MENTOR (Convert Design) after retargetting design, design is empty.
Xilinx Answer #4708 : Foundation F1.5i/2.1i: Cannot initialize Automation - cannot find Synopsys registry
Xilinx Answer #4709 : Virtex JTAG - Dedicated JTAG Pins do not need external pullups.
Xilinx Answer #4710 : LOGIBLOX, 4K: Estimating the number of 4K RAM/ROM primitives used in LogiBLOX memories / When does LogiBLOX use 16x1 and 32x1 RAM/ROM primitives
Xilinx Answer #4711 : M1.5 LOGIBLOX, NGDBUILD, SPARTAN, SPARTANXL: "ERROR:basnu:173 - The WAND symbol "../WANDxx" is not supported in the spartanxl architecture." LogiBLOX infers wired-ANDs for Spartan-XL Comparat or & RAM
Xilinx Answer #4713 : LOGIBLOX: FLOAT_VAL attribute support applies to LogiBLOX PADs only
Xilinx Answer #4714 : FPGA Express: Can I change the HDL text editor to an editor other than the default Synopsys editor?
Xilinx Answer #4715 : Foundation F1.4, F1.5: Constraints in UCF appear to be ignored after copying project in Foundation
Xilinx Answer #4719 : CPLD: 9500/XL : Is there any hysteresis on the inputs to 9500 or 9500XL devices?
Xilinx Answer #4726 : Fatal Error:x4ema clb.c:1172:1.60 illegal pack config made it to pack_flop CLB:1404 CLB1467
Xilinx Answer #4727 : F1.5 Schematic Editor: Net attributes parameter names multiply with each installation
Xilinx Answer #4729 : M1.5 Jtag Programmer: !Port Error message in win95 (during program option)
Xilinx Answer #4730 : Foundation1.5,Coregen,Logiblox,Checkpoint Simulation: How simulate an HDL or mixed design with Coregen or Logiblox?
Xilinx Answer #4731 : HDL Design Changes do not appear to get saved when upgrading from Foundation 6 to Foundation F1.x.
Xilinx Answer #4732 : F1.5,Unistall,Docs: When uninstalling Docs, get 'unable to locate installation log file ...isu...'
Xilinx Answer #4735 : A1.5/F1.5 PAR - MPPR gives reasonable results at first cost table run, but unreasonable results on subsequent cost tables.
Xilinx Answer #4738 : Installing A1.5 on HP-UX: Is pfs_mount still required for A1.5?
Xilinx Answer #4739 : M1.5 Floorplanner: Floorplan window does not show RLOCs
Xilinx Answer #4740 : M1.5: Constraints Editor: Can't enter any number that starts with "." or "0" in the pad to pad field.
Xilinx Answer #4741 : M1.5: Constrainst Editor: Net pulldown window in Timing Ignore Dialog does not show long net names
Xilinx Answer #4742 : M1.5: Constraint Editor: Crashes when element group "<" is selected twice.
Xilinx Answer #4743 : Design Manager M1.5: 'Set Guide file(s)' option is greyed out when a project is initially created
Xilinx Answer #4750 : XC4000xv bitstream information. (number of frames, bits per frame)
Xilinx Answer #4751 : ngdbuild: FATAL_ERROR:basut:basutptrfil.c:66:1.4 - Pointer already registered.
Xilinx Answer #4755 : Foundation F1.5: HDL source files must reside in Foundation project directory
Xilinx Answer #4760 : A1.5/F1.5 XC4000E MAP: BUFG must be LOC'd before map to control whether BUFGP or BUFGS is used.
Xilinx Answer #4765 : PC environment variables, license: Environment variables are not set; eg Cannot find license file -1,73:2
Xilinx Answer #4766 : F1.5 XABEL: Abl2edif creates an incorrect netlist when the underscore character is used at the end of a signal name: give based:24 error in translate
Xilinx Answer #4767 : Foundation F1.5: Automation Caused an Exception; Exit Code 80010104, 800706ba
Xilinx Answer #4769 : F1.x State Editor - How do you specify registered or combinatorial outputs?
Xilinx Answer #4770 : A1.5/F1.5 CPLD - Signature/User Code always generates "sign" when not using default option.
Xilinx Answer #4771 : Changes in software security for F2.1i, F1.5, A1.5 (versus v1.4 and previous)
Xilinx Answer #4773 : FPGA Configuration: SyncToDone must apply to all devices in Daisy-Chain.
Xilinx Answer #4774 : NGDBUILD M1.5: ERROR: based: 6 - On or above line <line> in file <file>...
Xilinx Answer #4775 : Alliance 1.5 & Foundation 1.5 Service Packs are available.
Xilinx Answer #4776 : Foundation F1.5i: Incorrect speed grades listed for XC4000XLA, XC4000XV, SpartanXL and Virtex
Xilinx Answer #4777 : 1.5i Map - Map crashes on floorplanned design.
Xilinx Answer #4778 : A1.5/F1.5 PAR - PAR ignores constraint in pcf file for IOB placement
Xilinx Answer #4784 : Foundation F1.5: Simulation template forced to Foundation EDIF
Xilinx Answer #4785 : F1.5, HDL Editor: Symbol is not created for a synthesized HDL macro
Xilinx Answer #4787 : F1.5 Foundation Express: Error cannot open the <path>/workdirs/WORK/<file>.sim for writing. Directory does not exist vss-77 fe-dm-hdlc-unknown.
Xilinx Answer #4791 : FPGA Express: Clock buffers cannot be assigned on INOUT ports in Express Constraints Editor
Xilinx Answer #4798 : Map 1.5i - Prohibit constraints in .ucf file are being ignored by map and are not written to .pcf file.
Xilinx Answer #4799 : F1.5 / FPGA Express 2.1.2 : illegal connection on instantiated BUFG gives NGDBUILD error 142
Xilinx Answer #4803 : Foundation 1.5, FPGA Express 2.1.x: Express Constraints GUI is missing Xilinx Options tab
Xilinx Answer #4805 : FPGA Express 2.x, 3.x - Cannot Export netlist from Synopsys - For unknown reasons the operation could not be completed.
Xilinx Answer #4809 : A1.5, A1.5i, Synopsys: New Designware libraries availible on the FTP site to fix carry-in problem with add_sub component
Xilinx Answer #4810 : BITGEN M1.5: SpartanXL Power Down Pin Configured Improperly.
Xilinx Answer #4811 : ngdbuild: ERROR:basnu:93 logical block of type RAM16X1D is unexpanded ( unexpanded primitives)
Xilinx Answer #4812 : FPGA Express: Entity depends on std_logic_1164 which has been analyzed more recently. LBR-28
Xilinx Answer #4814 : F1.5: SC caused a general protection fault in module conv_acs.all when importing Synplicity EDIF files
Xilinx Answer #4816 : Foundation F1.5 Simulator: Page setup print options not being saved/used
Xilinx Answer #4818 : F1.5/F1.5i, Calc3ka: F1.5 calc3ka sample project has incorrect design flow type
Xilinx Answer #4819 : Foundation Schematic Editor: Hotkeys for zooming in and out in Schematic Editor
Xilinx Answer #4821 : V1.5, V1.4 COREGEN: COREGen does not support dual-port ram with unregistered outputs
Xilinx Answer #4822 : A1.5/F1.5 PAR - PAR_NOGENRAMBLOCK environment variable
Xilinx Answer #4823 : 2.1i: Timing: How is the Setup/Hold Times calculated for the Datasheet IO Report?
Xilinx Answer #4824 : Foundation F1.5: Automation Caused an Exception; Exit Code 80010105
Xilinx Answer #4826 : M1.5: TAENGINE caused invalid page fault
Xilinx Answer #4827 : A1.5/F1.5 Map - WARNING:x4kma - Signal ` ' on pin 4 9
Xilinx Answer #4831 : COREGEN: Output of Delay Element module does not change in simulation if CE is unconnected
Xilinx Answer #4832 : 1.5i PAR - PAR generates DUP LOCATE HIT warning
Xilinx Answer #4833 : NGDBuild - ERROR:basla:106 - failed to launch program e, ERROR:basnb:48 - top leven input design file cannot be created
Xilinx Answer #4834 : Hardware Debugger A/F1.5: Horizontal Scroll bar in Display Signal Dialog is permanently disabled
Xilinx Answer #4835 : LogiCORE PCI: Does the PCI Interface support multi-function (multifunction) capability?
Xilinx Answer #4836 : LogiCORE PCI: does the core come with a behavioral simulation model?
Xilinx Answer #4837 : Floorplanner FAQ: Which users will best benefit from using the Floorplanner
Xilinx Answer #4838 : M1.5: Floorplanner FAQ: Differences between M1 and XACT
Xilinx Answer #4839 : 2.1i: Timing: OFFSET in/after and out/before give negative values in timing report
Xilinx Answer #4842 : VERILOG-XL: Warning! no matching timing check SETUP in Veritool for instance ... - skipping annotation
Xilinx Answer #4843 : 1.5i Map - FATAL_ERROR:x4kma:x4kmamerge.c:2867:1.158
Xilinx Answer #4845 : M1.5/M1.5i Map FATAL_ERROR:x4kma:x4kmacarry.c:3129:1.142 - never found an empty G pin
Xilinx Answer #4847 : A1.5/F1.5 Map - Fatal Error:xvkma:xvkmaslice.c:2620 for Virtex after Service Pack 1.
Xilinx Answer #4852 : A1.5/M1.5 MAP - FATAL_ERROR:baste:bastehint.c:318:1.10 - boundname(...) contains NAME_DELIM() Process will terminate.
Xilinx Answer #4853 : A1.5 Service Pack CD Install for Workstation. The CD is dated September 98.
Xilinx Answer #4855 : LogiCORE PCI: How does the PCI CORE handle wait states between data phases?
Xilinx Answer #4856 : LogiCORE PCI: Target core behavior when the 1st data phase needs more than 16 clocks?
Xilinx Answer #4857 : ***OBSOLETE SOLUTION*** LogiCORE PCI32 4000/Spartan (v2.0): Can the CLKE signal on the PCI CORE be used to drive user logic?
Xilinx Answer #4859 : F1.5, Active-VHDL3.2, synopsys: How to add packages to the Active-VHDL precompiled libraries.
Xilinx Answer #4861 : 1.5i Ngdanno - Timing simulation for ROMs is overly conservative
Xilinx Answer #4862 : A1.5/F1.5 Map - RLOCs on BUFEs do not work correctly
Xilinx Answer #4863 : A1.5/F1.5 MAP - Map ignores macros which use RLOCs on BUFEs
Xilinx Answer #4865 : 2.1i JTAG Programmer - VERIFY operation fails "too many mismatches..." errors (Spartan, Virtex...)
Xilinx Answer #4867 : FPGA Express: all combinatorial logic is mapped by Express
Xilinx Answer #4869 : NGD2VER/NGD2VHDL 1.5: The connection from RAM to LUT are optimized away.
Xilinx Answer #4871 : F1.5, State Editor: Synthesis -> Options to set encoding scheme has no effect
Xilinx Answer #4872 : VERILOG-XL: SDFA Error: Failed to find HOLD timingcheck.
Xilinx Answer #4873 : NC-VERILOG: How to compile the 1.5 Verilog Simprims, LogiBLOX, Unisims, and Coregen libraries?
Xilinx Answer #4874 : M1.5 LOGIBLOX: Generates empty Verilog .v simulation models for IN, OUT, and INVERT modules.
Xilinx Answer #4876 : Foundation 1.5 HDL Editor: Language Assistant for Verilog tri-state buffer is wrong.
Xilinx Answer #4879 : M1.5 Constraints Editor crashes when loading if clock signals are connected to bi-directional pads.
Xilinx Answer #4880 : Foundation Express F1.5: When are constraints applied from the Express Constraints Editor?
Xilinx Answer #4881 : Accessing Xilinx FTP site using MS Internet Explorer
Xilinx Answer #4884 : Design Manager M1.5: [windu_registryd] Failed to open logfile windu_reg.log
Xilinx Answer #4886 : A1.5/F1.5 MAP - Map will not put two SRL16 instances into a single Virtex CLB
Xilinx Answer #4890 : DESIGN MANAGER: error:basut:221 - switch "-tf" is not allowed.
Xilinx Answer #4891 : NGDBUILD 1.4: "ERROR:basnb:79 - Pin mismatch between block ..." with Synplify 5.x
Xilinx Answer #4892 : Foundation Simulator: Cannot Find Free Formula Stimulator when running command (script) file
Xilinx Answer #4895 : A1.5/F1.5 Map - FATAL_ERROR:x4ema:x4emamerge.c:3810:1.43 - Illegal CLB configuration for c2
Xilinx Answer #4898 : F1.5, Schematic Editor: Issues involving complex buses; removal of Bus Pin Connection function
Xilinx Answer #4899 : A1.5/F1.5 - PAR fails due to Map problem related to Floorplanning.
Xilinx Answer #4900 : A1.5/F1.5 Map - INTERNAL_ERROR:xvkma:xvkmabel.c:566:1.16 seen with Synplify 5.0.7
Xilinx Answer #4901 : A1.5/F1.5 - Synopsys design has multiple loads on net with some loads are not getting driven.
Xilinx Answer #4902 : A1.5/F1.5 MAP - Core Dumps with "PROGRAM ABNORMALLY TERMINATED" message on Virtex design.
Xilinx Answer #4908 : 1.5i Map - "ERROR:baspr:41 - Unable to parse ..." Map writes syntactically incorrect PCF when a USER timegrp is completely trimmed.
Xilinx Answer #4910 : M1.5: Timing Constraint Priority is being ignored for FROM:THRU:TO.
Xilinx Answer #4911 : 1.5 Map - Fatal_error: baspm:c:190:1.21 dll open of lib4krt.dll (this also applies for other DLLs)
Xilinx Answer #4913 : 2.1i COREGEN: Sample COREGEN .COE coefficient files for a FIR filter, Distributed RAM, Distributed ROM, and Block RAM
Xilinx Answer #4914 : A1.5/F1.5 Map - FATAL_ERROR:baste:bastencdf - Error in attempt to create BELs.
Xilinx Answer #4915 : Virtex: The data inputs of a MUXF6 can only come from the output of a MUXF5
Xilinx Answer #4922 : Foundation/Alliance 1.5: during place and route - warning: basrt:188 routing for this placement can not meet all timing constrainsts it may have as many as 1 timing errors.
Xilinx Answer #4923 : Foundation Express F1.5i/2.1i: HDL macros cannot have hierarchy or user VHDL libraries
Xilinx Answer #4925 : Implementation: part <part name> is either invalid or not supported
Xilinx Answer #4927 : A1.5/F1.5 MAP/Hitop - application error: <program.exe> the instruction at 0x780017## referenced at memory 0x########. The memory could not be written (msvcrt.dll). Due to Microsoft Visual Studi o 6.0 combatibility issue.
Xilinx Answer #4930 : FPGA Express 2.1.3 - Cannot allocate CLK to BUFG using Constraints Editor
Xilinx Answer #4931 : Windows NT Service Pack 4 may cause problems for Xilinx Software
Xilinx Answer #4934 : Foundation F1.5i, Virtex: Virtex schematic library update for F1.5i
Xilinx Answer #4935 : Virtex XAPP132: CLKDLL Jitter Spec in App. note 132 is not clear
Xilinx Answer #4942 : kmode_exception_not_handled in file win32k.sys
Xilinx Answer #4943 : Abel macro feedthroughs are being ignored in F1.5
Xilinx Answer #4945 : Synopsys FPGA/Design Compiler: How to use the TRANSLATE_OFF and TRANSLATE_ON pragmas
Xilinx Answer #4949 : FPGA Express: Implementing efficient multipliers in VHDL or Verilog
Xilinx Answer #4952 : M1.5. MAP: Dr Watson error on NT machines
Xilinx Answer #4954 : Map 1.5 - Fatal_error:xvkma:xvkmaslice.c:2620:1.78 - mergefsumxor: destination slice
Xilinx Answer #4959 : A1.5/F1.5 Map caused an invalid page fault in libbasut.dll
Xilinx Answer #4961 : M1.5 LOGIBLOX, FOUNDATION: Foundation Documentation on LogiBLOX implies that one can manipulate the pad_loc value of a LogiBLOX pad through the schematic editor
Xilinx Answer #4963 : FPGA Express 3.x: How to access special IOB components for Virtex/E
Xilinx Answer #4964 : How to use Viewlogic Workview Office 7.5 with Foundation F1.5/F2,1i
Xilinx Answer #4965 : F1.5 LOGIBLOX: "ERROR: The Project Directory does not exist or is not writeable."
Xilinx Answer #4967 : Foundation F1.5: Foundation HDL tabs do not allow local menu options to save Express messages
Xilinx Answer #4969 : F1.5 Express/VHDL: multiple architectures for a single entity is not supported
Xilinx Answer #4970 : M1.5: Map errors on empty time group created by Constraints Editor. (ERROR:baste - Time group)
Xilinx Answer #4972 : FPGA Express: Inferred latches always use LD_1 component instead of other primitives (LDCE, LDC)
Xilinx Answer #4974 : 1.5i 4KE Map - Map may incorrectly trim OUTFFTs that are pemanently active.
Xilinx Answer #4978 : M1.5i/2.1i: What are the resources that needs to be constrained in the user constraint file?
Xilinx Answer #4981 : FPGA Express: How to access Carry-In when building arithmetic functions
Xilinx Answer #4982 : MTI, M1.5: ERROR: time_sim.vhd(612): Type error in bit string literal. Type string is not an array of bit.
Xilinx Answer #4983 : Foundation F1.5: ngdbuild/Virtex: basnu:93 -logical block "<name>" of type "GND" is unexpanded
Xilinx Answer #4986 : PROM File Formatter 1.5/1.5i: SpartanXL and 4000XV PROM file generated incorrectly (Symptom: Done pin did not go high)
Xilinx Answer #4988 : FPGA Configuration: Mode Pin Setup for Express Mode in the XC4000XLA.
Xilinx Answer #4989 : 1.5i Virtex Map - ERROR:xvkma:xvkmamapper.c:1397:1.97
Xilinx Answer #4991 : 1.5i, 2.1i Map - 4KXLA design seg faults in Map after "Removing unused logic..."
Xilinx Answer #4993 : V1.5 COREGEN, VERILOG-XL: "Error! syntax error ... parameter signed =<-" / COREGEN Verilog behavioral models use Verilog-XL reserved word "signed" as a user parameter
Xilinx Answer #4994 : M1.5: Trce: Negative slack reported in OFFSET IN AFTER constraints.
Xilinx Answer #4995 : F1.5,2.1i security: When does FPGA Express check out a floating license?
Xilinx Answer #4996 : Foundation ABEL: Internal Error 0001: assert event at line 376 in file "Z:\Lib\tsokit\TSOCELL\TSO_SIG.C"
Xilinx Answer #5008 : FPGA Express: modules for black boxes (LogiBLOX, CoreGen) must be declared in Verilog designs; clock pins missing
Xilinx Answer #5009 : UNISIMS/SIMPRIMS: How to drive PRLD, GSR, GR, and GTS in a Verilog simulation?
Xilinx Answer #5016 : JTAGProgrammer: How to create a log file via the command line?
Xilinx Answer #5019 : Foundation F1.5 State Editor: Incorrect ABEL code generation when you have two state machines (L109/C15)
Xilinx Answer #5021 : JTAG - Is a bitsream generated for JTAG configuration the same as a bitsream for other configuration modes?
Xilinx Answer #5023 : SYNPLIFY: Why does disabling the "Force GSR usage" option still infer the STARTUP block? Using the xc_isgsr attribute?
Xilinx Answer #5024 : FPGA Configuration: DONE is High, device doesn't operate.
Xilinx Answer #5027 : Virtex: Is Partial Reconfiguration and Partial Readback supported in Virtex devices?
Xilinx Answer #5031 : 2.1i 4KX* MAP - FATAL_ERROR:x4ema:x4emamerge.c:3535:1.43 - Pin 8 already in use. moveflopinpin() for CLB: [3793] Process will terminate.
Xilinx Answer #5033 : Virtex: Libraries Guide for Output Banking Rules and configuration is incorrect
Xilinx Answer #5034 : A1.5iSP2/F1.5iSP2: JTAGProgrammer enhanced programming support for the 4000EX/XL/XLA, and SpartanXL (done not going high)
Xilinx Answer #5035 : M1.5 Spartan mapper can not fit design that fit in M1.4.
Xilinx Answer #5037 : XC4000XLT: Should the Vtt Pins be prohibited when using an XLT part?
Xilinx Answer #5038 : Simulation function of State Editor does not work
Xilinx Answer #5040 : 1.5 Foundation Schematic/Simulator: Simulator does not update when wire being simulated is changed to a different wire.
Xilinx Answer #5043 : FPGA Express: DPM: error: tried to use synchronized value in routine
Xilinx Answer #5045 : F1.5 Symbol Editor, XBLOX: Illegal bus format [0:0]
Xilinx Answer #5047 : F1.5 FOUNDATION Simulator: "Simul :MACRO: illegal macro format - line is too long"
Xilinx Answer #5048 : Synopsys, Virtex: replace_fpga and uniquify should not be used during synthesis using FPGA/Design Compiler (NGDHelpers 406)
Xilinx Answer #5050 : LogiCORE PCI32 4000/Spartan (v2.0.x): NGDBUILD errors out on a LOC constraint on INTA_0 net
Xilinx Answer #5051 : F1.5, M1.5, install: Where to find the CD Key required for installation?
Xilinx Answer #5053 : A1.5/F1.5 Map - Map drops connection internal to CLB corrupting logic
Xilinx Answer #5054 : ngdbuild: ERROR:bascp:94 - Invalid UCF/NCF file entry value "" detected on line 4, offset 64,
Xilinx Answer #5055 : LogiCORE PCI: Guide does not work if M/S_SRC_EN signals are unused
Xilinx Answer #5057 : Foundation F1.5, Timing Simulator: Metastable operation not accurately simulated
Xilinx Answer #5058 : Map: Hard macro pin locking from ucf not supported
Xilinx Answer #5061 : BitGen M1.5: SpartanXL Express Mode enabled with hidden switch.
Xilinx Answer #5063 : M1.5/Synopsys: FPGA designs containing STARUP/STARTBUF component may not configure properly when using FPGA/Design Compiler for design entry
Xilinx Answer #5066 : 1.5 4KX* PAR - INTERNAL_ERROR:x4kpl:x4kplanal.c:1730:1.73.3.2 - MACRO TYPE NOT FOUND.
Xilinx Answer #5070 : M1.5i/Synopsys VSS: Error when compiling UNISIM library: **Error: vhdlan,1073 unisim_VPKG.vhd(509) on function SLV_TO_INT
Xilinx Answer #5073 : FPGA Express produces XNF with lines greater than 2048 characters, ERROR:basxn:53 - Line number 30788: maximum field length exceeded
Xilinx Answer #5075 : M1.5 Map - Map fatal error when IFDX output is fed back to OFDTX loc'd to same pad.
Xilinx Answer #5078 : M1.5: Floorplanner does not recognize LOC attributes on some IOB components
Xilinx Answer #5083 : 2.1i, V1.5 INSTALL, COREGEN: " Your registry HKEY_LOCAL_MACHINE/SOFTWARE/JavaSoft/Java RuntimeEnvironment/1.1/javahome" messages and "JAVA was not found " or "Unsatisfied link" errors)
Xilinx Answer #5085 : M1.5 DC2NCF: TNM attribute created from DC2NCF causes warnings in NGDBUILD
Xilinx Answer #5089 : 1.5i PAR - Some Virtex designs get poor Place and Route results due to premature exit from placer.
Xilinx Answer #5090 : Running Mentor programs pld_* I see version M1.5.19 even though I just installed M1.5i (M1.5.25)
Xilinx Answer #5093 : Foundation F1.5 Project Manager: Implementation Status not properly updated when a project is on a network drive
Xilinx Answer #5094 : LogiCORE PCI: All about Zero and One wait states
Xilinx Answer #5098 : 2.1i PAR - Route results lead to DRC warning: WARNING:basdr:7 - Netcheck: An antenna was found on signal "hp_rdy";
Xilinx Answer #5099 : F1.5, Xilinx Constraints Editor: How to use the Xilinx Constraints Editor with Foundation F1.5
Xilinx Answer #5102 : M1.5: TRCE: Unconstrained path analysis appears in the middle of the timing report for VIRTEX
Xilinx Answer #5103 : M1.5i/2.1i: TRCE: Confusing constraint header when 4X is invoked with CLKDLL.
Xilinx Answer #5104 : M1 PAR: What is an "antenna" in the context of the place and route program, PAR?
Xilinx Answer #5105 : M1.5/2.1i: Floorplanner does not support hard macros (.nmc)
Xilinx Answer #5106 : 2.1i Floorplanner - PROHIBIT constraints are not supported.
Xilinx Answer #5108 : Virtex Configuration: What is the status of user I/O during configuration?
Xilinx Answer #5109 : Cable - Can Xchecker cable or Parallel cable be used for downloading to any device? ( Virtex or spartan )
Xilinx Answer #5110 : Foundation F1.5: Lmacs:58 The compression buffer length is too short, btrieve
Xilinx Answer #5111 : F1.5i/2.1i: Taengine produces Timing report with no data - too many paths to trace
Xilinx Answer #5112 : Foundation Schematic Editor: What do green net labels mean?
Xilinx Answer #5113 : 1.5i Virtex Map - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.112 - Cannot satisfy LOC/RLOC constraint
Xilinx Answer #5114 : FPGA Express 3.3: Abort at 59 occurs when parallel logic is coded
Xilinx Answer #5117 : F1.5i: Simul caused a General Protection Fault in module <unknown> when saving simulation state
Xilinx Answer #5118 : 1.5i PAR - Route of XC4085XL gives inferior results and takes > 2 times as long with 5_25
Xilinx Answer #5120 : 1.5 Map - Error xvkma - specialize_xor() being called for invalid XOR gate -----
Xilinx Answer #5121 : M1.5i/2.1i: Timing: Explaination of a Timing Report File (.TWR)
Xilinx Answer #5124 : F1.5i Simulator, Virtex: Cannot simulate CLKDLL component in a Timing Simulation.
Xilinx Answer #5125 : LogiCORE PCI: Can the I/O space in the PCI core be set to greater than 256 bytes?
Xilinx Answer #5126 : LogiCORE PCI: PCI Bus Configuration Timing Details
Xilinx Answer #5127 : LogiCORE PCI User/Design Guide: Key to various states depicted in waveforms
Xilinx Answer #5128 : LogiCORE PCI: When is the S_WRDN signal valid?
Xilinx Answer #5129 : LogiCORE PCI32: What is the advantage of using the BAR_x_WR/RD signals as refered to in the User Guide?
Xilinx Answer #5133 : Virtex: Are there any power sequencing issues for VCCint Vcco Vref?
Xilinx Answer #5134 : LogiCORE PCI: Harmless warnings during Cadence Verilog-XL simulation
Xilinx Answer #5136 : Concept2xil: Programmer Error: Failed Assertion at line 710
Xilinx Answer #5140 : M1.5i/2.1i: Using the Tri-State IOB Flip-Flop in SpartanXL, XC4000XLA, and XC4000XV
Xilinx Answer #5144 : Metamor to Foundation Express 1.5 (Synopsys) VHDL Conversion Guide
Xilinx Answer #5146 : 1.5i XC4000X* Map/PAR - ERROR:x4kpl:368 - RPM "l***" contains a partial carry logic chain. This is not supported in the current release.
Xilinx Answer #5147 : Virtex JTAG - TAP Advanced Timing Charecteristics
Xilinx Answer #5150 : M1.5i Map - Map drops Flop load from signal with multiple loads in Synopsys design.
Xilinx Answer #5151 : M1.5i Map - FATAL_ERROR:x4ema:x4emamerge.c:3810:1.43 - Illegal CLB configuration for c2
Xilinx Answer #5152 : M1.5i Map - Map fails physical design DRC: ERROR:xvkdr:36 - blockcheck: RAMCONFIG not used.
Xilinx Answer #5153 : A1.5i/F1.5i MAP/HITOP - application error: <program.exe> the instruction at 0x780017## referenced at memory 0x########. The memory could not be written (msvcrt.dll)
Xilinx Answer #5154 : Virtex Configuration: Is it possible to stop CCLK during configuration?
Xilinx Answer #5155 : FPGA Configuration: Configuration Problem Solver on web.
Xilinx Answer #5158 : NGDANNO 1.5: FATAL_ERROR:basut:basutblist.c:348:1.2-Maximum iterator count exceeded
Xilinx Answer #5159 : LogiCORE PCI: Is snooping supported?
Xilinx Answer #5160 : LogiCORE PCI: How many BARs does the PCI interface support?
Xilinx Answer #5163 : Does Xilinx Support LPM's?
Xilinx Answer #5164 : LOGIBLOX: When are TBUFs used for muxing in LogiBLOX RAM?
Xilinx Answer #5165 : COREGEN, 4K: Estimating the number of 4K RAM/ROM primitives used in COREGen memories / When does COREGEN use 16x1 and 32x1 RAM/ROM primitives
Xilinx Answer #5169 : Design Manager M1.4/M1.5/i: MPPR does not create revision directories; revisions don't appear in DM's view
Xilinx Answer #5170 : Map 1.5i caused an invalid page fault, LIBBASUT.DLL
Xilinx Answer #5171 : LogiCORE PCI: 0.7 or 0.75 multiplication factor in the UCF files
Xilinx Answer #5174 : A1.5i (M1.5.25) map: FATAL_ERROR:xvkma:xvkmaslice.c:4041:1.97 - domergeslices got empty slot for frag
Xilinx Answer #5175 : CPLD : XC9500XL: What is bus-hold circuit?
Xilinx Answer #5178 : VERILOG-XL: Timing violation: $recovery(posedge CLKB: 800, posedge CLKA: 800, 1.0: 10)
Xilinx Answer #5179 : Does Virtex support LVPECL voltage standard?
Xilinx Answer #5181 : 1.5i PAR - Placer fails on .pcf placement constraint (ERROR:baspl:292/291)
Xilinx Answer #5182 : M1.5i: EPIC online help on NT and 95: does not work from Help Menu.
Xilinx Answer #5188 : General Setup Initialization Errors - General Protection Fault (GPF) or "illegal operation" dialog
Xilinx Answer #5192 : Exemplar: After optimization Spectrum changes my instantiated BUFGDLL to a BUFGP
Xilinx Answer #5193 : LogiCORE PCI: All about master aborts (abnormal terminations)
Xilinx Answer #5197 : Mentor: Possible solution to RAM not simulating correctly in Quicksim II
Xilinx Answer #5199 : Mentor: Can I bring a non Mentor design into Quicksim II for a Board Level Timing Simulation?
Xilinx Answer #5201 : 1.5i Map - Virtex mapper fails to pack 2 FMAPs and 2 MUXCY_Ls into one slice.
Xilinx Answer #5202 : LogiCORE PCI: How does the LogiCORE interface handle single cycle grants?
Xilinx Answer #5204 : FPGA Express: Can I run more than one version of FPGA Express on my PC?
Xilinx Answer #5208 : MAP: "ERROR:xvkma:120 - LUT* symbol has an equation that has no connected signal" with Synplify 5.0.x
Xilinx Answer #5209 : V1.5, V1.4 COREGEN DATASHEET, 4K RAM: CLB utilization formula is incorrect for odd-valued Single Port 4K RAM sizes (sizes of the form 2N+1)
Xilinx Answer #5213 : M1.5i/2.1i: TRCE reports large differences in clock delay (skew) on BUFGLS in XV devices
Xilinx Answer #5214 : LogiCORE PCI: Does the LogiCORE interface support interrupts?
Xilinx Answer #5216 : Difference in E and EX libraries
Xilinx Answer #5217 : CORES and IP: availability of VXI bus cores
Xilinx Answer #5218 : V1.5 COREGEN, VIRTEX, VERILOG, VHDL, MIF, COE: What files are required for proper initialization of a Virtex Block RAM in an HDL behavioral simulation? / What is the MIF file?
Xilinx Answer #5225 : F1.5/F1.5i Schematic Editor, Virtex: Do not use BUFGIO library component
Xilinx Answer #5227 : LogiCORE PCI: How does the LogiCORE interface handle target abort?
Xilinx Answer #5228 : Foundation Schematic Capture: Are references required to end with a digit?
Xilinx Answer #5229 : LogiCORE PCI: How do the REQ#/GNT#/RST# lines in the LogiCORE interface act?
Xilinx Answer #5237 : Simulator: How to simulate a ramp or counter on a bus
Xilinx Answer #5239 : LogiCORE PCI64 Virtex: Can the PCI64 interface support 32 bit applications?
Xilinx Answer #5246 : LogiCORE PCI: Supported Device/Package/Speed Grades
Xilinx Answer #5247 : LogiCORE PCI: Xilinx Software & Synthesis tools support
Xilinx Answer #5249 : SYNPLIFY: How to preserve a signal through synthesis using the syn_keep attribute?
Xilinx Answer #5251 : VCS: Assertion failed "qop & arg1->pe.real & 0" at line 583 in file eval.c
Xilinx Answer #5252 : M1.5/1.5i: Methods to reduce simulation time in VSS
Xilinx Answer #5253 : LogiCORE PCI: Device Resource Utilization summary
Xilinx Answer #5254 : LogiCORE PCI32 4000/Spartan: Are the XC4000XLT and Spartan devices 3.3V/5V PCI compliant?
Xilinx Answer #5255 : SIMPRIMS: What does it mean when I get setup or hold time violations in my simulation? What do I do?
Xilinx Answer #5257 : Foundation Express F1.5/i: Synopsys Internal error - Abort at 1548 : Server threw an exception (1546, 124)
Xilinx Answer #5261 : LogiCORE PCI: Implementing CompactPCI HotSwap with Xilinx LogiCORE PCI solution
Xilinx Answer #5262 : NGD2VER 1.5i: dangling signals in Virtex Verilog simulation causes unknowns (stuck at "X")
Xilinx Answer #5263 : VCS: Running simulation
Xilinx Answer #5264 : A1.5i, F1.5i, COREGEN: What version of COREGEN is shipped with M1.5i (Performance Pack bundle)?
Xilinx Answer #5269 : Install 1.5i: Installing 1.5i documentation CD on Solaris 2.X/HP-UX 10.xx results in ERRORS
Xilinx Answer #5270 : SIMPRIMS: The INIT parameter is incorrectly defined for the X_LUT* Verilog models for Alliance 1.5
Xilinx Answer #5272 : LogiCORE PCI32 4000XLT: Incorrect 'MIN' clock delay value used to compute the setup time
Xilinx Answer #5275 : LogiCORE PCI32 4000: The timespec "USER_PADS" in the UCF files is incorrect for Viewlogic Flow
Xilinx Answer #5276 : LogiCORE PCI32 4000: The recorder module in compliance testbench does not get bound in the Express Flow
Xilinx Answer #5280 : Exemplar: Spectrum synthesis is giving me warning component ... has no visible entity binding
Xilinx Answer #5281 : F1.5/F1.5i Project Manager: Checking Implementation reports gives "Template Engine" error box.
Xilinx Answer #5285 : 1.5i 4KXL Map: FATAL_ERROR:baste:bastegrp.c:477:1.21 - No output pin for group
Xilinx Answer #5289 : LogiCORE PCI32 Spartan: Timing simulation may issue errors while simulating ping
Xilinx Answer #5290 : LogiCORE PCI32 Spartan: PCI pinout for PQ208 not compatible with 4013XL PQ208
Xilinx Answer #5291 : LogiCORE PCI32 Spartan: Setup constraints for the PQ208 package relaxed
Xilinx Answer #5292 : 1.5i Virtex PAR - Incorrect PCF file in PAR causes application error rather than Par warning
Xilinx Answer #5294 : Virtex IBIS models availability
Xilinx Answer #5299 : LogiCORE PCI: What loads should be used when calculating maximum clock-to-out timing?
Xilinx Answer #5301 : FPGA Express: Error L-1/C0 : #0 Not enough storage is available to complete this operation.
Xilinx Answer #5303 : F1.5i watch tutorial wtut_vhd does not contain .hdr, .dir, .blk, ...; library directory access error
Xilinx Answer #5304 : Virtex: What is an IBUFG and what can I use it for?
Xilinx Answer #5305 : F1.5i install: Is it required to install F1.5 first?
Xilinx Answer #5308 : F1.5/F1.5i/F2.1i Foundation Express: Information about "Abort" errors (1709, 1704, 1564, 67, etc.)
Xilinx Answer #5312 : M1.5i install: _ins5176._mp.exe acception: Access Violation(0xc0000005)
Xilinx Answer #5314 : F1.5i Project Manager:Cannot find license for constraints editor
Xilinx Answer #5319 : Foundation Installer overwrites license file on every install
Xilinx Answer #5323 : F1.4/F1.5/F1.5i HDL editor : Cannot print more than 56 lines a page
Xilinx Answer #5325 : FPGA Express: Information about the Duplicate Register Merge feature
Xilinx Answer #5326 : M1.5i: Virtex Timing - Par and TRCE report different numbers for the same design.
Xilinx Answer #5327 : M1.5:i Virtex EPIC Slice View: For MUX_F5 in EPIC, which signal is selected by '1'
Xilinx Answer #5329 : 1.5i. MAP - Map may crash on designs with modules containing OPTIMIZE attributes.
Xilinx Answer #5330 : 2.1i Security: Setting up a Node-Locked license.
Xilinx Answer #5331 : F1.5,2.1i Security. Debugging a Node-Locked License.
Xilinx Answer #5332 : F1.5,2.1i Security. Setting up a Floating License.
Xilinx Answer #5333 : F1.5,2.1i Security. Debugging a Floating License.
Xilinx Answer #5334 : FPGA Express 3.x: Instantiating LUTs for Virtex/E designs
Xilinx Answer #5344 : 1.5 XC5200 PAR - WARNING:baspl:325 - IOPLACETASK: No I/O comps to place
Xilinx Answer #5346 : Exemplar: How to infer STARTUP, using the infer_gsr command.
Xilinx Answer #5348 : Mentor: How to bring up the the pld_* help menu Mentor PDF docs that are installed.
Xilinx Answer #5352 : M1.5: Constraints Editor: ERROR:bascp:47 - Invalid UCF/NCF file entry value detected while reading UCF.
Xilinx Answer #5353 : M1.5: Constraint Editor: If period constraint comes in from NGD file, not UCF file, it can't be deleted or Edited.
Xilinx Answer #5358 : COREGEN, VHDL: Output still available from VHDL behavioral model for area-optimized multiplier when CE is deactivated
Xilinx Answer #5359 : FPGA Express 3.x: error: can't find type information (.typ file) for filename (HDL-353)
Xilinx Answer #5360 : Libraries Guide 1.5: Input Frequency Range of CLKDLL is incorrect
Xilinx Answer #5363 : 1.5i 4KXL Map - FATAL_ERROR:basnc:basncsignal.c:263:1.67 - Could not find a bel for a signal ...
Xilinx Answer #5364 : 1.5i XC4000X* PAR - Express designs with non-RLOC'd carry chains and Coregen modules may not place.
Xilinx Answer #5365 : M1.5: Floorplanner: RPMs are incorrectly displayed in the Floorplanner
Xilinx Answer #5368 : Virtex Configuration : What valid configuration speeds are available for Virtex master serial configuration?
Xilinx Answer #5371 : 1.5i Virtex PAR - XCV1000 implementation not progressing after 60 hours on 450MHz PC with 384 MB RAM
Xilinx Answer #5374 : 1.5i SP2 Virtex PAR - ABNORMAL PROGRAM TERMINATION when all IOBs in design are locked and the design contains SelectIO IOBs.
Xilinx Answer #5378 : F1.5/F1.5i HDL Editor: Lines >116 characters truncated when printing
Xilinx Answer #5381 : Virtex Configuration: Issues on configuring Virtex and 4000X devices in daisy chain
Xilinx Answer #5382 : Foundation Express: How to access the schematic viewer (Vista)
Xilinx Answer #5387 : NGDBUILD: "logical block ' ' of type 'READBACK' is unexpanded" with a Exemplar netlist
Xilinx Answer #5388 : FPGA Express: Unlinked modules when black box modules are instantiated. (FE-LINK-2)
Xilinx Answer #5390 : FPGA Express: Warning: No global set/reset (GSR) net can be used in the design .. (FE-GSRMAP-8)
Xilinx Answer #5391 : JTAG - What is the JTAG CLAMP instruction?
Xilinx Answer #5392 : F1.5i Project Manager: Cannot create directory. Long Path Name problems.
Xilinx Answer #5393 : F1.5/F1.5i: How do you access the extended message referred by Foundation HDL editor
Xilinx Answer #5394 : 1.5i, 2.1i 4KX* Map - Map errors out on carry logic when trimming is disabled.
Xilinx Answer #5398 : FPGA: Can I drive an IO when there is no power to the device?
Xilinx Answer #5399 : ngdbuild M1.5i: WARNING:basnu:159 - Attribute "LOC" on "tx1a_dup0" is on the wrong type of object.
Xilinx Answer #5402 : V1.5.2 COREGEN, XC4000: 4K 1-D ROM-based Correlator bit masking function irregularities: problems excluding MSBs, use of 0's to mask out bits, apparent incorrect behavioral and backannotated simulation model
Xilinx Answer #5405 : F1.5 Express: INOUT port declaration synthesized as an output only (FE-PMAP-18)
Xilinx Answer #5411 : Setup unable to find installation languages in setup.lid , error 105
Xilinx Answer #5413 : M1.5i Map - FATAL_ERROR:baste:bastencdf: Error in attempt to create BELs
Xilinx Answer #5416 : NGDBUILD (EDIF2NGD): How does EDIF2NGD handle embedded ranged strings in array names?
Xilinx Answer #5419 : 1.5i Virtex Map - ERROR:xvkma:99 - RLOC has bad suffix. Only valid suffixes are S0 and S1.
Xilinx Answer #5420 : Alliance/Foundation 1.5i: Icons in start menu do not bring up the software. Can't find execuatble.
Xilinx Answer #5421 : Are virtex devices compatible with PC100 class SDRAM?
Xilinx Answer #5422 : 15i Virtex DRC - DRC incorrectly flags a CLKDLL that drives both CLK0 and CLK2X offchip.
Xilinx Answer #5424 : 1.5i Virtex Map - FATAL_ERROR:xvkma:xvkmap.c:587:1.112. Cannot find IOB attached to IBUFG
Xilinx Answer #5425 : 1.5i Map - Map aborts with ERROR: PAD not a valid type for FMAP symbol
Xilinx Answer #5429 : M1.5i/2.1i: Prohibiting multi-purpose configuration pins.
Xilinx Answer #5432 : FPGA Express 3.1: NUMERIC_STD package available for Express 3.0 or 3.1
Xilinx Answer #5434 : 1.5i Map - FATAL_ERROR:basut:basutpak.c:560:1.3 - Bogus offset reading packed data.
Xilinx Answer #5437 : VSS with M1.5: "Error: vhdlsim,19: Discrete range is not consistent with corresponding index subtype" in simprim_Vpackage.vhd
Xilinx Answer #5439 : M1.5i: Epic: Cannot edit block/CLB/macro even in read-write mode.
Xilinx Answer #5440 : Mentor/NGDBuild warning:basnu:159-Attribute TNM_NET on "CLK" is on the wrong type of object
Xilinx Answer #5441 : LogiCORE PCI: What addressing mode is supported during memory burst transactions?
Xilinx Answer #5442 : LogiCORE PCI32 Spartan: How do you use our Spartan core as a target-only core?
Xilinx Answer #5443 : F1.5i: Virtex -6 speed grade not available in Project Manager.
Xilinx Answer #5444 : Libraries Guide contains typo error in Global Clock Buffer Location for Virtex
Xilinx Answer #5445 : V1.5 COREGEN, FOUNDATION: Bus Conflict errors during Foundation functional and timing simulation of NCO modules
Xilinx Answer #5447 : F1.5/F1.5i Project Manager: Pcm: Cannot initialize automation: could not get interfaces to Synopsys server
Xilinx Answer #5451 : CPLD XC9500/XL: Where to find decoupling capacitors for 9500/XL chips?
Xilinx Answer #5454 : F1.5/F1.5i Library Manager: When attaching a library to another project, unexpanded block errors occur in Implementation Tools
Xilinx Answer #5456 : 1.5i Map - Correlated back-annotation of Virtex carry chain losing some delays.
Xilinx Answer #5458 : 1.5i Virtex MAP - ERROR:baste:263 - The LOC constraint "M19" (a PCIIOB location) ...
Xilinx Answer #5459 : M1.5: Timing Analyzer: Dr. Watson error when Timing Analyzer closes or Application Error with an invalid page fault, libxvktw.dll
Xilinx Answer #5460 : 1.5i Spartan Map - Fatal Error: x4kema:x4kmamerge.c:3879:1.43- Already signals present on this..
Xilinx Answer #5461 : 1_5.19 MAP: Incorrect warning message when ROC is used in VHDL design
Xilinx Answer #5466 : M1.5i LOGIBLOX: XC9500 Up/Down counters with bit widths greater than or equal to 9 bits do not count correctly.
Xilinx Answer #5467 : Error Baspp - This design contains logic. . .correlated back annotation is not supported
Xilinx Answer #5470 : M1.5i: Floorplanner: Not able to move carry chain counter that have been placed against edge of die
Xilinx Answer #5472 : F1.5/F1.5i Project Manager: Automation failed, exit with error code 80080005
Xilinx Answer #5474 : NC-VERILOG: Running simulation
Xilinx Answer #5477 : F1.5i NGDBUILD: ERROR:basnu:93 - logical block "<instance_name>" of type "OBUFN_S" is unexpanded
Xilinx Answer #5478 : Webfitter: Left Hand Side (contents) of Help window is inactive (Java not enabled)
Xilinx Answer #5479 : Webfitter: JavaScript Error: https://xapps1.xilinx.com/webfitter/cgi-bin/buttons.cgi, line 35:
Xilinx Answer #5481 : M1.5 LOGIBLOX, FOUNDATION: The documentation on "How to Use Memory Elements" in the Foundation Help Contents incorrectly indicates you need to specify the Vendor and Bus Notation for a LogiBLO X module in the Setup window
Xilinx Answer #5482 : LOGIBLOX, 4000XLA/SpartanXL Aligned RPM: Map ERROR:baste:190 or OldMap:233 - Bad format for RLOC attribute
Xilinx Answer #5485 : 1.5i 4KE Map - FATAL_ERROR basutarray.c:207:1.5 - Sort produced an unsorted list
Xilinx Answer #5486 : 2.1i, M1.5i, LOGIBLOX: There is no LogiBLOX support for Virtex
Xilinx Answer #5488 : Design Manager M1.5/i: Map continues to use the "-fp" option even though Set Floorplan Files is set to 'None'
Xilinx Answer #5489 : M1.5i/2.1i: Timing: How the OFFSET IN and OUT calculation is made?
Xilinx Answer #5491 : 1.5i Virtex Map - ERROR:baste:301: The RLOC value of R0C0.S1 on component D creates a macro that is too large for the device
Xilinx Answer #5492 : 1.5i PAR - INTERNAL_ERROR:baspl:basplbscore.c:614:1.21
Xilinx Answer #5494 : M1.5i NGDbuild - ERROR:basnb:79 - File cannot be merged into block
Xilinx Answer #5498 : 1.5i Virtex Map - Virtex Map crashes after successfully writing output files.
Xilinx Answer #5499 : JTAG - Configuring multiple devices in a JTAG chain, do you need to buffer the TMS and TCK?
Xilinx Answer #5500 : Spartan XL - How to estimate power in Spartan XL. What is the K factor ?
Xilinx Answer #5501 : Cable - When powering a cable with 5 volts and using a 3.3 volt xl part, what voltage are the control signals?
Xilinx Answer #5506 : FPGA Express: out of virtual memory error. synopsys internal error 217
Xilinx Answer #5508 : Timing Simulation: How to Generate the Testfixture file, time_sim.tv, for an existing implementation
Xilinx Answer #5510 : M1.5 Trce, WARNING:bastw:169 - The pulse width for this signal is less than the minimum pulse-width
Xilinx Answer #5512 : M1.5i: Timing Analyzer: Timing analyzer crashes when run on older W95 & NT4.0 systems
Xilinx Answer #5513 : 1.5i Virtex PAR - WARNING:basdp:117 - Ignoring constraint < > because site was not found - Virtex Prohibit syntax
Xilinx Answer #5516 : 1.5i SP2 Bitgen -Bitstream for 4000X* and SpartanXL bitstream is incorrect for IFD with clock enable.
Xilinx Answer #5519 : 1.5i Package Files - New Virtex package files are available in addition to those available in 1.5i Service pack 2.
Xilinx Answer #5520 : 1.5i Virtex Back Annotation - Ngdanno issues warning stating that 100% back annotation is not possible
Xilinx Answer #5521 : 1.5i Virtex PAR -Placer hangs on a virtex design.
Xilinx Answer #5522 : 1.5i Promgen - ERROR:basbs:262 - 0x19682 bytes loaded up from 0x0 exceeds maximum0xffff..
Xilinx Answer #5523 : 1.5i 9500XL - Part list contains bad entries for 95288XL.
Xilinx Answer #5525 : 1.5i Virtex Back Annotation - Ngdanno does not back annotate delays on logical CLKDLL
Xilinx Answer #5526 : 1.5i Virtex Back Annotation - CLKDV_DIVIDE and DUTY_CYCLE_CORRECTION only in physical netlist
Xilinx Answer #5528 : M1.5i Virtex Timing - PAR issues warning when trying to create the TIMEGROUP "DLLS"
Xilinx Answer #5529 : M1.5i Timing - New Virtex Speed Files are available in the 1.5i Service Pack 2.
Xilinx Answer #5530 : 1.5i XC400XLA Speed Files - Preliminary Speed Files are avaialble for x4013xla, x4062xla and x4085xla.
Xilinx Answer #5532 : 1.5i PAR - Leveage guided PAR fails with NTERNAL_ERROR:basnd:basndtiming.c:647:1.25.1.2 -...
Xilinx Answer #5533 : 1.5i PAR - MPPR with Virtex gets poor results after first pass.
Xilinx Answer #5534 : 1.5i Map - run time error - pure virtual call
Xilinx Answer #5535 : 1.5i Virtex Timing - Speed numbers for horizontal long lines are being underestimated.
Xilinx Answer #5536 : 1.5i Ngdanno - ERROR:baspp - this design contains logic for which correlated back annotation ...
Xilinx Answer #5537 : 1.5i Bitgen - Bitgen does not switch startup clock options for Virtex.
Xilinx Answer #5538 : DataBook: Bonding of XC9536-CS48 in the datasheet seems to be different than that of XC9536XL-CS48
Xilinx Answer #5539 : M1.5i Virtex Timing - Timing analysis is missing paths to IOBs when PCI used.
Xilinx Answer #5540 : 1.5i Virtex PAR - Placer seg faults when both list and single LOC csts applied to a TBUF set.
Xilinx Answer #5541 : PAR misreports Virtex PCIIOBs as only inputs instead of bidirs.
Xilinx Answer #5542 : 1.5i PAR - PAR never completes router resource preassignment
Xilinx Answer #5543 : 1.5i PAR - Placement error related to use of carry logic in guided PAR.
Xilinx Answer #5544 : 1.5i Back Annotation - Muxf6 is not backannotated correctly due to map problem.
Xilinx Answer #5545 : 1.5i Back Annotation - Ngdanno creates a dangling net in a design.
Xilinx Answer #5546 : 1.5i PAR - A design fails in PAR with ERROR:xvkap:62 - IOB IOBUFAGP is incompatible with SelectIO standards ...
Xilinx Answer #5547 : 1.5i Virtex bitgen fails to create a bitfile if -t option is used, but no error is reported
Xilinx Answer #5548 : M1.5i Timing - TW is not correctly distributing a Net PERIOD if the CLKDV has a non-integer value.
Xilinx Answer #5549 : M1.5i Virtex Timing - Timing Engine incorrectly propagates PERIOD thru 2 CLKDLLs in Virtex.
Xilinx Answer #5550 : M1.5i Virtex Timing - Timing tools are not heeding DUTY_CYCLE_CORRECTION parameter.
Xilinx Answer #5551 : 1.5i Timing - Mapper is not including Both halves of BLOCKRAM in clock net TNM.
Xilinx Answer #5552 : M1.5i Timing -Several changes are needed for virtex names to correspond to data sheets.
Xilinx Answer #5553 : 1.5i Virtex Back Annotation - Simulation errors during physical back annotation (no .ngm) due to clock renaming by map.
Xilinx Answer #5554 : 1.5i Virtex PAR - Router is routing backbone net to IOB CLK pins incorrectly.
Xilinx Answer #5555 : 1.5i PAR - Guide fails to match comps when guiding with identical design.
Xilinx Answer #5556 : 1.5i SP2 XC4000XV PAR - Most of the paths on octal lines in 4000xv are not being represented as being buffered.
Xilinx Answer #5557 : 1.5i Virtex Bitgen - Incorrect bitstream programming for constant values in Virtex.
Xilinx Answer #5558 : 1.5i Virtex Bitgen - Memory cell programming for Virtex I/O standards need to change for SSTL2 I/II
Xilinx Answer #5566 : M1.5i SpartanXL Timing - New speed files are available for Spartan XL in Service Pack 2.
Xilinx Answer #5568 : 1.5i Virtex Map - FATAL_ERROR xvkma:xvkmapper:c:1691:1.112 - Cannot satisfy LOC/RLOC constraint on
Xilinx Answer #5569 : PCILOGIC simulation model missing two inverters
Xilinx Answer #5570 : 1.5i Virtex Bitgen - PCI CE wrap-around pip is not enabled in the Virtex BFD.
Xilinx Answer #5571 : 1.5i PAR - Performance of 4062xla-09 design is inferior to 4062xl-09.
Xilinx Answer #5572 : 2.1i: 9500/XL: How to internally source BUFGTS, BUFGSR, BUFG
Xilinx Answer #5573 : 1.5i CPLD - 9572xlcs48 package availability
Xilinx Answer #5575 : 1.5i Virtex Map - Segmentation Fault
Xilinx Answer #5576 : M1.5i - Ngdbuild : ERROR:basnu:192 - The LUT2_L symbol ... does not have any programming information
Xilinx Answer #5582 : M1.5i PAR: ERROR:xvkap:50 - Design conataines net <netname> driven by TBUFs that are constrained to different rows
Xilinx Answer #5584 : F1.5i 9500XL: Functional Simulation and Timing Simulation work but the outputs are not working correctly.
Xilinx Answer #5589 : Virtex: What are the empty site IO blocks for virtex in fpga_editor.
Xilinx Answer #5591 : 1.5i Virtex PAR - PAR terminates abnormally after initial placement if a large percentage of BLKRAMs are being used.
Xilinx Answer #5595 : LogiCORE PCI32 4000/Spartan: VHDL synthesis/simulation with PCI LogiCORE v2.0, Synplify 5.0.8, & M1.5i
Xilinx Answer #5597 : F1.5i, Project Manager: Project Manager buttons grayed out
Xilinx Answer #5601 : Foundation Express: Cannot create chip in Synopsys project
Xilinx Answer #5602 : Design Manager M1: Failed to create empty document
Xilinx Answer #5605 : VIRTEX, COREGEN: Can 4K COREGen RAMs and ROMs be targeted to Virtex devices?
Xilinx Answer #5609 : M1.5i Virtex VHDL simprim model incorrect for SRL16, SRL16_1, SRL16E, and SRL16E_1 models
Xilinx Answer #5612 : Foundation Express: Cannot find license file (-1,73:2) after installing 1.5i Service Pack
Xilinx Answer #5616 : 1.5i PAR - Virtex design with apparently good RPM fails during placement.
Xilinx Answer #5624 : know
Xilinx Answer #5625 : Instantiating Xilinx Library elements in Foundation 1.5xx HDL flow: where can you get interface information
Xilinx Answer #5630 : V1.5.2 COREGEN: Information on the Coregen v1.5.2 release shipped with F1.5i_sp1/sp2, and A1.5i_sp1/sp2 (Service Pack 1 and 2 for Foundation F1.5i or Alliance A1.5i).
Xilinx Answer #5631 : Foundation Express v3.1 available in F1.5i Service Pack 1 via Web
Xilinx Answer #5633 : FPGA Express: Syntax error at or near token 'bxx (VE-0)
Xilinx Answer #5636 : XC4028XLA/XC4036XLA: Is this device still available in the HQ304 package?
Xilinx Answer #5637 : M1.5/2.1i: EPIC/FPGA Editor: Displays edge decoders for Spartan and SpartanXL devices.
Xilinx Answer #5638 : Foundation Project Manager 2.1i: E:#0 DPM Error: Project creation/opening failed. Invalid Project
Xilinx Answer #5645 : Foundation F1.5/F1.5i: When trying to execute the Project Manager, nothing happens
Xilinx Answer #5648 : V1.5.2/V1.5i_sp1 COREGEN, INSTALL: Coregen 1.5.2 in A1_5i Service Pack 1 contains readme from the older 1.5 release / How to verify the Coregen 1_5i Service Pack 1 install.
Xilinx Answer #5649 : Virtex: How to instantiate CLKDLL in the HDL code
Xilinx Answer #5650 : F1.5 Express: Warning: The pin from <A> of <B> has no corresponding port <C> on the design. FE-LINK-7
Xilinx Answer #5651 : Foundation Schematic: Do not use the Power Symbols (VCC, GND) from the Schematic Editor Toolbar
Xilinx Answer #5657 : **Obsolete**F1.5i_sp1: 9500XV - Can be found under the 9500XL pull-down menu
Xilinx Answer #5658 : 9500: JTAG Programmer 1.5 9500_v1.bsd or 9500_v2.bsd files needed
Xilinx Answer #5661 : C1_5.17 COREGEN IP MODULE LIBRARY UPDATE: Known problems with the ROM-Based Correlators, NCO, and Divider
Xilinx Answer #5662 : Virtex JTAG - How to configure a Virtex device via JTAG with debugging options
Xilinx Answer #5663 : 1.5i 4KX* MAP - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.113 - Cannot satisfy LOC/RLOC constraint on comp H14/H57/I610/$1I106/$1I64 Process will terminate. Cannot satisfy LOC/RLOC constraint on comp H14/H57/I610/$1I106/$1I64 Process will terminate.
Xilinx Answer #5666 : Virtex Configuration: Configuring Multiple Virtex Devices in SelectMAP mode.
Xilinx Answer #5667 : F1.5i Service Pack Install: "Cannot Find Program Location" when installing Design Entry Tools Update
Xilinx Answer #5668 : F1.5i Service Pack 1 Install: An Error occurred during the move data process: -115
Xilinx Answer #5669 : m1.5: Constraints Editor: TIMESPECs which reference other TIMESPECs are displayed incorrectly
Xilinx Answer #5670 : F1.5i Service Pack 1 Install: An error occurred during the move data process: -113
Xilinx Answer #5675 : Virtex: Virtex doesn't have IFDs and OFDs
Xilinx Answer #5677 : Project Manager M1: Project Manager (PCM) disappears when opening/invoking a project
Xilinx Answer #5678 : Exemplar Spectrum: Read gives :hdl_file.v", line 14: Error, Empty port is not supported
Xilinx Answer #5680 : Install 1.5i: Installation of Service Pack or other updates errors out with "System error during decompression"
Xilinx Answer #5681 : Exemplar: After upgrading from Spectrum 1998.2d build 5.94 to 1998.2d build 5.103 my project now targets Spartan where the saved project was targeting Virtex?
Xilinx Answer #5682 : FPGA Express: Inserts OBUF when instantiating OBUFE in HDL design
Xilinx Answer #5683 : F1.5is1, Express 3.1: Incorrect speed grades listed for XC4000XLA family
Xilinx Answer #5684 : Design Manager 2.1i: Non-timing driven implementation of Virtex/VirtexE/Spartan2 can result in lower design performance
Xilinx Answer #5685 : F1.5i_sp1: 9500XV auto-selection does not work automatically in current release
Xilinx Answer #5686 : 1.5i XC4000XL PAR - Router fails to meet timing on TBUF nets, but re-route is successful.
Xilinx Answer #5688 : LogiCORE PCI: STOP_IO asserted, S_TERM low, & S_READY is high in target app
Xilinx Answer #5689 : M1 PAR: How can I access multple processors in a single node using the Turns Engine?
Xilinx Answer #5690 : Foundation Express: VHDL files for user libraries are not found if project is moved
Xilinx Answer #5691 : F1.5is1: Foundation Schematic Editor: Error Reading File/ Error Writing File/ Reading file [filename] failed/ Writing file [filename] failed.
Xilinx Answer #5693 : Virtex: How to use BlockRams in HDL codes
Xilinx Answer #5695 : f1.5isp1: When ABEL synthesis engine is run in NT 4.0 SP3, tkwdog process freezes computer (opening project, syntax check, synthesize, add to project)
Xilinx Answer #5697 : SYNPLIFY: Using FDCE or FDPE support for 9500 synthesis
Xilinx Answer #5698 : FPGA Express 3.x: Error: Target 'L' is incompatible with assigned value in routine "=" line 490 when using IEEE.numeric_std (HDL-40)
Xilinx Answer #5702 : Power Estimation for 4000XLA and 4000XV families
Xilinx Answer #5703 : F1.5i Service Pack 1 Install: "Corrupt Cabinet File" when extracting fpgaexp.ico from express_31.exe
Xilinx Answer #5704 : 1.5i 4KXL PAR - 4036xl design unable to place some CLBs clocked by BUFGE
Xilinx Answer #5705 : LogiCORE PCI: Can the top-level of hierarchy be modified in a Xilinx PCI design?
Xilinx Answer #5706 : FPGA / Design Compiler 1999.05: Using SYNLIBS settings produces warning UISN-26
Xilinx Answer #5709 : F1.5J : Problem installing Service Pack 1 or 2 on to F1.5J (Japanese version) ONLY FOR JAPANESE CUSTOMERS
Xilinx Answer #5712 : SYNPLIFY: "xcmap.c: Error: primitive view:PrimLib.z(prim) not handled yet"
Xilinx Answer #5713 : pld_men2edif ERROR:basnu:120 - logical net "port_signal_name" has multiple pad connections
Xilinx Answer #5718 : Virtex JTAG - How to program multiple Virtex devices in a JTAG chain
Xilinx Answer #5727 : COREGEN, LOGIBLOX: Differences between 4K Dual Port RAM generated by Coregen and LogiBLOX
Xilinx Answer #5732 : 1.5 XC4000XL Map - ERROR:x4kma:367 - An illegal carry configuration has been detected...
Xilinx Answer #5736 : 1.5i Virtex Map - Bus error (core dumped) on V300 design
Xilinx Answer #5738 : Virtex: What are the temperature sensing diode pins (DXP and DXN)?
Xilinx Answer #5742 : Virtex: What is the minimum pulse width for the PROGRAM pin?
Xilinx Answer #5744 : Foundation/Alliance 1.X tools: Installing on NTFS
Xilinx Answer #5747 : M1.5i/2.1i: UCF priority
Xilinx Answer #5750 : 1.5i Map - FATAL_ERROR:xvkma:xvkmaslice.c:4087:1.101 - domergeslices got empty slot for frag comp...
Xilinx Answer #5751 : 2.1i Design Compiler - Typo in template .synopsys_dc.setup file (PARSE-1)
Xilinx Answer #5756 : V1.5, V1.4 COREGEN: Coregen EDIF targets 4013EPQ240-3 part when architecture is set to 4000 and Spartan families
Xilinx Answer #5757 : 1.5i PAR - Bogus PAR error regarding VREF : ERROR: xvkap:61
Xilinx Answer #5760 : LogiCORE PCI: Are we free to use any BAR desired for I/O or Memory space?
Xilinx Answer #5765 : Foundation/Alliance 2.1i: Missing help files for CPLD only installs
Xilinx Answer #5767 : Design Manager M1.5: Unix - Cannot execute binary file when trying to run design manager . . . Exec format error
Xilinx Answer #5770 : CPLD 9500XL: How much current can the I/O sink/source?
Xilinx Answer #5772 : 1700D: Military part members of the 1700D family are not being obsoleted.
Xilinx Answer #5777 : A1.5i: XC4000XV Synopsys synthesis and designware files are available
Xilinx Answer #5778 : 1.5i, 2.1i 4K Map - Guided map of unchanged design is unable to guide several CLBs.
Xilinx Answer #5779 : 2.1 Virtex PAR - Guided Par can't match components using guide file created in 1.5i release or earlier.
Xilinx Answer #5781 : 1.5i Virtex Map - Map gives FATAL_ERROR:xvkma:xvkmaslice.c:5862:1.101
Xilinx Answer #5783 : COREGEN C1_5.17 IP MODULE PATCH INSTALL: Cannot overwrite existing Coregen directories on PC
Xilinx Answer #5784 : 2.1i JTAG Programmer - 4000E/4000EX/4000XL/5200/Spartan do not have an IDCODE
Xilinx Answer #5785 : M1.5i: EPIC: core dump with segmentation fault when adding a pin to a block
Xilinx Answer #5787 : V1.5.2 COREGEN: Coregen User Guide version specified incorrectly as v1.5.2i on the cover page
Xilinx Answer #5788 : NGDBUILD: ERROR:based:58 - On or above line 890 in file "repic.edf" with Synplify netlist
Xilinx Answer #5791 : FPGA Express 3.2: Verilog pre-processor available to allow 'ifdef, 'else, and 'endif
Xilinx Answer #5792 : 1.5i - A new package file is available to correct pinout errors in XC40150XV-BG432.
Xilinx Answer #5793 : NGD2VER/NGD2VDHL 1.5: The -r option causes inversion of tristate line on the OBUFT
Xilinx Answer #5795 : XC9500/XC9500XL/XC9500XV: What CPLD devices are supported in the 1.5i Service Pack 1?
Xilinx Answer #5796 : Timing Constraint on BSCAN element
Xilinx Answer #5797 : LogiCORE PCI32 Spartan: New UCF files for use with the M1.5i release are now available
Xilinx Answer #5800 : FPGA Express 3.3: Inferring SRL16 and SRL16E components for Virtex/E devices
Xilinx Answer #5804 : M1.5: TRCE: WARNING:bastw:544 - Clock nets using non-dedicated resources were found
Xilinx Answer #5808 : 1.5i Virtex Map - Application error: the instruction at address x referenced memory at address x
Xilinx Answer #5810 : 1.5i Map - A case has been seen where -pr b option drops an inversion between flop and BUFT.
Xilinx Answer #5815 : 2.1i COREGEN: Coregen 2.1i displays all known projects for all users in the available projects listing in multi-user environment
Xilinx Answer #5818 : 1.5i SP2 Virtex PAR - Internal Error : Basnd: basndtiming.c:251:1.25.1.2 - Internal delay calculator failure
Xilinx Answer #5819 : Hardwire JTAG - Does Hardwire support JTAG?
Xilinx Answer #5824 : 1.5i Map - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.113 - Cannot satisfy LOC/RLOC constraint
Xilinx Answer #5828 : M1.5i SP2 XC4000XV Timing - PAR doe not route optimally due to speed file problems.
Xilinx Answer #5829 : 1.5i SP2 Hitop - ERROR:cl244 - [Internal Error] Corrupt partition product term.
Xilinx Answer #5830 : 1.5i SP2 Bitgen - Equations for I1, I2, and I3 -> PCI_CE are wrong
Xilinx Answer #5831 : 1.5i SP2 Virtex Bitgen - Pulldown should not be enabled on VREF pins.
Xilinx Answer #5832 : 1.5i SP2 Virtex Bitgen - Bitgen is setting security bits too soon causing configuration to fail
Xilinx Answer #5834 : 1.5i SP2 Hitop - Hitop fails to select 9536XL and 9572XL devices in autoselect mode.
Xilinx Answer #5835 : 1.5i SP2 Virtex Map - Cannot satisfy LOC/RLOC constraint for CC8CE and FDRSE design
Xilinx Answer #5836 : 1.5i SP2 Virtex Map - Enhancements to guide methodology for Virtex PCI designs.
Xilinx Answer #5837 : 1.5i SP2 X4000XV Timing - Some incorrect speed values have been corrected in the XC4000XV speed files.
Xilinx Answer #5838 : 1.5i SP2 Virtex PAR - PAD report does not report VREF pins correctly
Xilinx Answer #5839 : M1.5i Sp2 XC4000XV Timing - XC4000XV timing analysis incorrectly reports ~20ns delay on data input to INFF.
Xilinx Answer #5840 : 1.5i SP2 Virtex Bitgen - Virtex progammable clock delay support added for use with PCI 66 MHz designs.
Xilinx Answer #5841 : 1.5i SP2 Virtex MAP - Map does not correctly pack FMAPs when using CORE_LUT_CONSTRAINT
Xilinx Answer #5842 : 1.5i SP2 Virtex Map - PCILOGIC pins TRDY and IRDY are incorrectly swapped.
Xilinx Answer #5844 : 1.5i SP2 Virtex Map - A net splitting feature has been added for multiple fanout IRDY/TRDY nets in PCI.
Xilinx Answer #5846 : 1.5i SP2 CPLD Packages - The BG256 package additions for 95288XL and 95288XV
Xilinx Answer #5847 : 1.5i SP2 9500XL Hprep6 - Incorrect implementation of XOR3 and greater in hprep6
Xilinx Answer #5848 : 1.5iSP2 JtagProgrammer - Virtex devices JTAG Programming support added.
Xilinx Answer #5849 : M1.5i SP2 XC4000XLA Timing - New speed data is available.
Xilinx Answer #5850 : 1.5i SP2 Virtex Device Representation - pci_ce signal in top right and bot right tiles connects to wrong hexes.
Xilinx Answer #5851 : 1.5i SP2 Virtex back annotation - Ngdanno issues warning stating that 100% back annotation is not possible.
Xilinx Answer #5852 : 1.5i SP2 Virtex PAR - PAR rips up and reroutes guided nets in PCI design.
Xilinx Answer #5853 : 1.5i SP2 Virtex Device Representation - PCIIOB model needs a bel to drive the PCI pin
Xilinx Answer #5854 : 1.5i SP2 XC4000XV Device Representation - There are 4 bogus PIPs in the lower right corner of 4000xv NPH's
Xilinx Answer #5855 : 1.5i SP2 MAP - Application Error has occured (access violation) , MS Studio issue
Xilinx Answer #5856 : 1.5i SP2 Hitop - Hitop fails with an application fault when used w. newer vers. of MSVCRT.DLL
Xilinx Answer #5858 : M1.5is2 MAP:WARNING:xvkdr:3 - blockcheck: Dangling SRMUX input. SRMUX is configured to use pin SR, but pin SR is not connected
Xilinx Answer #5859 : M2.1i: Specifying PULLUPs/PULLDOWNs in UCF
Xilinx Answer #5861 : 1.5i Virtex Map - RLOCs cannot be applied to SRL16s
Xilinx Answer #5862 : 1.5i : Foundation Install and Release document: p. 115, "No Bitstream generation included for Virtex"
Xilinx Answer #5864 : M1.5i: Timing Analyzer: SRL16s are placed in both 'RISING' and 'FALLING' clock groups by TRCE
Xilinx Answer #5865 : Virtex Configuration: Done goes High, but device does not startup
Xilinx Answer #5873 : 1.5i Virtex Map - Virtex macro ADD16 crashes MAP when inputs and outputs are not driven/sourced
Xilinx Answer #5886 : 1.5i SP2 Virtex PAR - FATAL_ERROR:ROUTE:xvkrtexpand:1867:1.17.1.4 - Internal router error.
Xilinx Answer #5887 : Alliance 1.5i Service Pack 2 is now available
Xilinx Answer #5889 : 1.5i Virtex Map - MAP is dropping some FF paths from Period constraint.
Xilinx Answer #5894 : Virtex Timing: What is the CLKA -> CLKB setup time for different ports (Tbccs) timing parameter?
Xilinx Answer #5896 : M1.5: TRCE: Incorrect skew calculation between clock domains
Xilinx Answer #5899 : 2.1i COREGEN, SOLARIS 2.6: Project Choose Browser takes several minutes to browse to /home and other mount points on Solaris 2.6 (REL)
Xilinx Answer #5905 : HW-130: Version 4.5/4.61 Supports the operating systems Win95, Win98, and WinNT
Xilinx Answer #5907 : V2.1 COREGEN: Path entered in New Project GUI is not read in when you click on Browse button
Xilinx Answer #5918 : 1.5i Timing - PAR appears to hang due to problem with OFFSET constraint.
Xilinx Answer #5921 : 9500 datasheet - What is the "block software selectable" option for pullup resistors?
Xilinx Answer #5923 : 1.5i Service Pack 2 Data File Updates are available.
Xilinx Answer #5926 : LogiCORE PCI docs: Not clear on how to drive S_READY and S_TERM
Xilinx Answer #5927 : M1.5i Virtex Pin2ucf - An incorrect signal name is used in the .ucf data for Clock signals in Virtex devices.
Xilinx Answer #5928 : M1.5i: Lab Install of Hardware Debugger, Jtag Programmer, Prom File Formatter: Tools don't start
Xilinx Answer #5930 : 1.5i Map - WARNING:xvkdr:3 - blockcheck: Dangling CYINIT input. CYINIT of comp
Xilinx Answer #5931 : M1.5i: EPIC: Error:bascp:242 - Can not modify constraint that applies to multiple objects.
Xilinx Answer #5934 : M1.5i: Floorplanner hangs when openning from DM or Core Dumps when openning from command line.
Xilinx Answer #5936 : Foundation F1.5i Service Pack 2 available via Web
Xilinx Answer #5939 : M1.5i/2.1i: When a group gets made and a TIG is placed THRU this group the TIG gets ignored
Xilinx Answer #5941 : Virtex: For the IO timing numbers, what capacitive load was used?
Xilinx Answer #5942 : 4000xla/xv : Pins 158, 108, 109 missing on 4028xla-hq240 Pin 91 missing on 4028xla-hq208
Xilinx Answer #5943 : M1.5i: Timing Analyzer: Application error:<program.exe> the instruction at 0x780017## referenced at memory 0x########. The memory could not be written".
Xilinx Answer #5952 : FPGA / Design Compiler 1999.10: Synthesizing with Synopsys version 1999.10 may give UISN-27 error
Xilinx Answer #5956 : HW-130-CAL : What is the Calibration Adapter? Do you normally need it?
Xilinx Answer #5958 : FPGA Compiler / Design Compiler: LUT programming information dropped for Virtex designs (NgdHelpers:406)
Xilinx Answer #5959 : FPGA Express 3.1: VHDL syntax error on "alias" statement VSS-1081 (not supported)
Xilinx Answer #5961 : LogiCORE PCI Synplicity flow: xcmap.c: Error: primitive view:PrimLib.z(prim) not handled yet
Xilinx Answer #5964 : M1.5 Install: Device Download Install does not install the MFC42.DLL
Xilinx Answer #5965 : M1.5i/2.1i; Timing: PERIOD constraint analyzes path from a FROM:THRU:TO spec
Xilinx Answer #5967 : Foundation Express: Feature has expired (-10, 32) when starting the program
Xilinx Answer #5968 : 2.1i: Virtex schematic library for Viewlogic that supports Functional Simulation in Viewsim
Xilinx Answer #5969 : 1.5i Virtex Map - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.113 - Cannot satisfy LOC/RLOC. . .
Xilinx Answer #5972 : FPGA Express 3.1: unexpected errors, access violation (0xc0000005), Dr. Watson
Xilinx Answer #5974 : Foundation schematic F1.5is1 - resets synthesis options when you push into a HDL macro
Xilinx Answer #5975 : F1.5iS1 Simulation: Error opening file <name>.cmd in project manager's console
Xilinx Answer #5983 : 1.5i Map - Bus error (core dumped) after Merging...
Xilinx Answer #5988 : LogiCORE PCI64 Virtex (v3.0): What version of Xilinx software is required by the LogiCORE PCI64 Virtex?
Xilinx Answer #5989 : LogiCORE PCI64 Virtex (v3.0): 66 MHz implementation issues
Xilinx Answer #5990 : JTAGPGMR 1.5x: Using parallel port beyond LPT1 and LPT2
Xilinx Answer #5991 : LogiCORE PCI Virtex (v3.0): Is timing simulation supported for the LogiCORE PCI64 Virtex?
Xilinx Answer #5992 : 2.1i LOGIBLOX, WINDOWS: Unable to start or invoke LogiBlox GUI on Win 95 / 98 in standalone command line mode
Xilinx Answer #5993 : Design Manager F1.5i: Cannot locate fndtn/active/exe/appcn32.dll, suspro32.dll, s95log.dll
Xilinx Answer #5995 : Virtex clkdll: How to simulate CLKDV_DIVIDE in pre-synthesis functional simulation.
Xilinx Answer #5999 : 2.1i CPLD Fitter: Global Offset in 9500 is ignored
Xilinx Answer #6002 : V1.5i, V1.5, V1.4 COREGEN : Unsatisfied link error on startup
Xilinx Answer #6003 : 1.5i Virtex Map - INTERNAL ERROR: xvkmabel.c: 559:1.21 - XVKMA_BEL_C:: getbelsconntosig(): . . .
Xilinx Answer #6008 : LogiCORE PCI64 Virtex (v3.0): Some timespecs have zero items analyzed in the TRCE report
Xilinx Answer #6012 : V2.1i COREGEN, C_IP2: Latency may be incorrect in Virtex Variable Multiplier VHDL behavioral model
Xilinx Answer #6013 : FPGA Express: Verilog keyword "tri" causes Express to crash (Cannot create chip in Synopsys project) (Abort at 470)
Xilinx Answer #6014 : Foundation 1.5is1: Archive utility does not include underlying files....
Xilinx Answer #6016 : 2.1i COREGEN: Projects accessible only to a local user may get displayed in the global Known Projects list. (REL)
Xilinx Answer #6017 : 2.1i COREGEN: Busy cursor goes away if Overwrite Files dialog pops up before elaboration of a module begins.
Xilinx Answer #6018 : 2.1i COREGEN: Getting Started dialog does not always open up the right "last project"
Xilinx Answer #6019 : 2.1i COREGEN, MTI, VERILOG: MTI "xxxx already exists" compilation errors when analyzing CORE Generator Verilog behavioral models
Xilinx Answer #6020 : 2.1i COREGEN: Coregen may take a while to start up the first time.
Xilinx Answer #6025 : Prom File Formatter: basbs - size of PROM 0 (...) exceeds maximum size of 1024K for Mcs86 prom format
Xilinx Answer #6026 : F1.5i Install:Installed devices are not written in fileset.txt for Base package install
Xilinx Answer #6028 : Foundation F1.5i Service Pack 2: How to add new CPLD/FPGA devices into the Foundation parts selector
Xilinx Answer #6032 : 1.5i SP1 - ERROR:xvkap:53 RLOC constraints have been applied to a subset of the slices
Xilinx Answer #6033 : Virtex: Virtex power estimator, where to find the program, and its user guide.
Xilinx Answer #6034 : Virtex designs running ngdbuild: ERROR:NgdHelpers:342 - input pad net "xxxx" drives multiple buffers
Xilinx Answer #6035 : MAP: 1.5i: ERROR:baste:180 - "RLOC" suffix on. . .
Xilinx Answer #6037 : 2.1i COREGEN, MTI, VHDL: Required MTI commands for analyzing/compiling the CORE Generator VHDL models
Xilinx Answer #6038 : 2.1i COREGEN: Netscape launched from COREGEN does not point to the correct page
Xilinx Answer #6039 : 2.1i COREGEN: A new Netscape session is launched when you click on Web links in COREGEN.
Xilinx Answer #6040 : A1.5isp2/F1.5isp2: 9500XL Designs with FDCE, FDPE, or other CE elements require this new jedec file creation update.
Xilinx Answer #6052 : M1.5i/2.1i: Trce: Dr. Watson Exception access violation (0xc0000005) Address 0x10xxxxx
Xilinx Answer #6053 : A1.5is2/F1.5is2: 9536XL JtagProgrammer gives error integrity...'designname(Device1)': Programming terminated due to errors.
Xilinx Answer #6054 : A1.5s2/F1.5is2: 95288XL Programming support and jedec file creation support
Xilinx Answer #6057 : M1 Map - ERROR:x4kma:7 - The CY4 symbol "$blah" has no signal connected to CIN
Xilinx Answer #6058 : M1.5isp2 Map:Fatal Error:xvkcm:xvkcmverify.c:47:1.11.1.2 - mistmatched number of primitives 52 != 53 for 'PCIIOB'
Xilinx Answer #6062 : 1.5i/2.1i: Virtex Back Annotation - Incorrect models for OBUF_GTL and OBUFT_GTL
Xilinx Answer #6066 : M1.5i/2.1i: RISING and FALLING constraint grouping does not filter out non-FF elements
Xilinx Answer #6067 : M1.5i/2.1i: How to obtain timing information from new speedfiles: Speedprint utility
Xilinx Answer #6068 : 2.1i, V1.5 COREGEN, DATASHEETS: the CLB count is incorrect for a 16-bit wide loadable registered adder
Xilinx Answer #6069 : 1.5i 3K Map - Map ignores unbonded pad types and creates bonded IOBs which can lead to overmapping and bitgen errors.
Xilinx Answer #6071 : NGD2VER/NGD2VHDL: Creates netlists with undriven signals that produce 'X' outputs in simulation
Xilinx Answer #6073 : 2.1i COREGEN: COREGEN project path drop-down menu does not appear to be dismissed if you click outside of it
Xilinx Answer #6074 : M1.5iSP2 : XC4000XV net delays changed in the new speed files.
Xilinx Answer #6075 : A/F1.5is2 SP2 INSTALL : ERROR - Could not create file <path to 1.5i /bin/hp /libbasnu.sl>. Text file busy
Xilinx Answer #6080 : Foundation F1.5i: Upgrading your Foundation Express license to 3.1
Xilinx Answer #6081 : 2.1i COREGEN: CORE Generator does not display installed cores until a valid project has been specified
Xilinx Answer #6082 : 2.1i COREGEN: How to install new CORE Generator IP updates / newly installed cores not visible
Xilinx Answer #6085 : FPGA Express: How to instantiate I/O pads in your HDL code
Xilinx Answer #6087 : Documentation: Product Prefix Definition (AL, AM, DO, DS, UO, US, etc)
Xilinx Answer #6089 : 1.5i Virtex PAR - Placer crashes on design with routed hard (.nmc) macros.
Xilinx Answer #6090 : Hitop: Impelemented Equations within the Fitter Report don't have the .pin or .fb extensions when using ABEL.
Xilinx Answer #6091 : Foundation Schematic: Macro - Not updating when 'create netlist from current sheet'
Xilinx Answer #6094 : 2.1i: TRCE/Timing Analzyer The Datasheet Report is inconsistent with verbose path report
Xilinx Answer #6102 : Programmers : What programmers can I use to configure my Xilinx PROM?
Xilinx Answer #6104 : 2.1i JTAG Programmer - Programming via JTAG, DONE goes high but registers not responding
Xilinx Answer #6106 : Virtex : Where can I find I-V curves for Virtex IO's?
Xilinx Answer #6110 : Virtex: What are the differences between Vref(R) and Vref(r) in the package drawings
Xilinx Answer #6113 : F1.5i: Functional/Gate level Simulation on flatten EDN give 'Warning 9199: Unknown component - U1, sym_name.
Xilinx Answer #6116 : V2.1i COREGEN, HP: NullPointerException thrown after error dialog pops up on HP only (release notes)
Xilinx Answer #6121 : NGD2VER/NGD2VHDL: WARNING:baspp - hierarchical block"" has been flattened. Its pins will not be observable in the generated simulation model.
Xilinx Answer #6126 : F1.5is2: The XC9572XL CS48 is missing from the part selector for the front-end tools
Xilinx Answer #6129 : M1.5i: EPIC: How do I change LUT equations?
Xilinx Answer #6130 : M1.5/2.1i: Constraint Editor : unable to find clock signal in global tab
Xilinx Answer #6131 : 2.1i JTAG Programmer - ERROR:basut - The IDCODE returned indicates that the instance in the boundary-scan chain is not a Xilinx part.
Xilinx Answer #6134 : MAP v1.5is2, COREGEN, SDA FIR: x4kma : 339 - The (symname) symbol "xx/xx" has no signal connected to B1. This pin must be connected . . .
Xilinx Answer #6135 : Prom File Formatter M1.5is2: basbs 186 -Unable to read file "D:/path/ver1/rev1.bit.
Xilinx Answer #6136 : JTAG - XC4000 based devices: Registers do not work properly when device is configured through JTAG
Xilinx Answer #6148 : V2.1i COREGEN, SOLARIS: Cannot bring up module customization GUI on Solaris 2.6/2.7 Openwin platform when window activation setting is set to "ClickMouse" to activate
Xilinx Answer #6149 : V2.1i COREGEN: Coregen windows may not refresh or may simply hang on Windows NT if left running for extended periods of time (REL)
Xilinx Answer #6150 : Foundation 2.1i: Cannot change color scheme in Foundation Schematic Editor
Xilinx Answer #6152 : PROMs: Migration Guide for XC1700 and XC1800 devices
Xilinx Answer #6158 : Virtex Documentation:Vref as user I/O if not needed in supporting the I/O Standard
Xilinx Answer #6159 : 2.1i Floorplanner: The Shortcuts for 'Select Loads', 'Select Source', 'Zoom to Box', 'Zoom to Part' and Expand/Collapse Hierarchy do not work.
Xilinx Answer #6164 : 2.1i: Floorplanner: The IBUFG placment is not verified by DRC check
Xilinx Answer #6165 : FPGA Express: Signal or port name expected as actual in association element (VSS-806)
Xilinx Answer #6166 : 2.1i: TRCE - The number of logic levels reported differently when different trce options are used
Xilinx Answer #6169 : Spartan - Spartan, Spartan XL, and Spartan-II bitstream compatibility
Xilinx Answer #6172 : XABEL: Can't find file x.bl0; BLIF2EQN can only translate projects with 4 or fewer functional_block (hierarchy) statements
Xilinx Answer #6173 : 2.1i: XACT Command "lca2xnf -s" is no longer available, but can be replaced by "speedprint -s" command.
Xilinx Answer #6174 : 2.1i: How to make FPGA Editor work like EPIC (zoom in/out)
Xilinx Answer #6179 : XC9500/XC9500XL/XC9500XV: What CPLD devices are supported in the 1.5i Service Pack 2?
Xilinx Answer #6183 : 9500XL: Fitting Support update for 1.5i Service Pack 2
Xilinx Answer #6184 : 1.5i: 9500XL: Hitop : BUFT and Clock polarity inverted
Xilinx Answer #6187 : V2.1i COREGEN: What's new in the 2.1i release of the CORE Generator System (TM)
Xilinx Answer #6189 : V2.1i COREGEN: List of existing / known projects does not always appear in COREGEN GUI known projects list dropdown
Xilinx Answer #6190 : V2.1i, V1.5, V1.4 COREGEN: How to obtain the latest IP (COREs) for the CORE Generator
Xilinx Answer #6191 : M1.5/M1.5i Device Download/Lab Install: Hardware Debugger: Error: The ordinal 6453 could not be located in library mfc42.dll
Xilinx Answer #6192 : Synopsys FPGA Compiler: writes out absolete timing constrains in XNF (basnu:179)
Xilinx Answer #6194 : 1.5i, 2.1i Map - A level of logic is used for inverter between IBUF and Register.
Xilinx Answer #6197 : 2.1i: FPGA Editor: FPGA Editor adds incorrect file extension when saving designs as macros.
Xilinx Answer #6198 : M1.5i/2.1i: How to utilize the Virtex secondary global clock routing
Xilinx Answer #6201 : 1.5i Virtex Map - ERROR:xvkdr:41 - blockcheck: Improper DLL feedback loop.
Xilinx Answer #6206 : LogiCORE PCI64 Virtex (v3.0): Data bits in the first data phase of a burst transaction may be incorrect
Xilinx Answer #6209 : 1.5i SP2 Virtex PAR - Par causes an invalid page fault if all IOBs on a Virtex design are locked.
Xilinx Answer #6211 : F1.5is2 - macroed.exe Exception:access violation (0xc0000005), address 0x75b315af
Xilinx Answer #6212 : 1.5i SP2 Virtex Map - FATAL_ERROR:xvkcm:xvkcmverify.c:47:1.11.1.2 - Mismatched number of primitives...
Xilinx Answer #6214 : Virtex IOFF: How to use the registers/FFS in the IOB?
Xilinx Answer #6217 : 1.5i PAR - ERROR:baspw:103 - The extension on output file ... is not valid because a PAR -n value greater than one (1) has been specified
Xilinx Answer #6223 : 2.1i/1.5 Design Manager (WS ONLY) - Selecting "Browse" dialog hangs application, Flow Engine hangs upon starting.....
Xilinx Answer #6224 : M1 Map - WARNING:x4kma:423: Signals drive closed FMAPs. Set XIL_MAP_OPEN_FMAPS
Xilinx Answer #6226 : M1.5i/2.1i: Timing Analyzer: There is a limit to the number of paths reported per timing constraint, 4096.
Xilinx Answer #6229 : Map 1.5i, 2.1i Map - FATAL_ERROR:basut:basutcname.c:410:1.8; Utilities:UtilCname.imp.c:400:1.1.2.2: Maximum name length exceeded
Xilinx Answer #6231 : V2.1i COREGEN: Core names are case sensitive in xco and batch files.
Xilinx Answer #6236 : FPGA Express 3.1: Virtex: May not always infer the MUXF5 / MUXF6
Xilinx Answer #6240 : TRCE/Timing Analyzer 2.1i: Elements are analyzed by Period and not FROM:THRU:TO
Xilinx Answer #6242 : V2.1i COREGEN: Coregen may use CPU even when idle
Xilinx Answer #6245 : 2.1i: Timing Analyzer: Blockram components are not listed in RAM Sources/Destinations element types.
Xilinx Answer #6250 : 2.1i COREGEN: Required order of analysis/compilation for CORE Generator VHDL and Verilog behavioral model libraries
Xilinx Answer #6252 : FPGA Configuration: Express Mode fails (INIT Low) for XCS40XL.
Xilinx Answer #6254 : Xact to M1.5i conversion documentation: preload_opt and mrinput attribute
Xilinx Answer #6255 : SYNPLIFY: The xc_loc attribute does not correctly write the LOC property to the EDIF for Virtex
Xilinx Answer #6260 : V1.5, V1.4 COREGEN, VERILOG, VHDL: .vhd and .v files produced by COREGEN are only for simulation.
Xilinx Answer #6261 : 2.1i Install: Uninstall sometimes doesn't appear in Add/Remove Programs
Xilinx Answer #6262 : 2.1i Install: Uninstall leaves a 16.9 MB footprint
Xilinx Answer #6263 : 2.1i Install: Install is unable to create the destination directory.
Xilinx Answer #6265 : 1.5i Timing - The Preliminary -09 speed grade for the xc4000xv family is now available
Xilinx Answer #6266 : 1.5i 4KXLA Timing - New speed data is now available for XC4000XLA
Xilinx Answer #6267 : 1.5i Virtex Timing - Preliminary -4 speed data is available for Virtex
Xilinx Answer #6268 : F1.5i and A1.5i install: invalid part or library not available for a part. How to install a part from the CD?
Xilinx Answer #6282 : Logic Modelling: smartccn fails when using back-annotated EDIF created with .NGM file (error 11032: no package pin connected)
Xilinx Answer #6286 : F1.5iS2: Using block statement structures using {,}s in Abel state machine assignments may cause incorrect equations
Xilinx Answer #6288 : F1.5iS2: XABEL: Registered Sets cannot be assigned using HEX, Octal, Binary or Decimal representation
Xilinx Answer #6289 : 1.5i Virtex Map - Not all instances a timespec are being covered by the resulting .pcf file.
Xilinx Answer #6290 : V2.1i COREGEN, ROM: COREGEN Registered ROM GUI complains too early about "No Coefficients specified" after input data width is changed.
Xilinx Answer #6291 : V2.1i COREGEN: "Error creating log file coregen.log" / Location of coregen.log
Xilinx Answer #6294 : Timing Analyzer 2.1i: Old filter settings are not removed
Xilinx Answer #6297 : JTAG Programmer 1.5 misunderstands the s20xl TQ144 bit file for s20xlt_Q144.
Xilinx Answer #6298 : FPGA Compiler II, FPGA Express: FST scripting tool: Compiler directives for using pullups/pulldowns
Xilinx Answer #6299 : M1.x: Epic : how to find pins in EPIC
Xilinx Answer #6300 : V2.1i COREGEN, MTI: "Error: Unknown identifier 'xilinxcorelib"'"when compiling Coregen VHDL Baseblox in MTI
Xilinx Answer #6301 : ngdbuild: ngdbuild does not error with conflicting LOCs
Xilinx Answer #6307 : NGDBuild WARNING:basnu:159 - Attribute "TNM_NET" on "CLK" is on the wrong type of object. Please see...
Xilinx Answer #6309 : F1.5i: Timing: Timing Error: This program has perform an illegal operation.
Xilinx Answer #6310 : F1.5i: XABEL: Syntax Error 1039: Identifier name <signal>.c is already defined, Syntax Error 1030, Syntax Error 1029...
Xilinx Answer #6312 : M1.5i: Trce: exception access violation & Error: xvkdr: 5 - blockcheck:
Xilinx Answer #6314 : 1.5i, 2.1i Virtex Map - FATAL_ERROR:basmm:basmmfact.c:1349:1.84 - Unknown pad pin type
Xilinx Answer #6316 : 2.1i: Timing Analyzer - The instruction at "0x5f40129c" referenced memory at "0x00000004". The memory could not be "read".
Xilinx Answer #6317 : 2.1i: FPGA Editor: File -> Save As Macro is always greyed out
Xilinx Answer #6318 : 2.1i: FPGA Editor: External Pin Property dialog doesn't have much functionality.
Xilinx Answer #6319 : 2.1i Floorplanner: It writes out bad constraints for BEL PAD
Xilinx Answer #6320 : M1.5/2.1i: Floorplanner: Unable to open fnf file F:\path_to\_fplan.fnf for reading
Xilinx Answer #6321 : 2.1i: Timing - Default Analysis and Advanced Analysis report maximum frequency differently
Xilinx Answer #6326 : UNISIMS: GSR/GTS behavior does not simulate with RAMB4* Verilog models.
Xilinx Answer #6330 : VCS: How to compile the 2.1i Simprim, LogiBLOX, Unisim, and Coregen HDL libraries?
Xilinx Answer #6333 : 2.1i: FPGA Editor: Adding a Button, like Listing External Pins of a macro
Xilinx Answer #6334 : SYNPLIFY: How to apply the BUFG attribute for XC9500 devices?
Xilinx Answer #6335 : 1.5i, 2.1i 4KX* PAR - Pad report contains TDO as a reserved pin even when not using boundary scan
Xilinx Answer #6336 : 1.5i Virtex Map - ERROR:xvkma:125 - PAD encr_tx_clk.PAD does not have at least one IO buffer, possibly due to bad LOC constraint or missing buffer connection. i
Xilinx Answer #6342 : M1.5: Trce 1.5is2: WARNING:basts:157 - PERIOD TIMESPEC ...contains a mixture of pad and synchronous elements
Xilinx Answer #6349 : VCS: How to back annotate the SDF file for timing simulation?
Xilinx Answer #6350 : VCS: Error: undefined system task or function $sdf_annotate
Xilinx Answer #6353 : 2.1i: Timing: 4kxl/xla & Virtex Min timing & Prorating for Temperature/Voltage
Xilinx Answer #6354 : 2.1i: FPGA Editor: There is no busy cursor while probe is routed.
Xilinx Answer #6355 : 2.1i: Constraints Editor: PULLUP/PULLDOWN constraints from the NGD file are not displayed.
Xilinx Answer #6356 : 2.1i: FPGA Editor: getattr main extpins gives strange report.
Xilinx Answer #6357 : 2.1i: Constraints Editor issues false warning (NgdHelpers: 488)
Xilinx Answer #6358 : 2.1i: Floorplanner (4kxl): ERROR:x4kma:387 - Unable to obey design constraints which require...
Xilinx Answer #6360 : 2.1i: Floorplanner: When constraints are placed over boundries, placement is not disabled.
Xilinx Answer #6361 : 2.1i: Floorplanner: The horizontal flip does not flip but shifts to the right one CLB. HP
Xilinx Answer #6362 : Virtex CLKDLL HDL simulation: LOCKED signal doesn't lock if it's not in ps time resolution.
Xilinx Answer #6364 : 2.1i: FPGA Editor: EPIC Script, FIND command does not work in FPGA Editor
Xilinx Answer #6366 : V2.1i COREGEN, WINDOWS NT, 95, 98: Cannot start up Coregen on Windows NT-- application hangs after loading SizeRequirements.class
Xilinx Answer #6368 : M1.5: Timing Analyzer1.5isp2: the exclude paths with nets option doesn't work.
Xilinx Answer #6380 : 2.1i: Constraints Editor: Pad group pulldown lists all groups instead of just pad groups
Xilinx Answer #6381 : 2.1i: Constraints Editor: FROM TO dialog doesn't allow open ended FROM TOs.
Xilinx Answer #6382 : 2.1i: Constraints Editor - Pad-to-Pad Dialog allows creation of duplicate timespec names
Xilinx Answer #6383 : 2.1i: Constraints Editor - TIMESPEC TSxx = FROM(abc) TO(xyz) - WARNING : Unable to create FROM TO with tsxx
Xilinx Answer #6384 : 2.1i: Constraints Editor - Wildcard symbol " * " is not supported by Constraints Editor
Xilinx Answer #6385 : 2.1i: Constraints Editor - Only first of several similar constraints placed in the editable constraints window
Xilinx Answer #6386 : 2.1i: Constraints Editor - Can not create relative FROM PADS TO PADS constraints in the FROM/THRU/TO dialog
Xilinx Answer #6387 : 2.1i: Constraints Editor - Cannot remove point from existing FROM/THRU/TO constraint
Xilinx Answer #6388 : 2.1i: Constraints Editor: Can't override TSid from a source constraint
Xilinx Answer #6389 : 2.1i: FPGA Editor: ERROR:FPGAEditor:133 - Illegal comptype name "iob" specified
Xilinx Answer #6390 : 2.1i: Timing Analyzer - Under the File menu, the Most Recent Updated (MRU) items are enabled even when the list is empty
Xilinx Answer #6392 : 2.1i: Timing Analyzer: Path items counts for twr file does not match the actual path items for designs with circuit loops.
Xilinx Answer #6395 : Project manager: lists bg352 package for 95288xl when only a bg256 exists
Xilinx Answer #6401 : Simulator M1.5is2 : CLKDLL fails to function properly using offchip synchronization
Xilinx Answer #6402 : Virtex ngdbuild: ERROR:NgdHelpers:664 - Period specification "TS_clkdv" references the TNM group "clkdv", which contains only pad elements
Xilinx Answer #6404 : M1.5/2.1i: Constraints Editor: Can I specify NODELAY?
Xilinx Answer #6406 : ngdbuild Virtex designs: ERROR:basnu:118 - logical net "xxxx" has both a pullup and a pulldown.
Xilinx Answer #6407 : Installing and running Foundation1.4 and Foundation1.5i on the some Operation system
Xilinx Answer #6408 : 1.5i, 2.1i Virtex PAR - PAR crashes with Exception: access violation (0xC0000005) Address 0x031335A6
Xilinx Answer #6413 : 2.1i: Fpga_editor; Adding probes to Virtex, the banking information is required.
Xilinx Answer #6414 : 2.1i: FPGA Editor: Issuing 'getattr net' command in the command line causes Fatal Error & core dump/Dr. Watson.
Xilinx Answer #6415 : 2.1i: FPGA Editor: Chip View Mode vs Edit Mode for Block Editing.
Xilinx Answer #6416 : 2.1i: FPGA Editor: ERROR:FPGAEditor:285 - Cannot alter a global period constraint via a new attribute.
Xilinx Answer #6417 : 2.1i: FPGA Editor: Add Macro dialog opens browser in last loaded macro directory.
Xilinx Answer #6422 : Setting up/install a printer for Xilinx workstation tools.
Xilinx Answer #6427 : 1.5iSP2 Update: New device support for JTAGProgrammer and CPLD Fitter
Xilinx Answer #6429 : Virtex timing simulation: DUTY_CYCLE_CORRECTION property on BUFGDLL in UCF file may not be seen by sim model
Xilinx Answer #6431 : FPGA Express 3.3: The "dont_touch" attribute is now available
Xilinx Answer #6433 : Exemplar: My instantiated Xilinx component is getting removed by synthesis (Optimize)
Xilinx Answer #6434 : PCI Logicore 3.0: MAP error message "x4kma:387" for SpartanXL and 4000XLA flow
Xilinx Answer #6435 : ngdbuild: BUFE or BUFT cannot drive an OPAD directly for Virtex. ERROR xvkpu - The symbol page1$4p/i5 failed to join a regular I/O component as required. Buffer is not an I/O buffer.
Xilinx Answer #6436 : Foundation Express 2.1i: FPGA Express 3.3 is available in Service Pack 2
Xilinx Answer #6437 : 2.1i: FPGA Editor: Path constraint functionality is not supported.
Xilinx Answer #6438 : 2.1i Floorplanner: Map file naming is causing problems for the Design Manager
Xilinx Answer #6439 : 2.1i: FPGA Editor - The default sort order for components and nets in the list window is different than EPIC
Xilinx Answer #6440 : 2.1i: FPGA Editor - IOB components added for probing internal signals are not sorted in the List Window.
Xilinx Answer #6441 : 2.1i: FPGA Editor - The net names shown by the block edit window are truncated to the last 14 characters
Xilinx Answer #6442 : 2.1i: FPGA Editor - Is there a way to add a TSID to the list of constraints in FPGA Editor?
Xilinx Answer #6443 : Where can I find year 2000 (Y2K) compliancy of Xilinx Software?
Xilinx Answer #6445 : 2.1i: TRCE/Timing Analyzer: ERROR: basut: 162 - This Xilinx application has run out of memory ...
Xilinx Answer #6446 : 2.1i: Timing: Offset out/before won't find clock period in calculating the timing values.
Xilinx Answer #6447 : 2.1i: TRCE/Timing Analyzer: Unconstrained path report contains constrained paths & paths constrained by OFFSETs.
Xilinx Answer #6448 : 2.1i: TRCE/Timing Analyzer does not provide the ability to constrain the blockram halves separately.
Xilinx Answer #6449 : 2.1i: TRCE/Timing Analyser: Skew not automatically accounted for on Virtex low skew clocks
Xilinx Answer #6450 : 2.1i: TRCE/Timing Analyzer: Does not support reg_sr_clk path tracing control.
Xilinx Answer #6453 : Initializing Mentor Quicksim simulation: Net name for the global reset signal for CPLD's (9500)
Xilinx Answer #6459 : Block Ram simulation show outputs on a read port as 'X', even though doing read only (BRAM)
Xilinx Answer #6467 : 2.1i Install: NT users should log out after install before using xilinx tools
Xilinx Answer #6468 : 2.1i Install: Unable display Chinese characters on Trad Chin 95
Xilinx Answer #6469 : 2.1i Install: Design Manager throws an exception on startup
Xilinx Answer #6470 : 2.1i INSTALL, COREGEN, MOTIF, HP, SOLARIS: Warning: Cannot convert string "<Key>SunCopy" to type VirtualBinding
Xilinx Answer #6471 : 2.1i Install: CAE install may take over an hour to complete
Xilinx Answer #6472 : 2.1i Install: HP 11.0: ERROR - Could not find source file or directory /location/chipview.
Xilinx Answer #6473 : 2.1i Install: Entering user information: Name, Company, CD-Key, Serial Number
Xilinx Answer #6474 : NGDBUILD: Error:basnu:138 - output pad net has multiple drivers
Xilinx Answer #6475 : Foundation F2.1i: Upgrading your Foundation Express license to 3.2 or 3.3
Xilinx Answer #6482 : NGD2VER 2.1: ERROR: Portability:90 - Command line error: Switch "-u" is not allowed.
Xilinx Answer #6484 : Virtex Configuration: Can CRC be disabled.
Xilinx Answer #6485 : 2.1i: Timing Analyzer: Topic Does not exist for 'Run Macro' and 'About' GUI buttons.
Xilinx Answer #6486 : 2.1i: Timing Analyzer: "Opening Design" dialog dissappears long before design is finished loading
Xilinx Answer #6492 : 1.5i Virtex Map/PAR - Clock net LOC constraints may be ignored if IPAD to BUFG connection is used.
Xilinx Answer #6495 : Design Manager/Flow Engine M1.5i: ERROR:hi1 - No design name specified. Use "hitop -f design.ngd
Xilinx Answer #6497 : 2.1i COREGEN: CORE Generator Web links may not use the Web browser specified during 2.1i installation
Xilinx Answer #6501 : M1.5i/2.1i: TRCE: What does the timing errors in a timing report correspond to in the design.
Xilinx Answer #6502 : LogiCORE PCI: What is the comply directory in the downloaded files?
Xilinx Answer #6508 : 2.1i: Floorplanner - Does not support Win 95/98/NT file names that contain spaces
Xilinx Answer #6509 : 2.1i: Floorplanner - BELs that have been floorplanned to Area Constraints are not removed from Hierarchy Window
Xilinx Answer #6510 : 2.1i: Floorplanner - Floorplanner allows illegal BUFG placement.
Xilinx Answer #6511 : 2.1i: Floorplanner - A "shadow" is left after a refresh when dragging component
Xilinx Answer #6513 : 2.1i: FPGA Editor: How to Select/Deselect Objects.
Xilinx Answer #6516 : 2.1i: Floorplanner: Block RAM does not display correctly in bottom left and right hand corners of Floorplanner window on Solaris
Xilinx Answer #6517 : 2.1i: FPGA Editor - Selecting Virtex switch box pins sometimes highlights the pin next to it
Xilinx Answer #6518 : 2.1i: FPGA Editor - Macros cannot be deleted once they have been added to a design
Xilinx Answer #6519 : 2.1i: FPGA Editor - Autoroute returns ERROR:FPGAEditor:356 - Nothing found to autoroute.
Xilinx Answer #6520 : 2.1i: FPGA Editor - Can not have hierarchy in macros
Xilinx Answer #6521 : 2.1i: FPGA Editor - Edit/Add Macro External Pin doesn't get grayed out for Macro External Pin
Xilinx Answer #6522 : 2.1i: FPGA Editor: The same keyboard shortcut (E) is assigned to 2 itmes in the Edit menu
Xilinx Answer #6523 : 2.1i: FPGA Editor: Can't change reference location for macros
Xilinx Answer #6524 : 2.1i: FPGA Editor: Not every command saved to .scr, .out & .log files.
Xilinx Answer #6527 : V2.1, V1.5i COREGEN, FOUNDATION: Virtex block RAM generated by CORE Generator does not simulate initial values properly in Foundation functional simulation
Xilinx Answer #6533 : Foundation Express: Cannot send "Create Version" window to the background during synthesis
Xilinx Answer #6534 : UNISIMS: Alliance 2.1i (or later) changes from 1.5i (or earlier) for Verilog UNISIMS simulation
Xilinx Answer #6535 : MODELSIM VLOG: ERROR: ../../../<design>.v: Port 'OUT' not found in module
Xilinx Answer #6537 : UNISIMS/SIMPRIMS: How do I use the glbl.v module in a Verilog simulation?
Xilinx Answer #6538 : MODELSIM VLOG: Error: Unresolved reference to 'glbl' when trying to simulate a Verilog design with Alliance 2.1 (or later)
Xilinx Answer #6539 : Foundation Express 2.1i: "CONV: line X Wrong number of fields BUS" when creating HDL macro
Xilinx Answer #6540 : MODELSIM VLOG: ERROR: ../../../<logiblox_module.v>: Instantiation of 'X_OR' failed (design unit not found)
Xilinx Answer #6542 : Hardware Debugger 2.1: USB is not supported on any UNIX platform.
Xilinx Answer #6545 : Hardware Debugger 1.5/2.1: Parallel Cable toggles PROG after Download.
Xilinx Answer #6547 : 2.1i COREGEN: COREGEN may lose all entries in listing of known projects except for the last project created in mult-user environment
Xilinx Answer #6548 : Hardware Debugger 2.1: Opening a design file with a long path name may cause page fault.
Xilinx Answer #6549 : Hardware Debugger 2.1: Debugging (Capture) Features not supported for MultiLINX Cable.
Xilinx Answer #6550 : Hardware Debugger 2.1: Loss of communication with MultiLINX during download causes system crash.
Xilinx Answer #6551 : Hardware Debugger 2.1: HP 11.0 is currently not supported.
Xilinx Answer #6552 : Hardware Debugger 2.1: MultiLINX USB Host connection only supported on W95c & W98.
Xilinx Answer #6553 : Hardware Debugger 2.1: Changing baud rate resets MultiLinx Cable.
Xilinx Answer #6554 : 2.1i Design Manager - Running pld_dsgnmgr through Mentor DM or Through Exemplar's P&R tab, can not choose options for implementation
Xilinx Answer #6555 : Mentor-Xilinx Interface 2.1i: After choosing Quicksim for my simulation in the Xilinx GUI and implementing, I don't see the time_sim.edn for back-end simulation
Xilinx Answer #6556 : V2.1i COREGEN, VERILOG, VHDL: New HDL behavioral simulation flow does not generate .VHD and .V models for simulation
Xilinx Answer #6558 : Hardware Debugger 2.1: Verify fails on SpartanXL.
Xilinx Answer #6559 : V2.1i COREGEN: "ERROR: Could not locate specified browser /usr/local/bin/acroread" / Cannot launch Web browser & Acroread from COREGEN on HP
Xilinx Answer #6562 : 1.5i/2.1i Map - FATAL_ERROR:basnc:basncsignal.c:263:1.67 - Could not find a bel...
Xilinx Answer #6563 : 1.5i, 2.1i Map - A .mfp constraint for LOC'd FF is incorrecty overridden by "-pr b"
Xilinx Answer #6564 : 2.1i: Floorplanner showing unbonded power and ground IOB pins in hierarchy window
Xilinx Answer #6565 : 2.1i: Floorplanner: Area constraints can not be placed over blockram bars in virtex/virtexE
Xilinx Answer #6566 : 2.1i Timing Analyzer: Does not accept decimal or negative values for temprature in prorating options
Xilinx Answer #6567 : FPGA Editor 2.1i: Double clicking on component, doesn't open Edit Block window.
Xilinx Answer #6568 : 2.1i Spartan2 PAR - Spartan2 placer may crash when placing routed hard macros.
Xilinx Answer #6569 : Foundation Schematic 1.5is2- Conv: Netlist [objectname].alb(0):seek 0x##, invalid char 0x0
Xilinx Answer #6571 : 1.5i Map - ERROR:x4kma:339 - The CY4 symbol has no signal connected to A0.
Xilinx Answer #6572 : 2.1i Virtex Map - Device utilization appears to increase because of new default packing rules.
Xilinx Answer #6573 : 2.1i Virtex PAR - MPPR usage less effective due to less dependence on cost table differences.
Xilinx Answer #6576 : V2.1i COREGEN, WINDOWS: Problems launching Web browser .exe executable from CORE Generator if Windows Explorer "Hide file extensions" Folder option is enabled (verify)
Xilinx Answer #6577 : 2.1i: Constraints Editor: From NGD, only first period constraint is being displayed by CE.
Xilinx Answer #6579 : Workview Office: Who to contact for Workview Office license update? Required License file not found (Errror 8030)
Xilinx Answer #6583 : SYNPLIFY: Force GSR on Virtex designs does not generate a STARTUP_VIRTEX cell
Xilinx Answer #6584 : LOGIBLOX, SIMPRIM, 4K: Timing simulation of Counter does not work, all outputs are "X"
Xilinx Answer #6586 : LogiCORE PCI Data book : Incorrect pin description for Spartan/4KXLT devices
Xilinx Answer #6587 : NGD2VHDL: Generate Pin File (-pf) option in NGD2VHDL does not include all pins listed in VHDL
Xilinx Answer #6588 : Synopsys FPGA Compiler 1998.08/1999.05: Slew rate specifications on Virtex IOBs are ignored during synthesis.
Xilinx Answer #6589 : 2.1i: FPGA Editor - There is no way to stop playback of a script once it has started
Xilinx Answer #6590 : INSTALL 2.1i: Virtex E / Spartan 2(II) : Why are these families greyed out during installation / How can I enable software support for them ?
Xilinx Answer #6592 : F1.5i Foundation:Btrieve incompatibilty with Macola 7.5
Xilinx Answer #6596 : 2.1i COREGEN, MTI, VERILOG: "WARNING[xx]: .../XilinxCoreLib/xxxx.v(xx): Redefinition of macro: true" (or TRUE, false, or FALSE) when analyzing COREGEN Verilog behavioral models
Xilinx Answer #6597 : M1.5is2, par - access violation (0xc0000005), address 0x01d03564, invalid page fault in module libx45rt.dll, core dump
Xilinx Answer #6599 : 2.1i: FPGA Editor: FPGA Editor does not report a line number when reporting error in script
Xilinx Answer #6600 : 2.1i: FPGA Editor: Excessivly long load time for Virtex 1000
Xilinx Answer #6601 : 2.1i: FPGA Editor: fpga_editor_user.ini file is not recognized.
Xilinx Answer #6603 : 2.1i: FPGA Editor: Unable to unhighlight a component after adding it and highlitghting it
Xilinx Answer #6604 : 2.1i: FGPA Editor: Script playback open dialog looks in last place script loaded instead of saved.
Xilinx Answer #6605 : 2.1i: FPGA Editor: Scroll bars on Array window do not work on HPUX.
Xilinx Answer #6606 : 2.1i: FPGA Editor: Resizing the 'Array', 'Edit Block' or 'World' window does not update the size of the FPGA image on HPUX.
Xilinx Answer #6607 : FPGA Express 2.x,3.x: Express hangs while checking syntax (Abort at 1704)
Xilinx Answer #6608 : 1.5iSP2 PAR HP-UX 10.2 : cannot find libCsup.1
Xilinx Answer #6611 : V2.1i COREGEN, VIEWLOGIC, POWERVIEW v6.1, VLLINK, UNIX, FUSION v1.4 : "ERROR: Viewlogic symbol generation failed.", "WARNING: Core xxx did not generate product ViewSym"
Xilinx Answer #6616 : 2.1i: FPGA Editor: How to add a Probe to a design.
Xilinx Answer #6618 : MAP 1.5is2: FATAL_ERROR:basut:basutarray: Sort produced an unsorted list when using PCI Virtex core
Xilinx Answer #6624 : 2.1i Virtex Map - Map errors atttibuted to incorrect CLKDLL usage (ERROR:xvkmm:12 and ERROR:xvkmm:16)
Xilinx Answer #6630 : map 1.5iS2/4062xl: FATAL_ERROR:baste:bastecmpin.c:314:1.27.18.2 - NULL pinhook
Xilinx Answer #6633 : 1.5i, 2.1i PAR - High density placer (4085XL+, 4KXV) fails on area constrained TBUFs.
Xilinx Answer #6635 : JTAG BSDL - What are the Boundary Scan IDCODES for Virtex FPGAs?
Xilinx Answer #6639 : ChipViewer 2.1i: The input path is not shown when you click on a input pin in the ChipViewer
Xilinx Answer #6640 : 2.1i: Hitop: hi429 - Cannot apply TIMESPEC on what seems to be a valid signal
Xilinx Answer #6643 : 2.1i JTAG Programmer - Chain initialization does not work for FPGA's with IDCODE
Xilinx Answer #6644 : 2.1i: JTAGProgrammer: When using Parallel port LPT2, mislabeled LPT1
Xilinx Answer #6645 : CPLD Fitter 2.1i: Access violation error when using a test vector file for xc95288xl BG256.
Xilinx Answer #6647 : 2.1i: 9500/XL: ERROR:JTag - Functional test vector '5' failed for instance '68be(Device1)' at pin number 'C6'.
Xilinx Answer #6648 : Foundation Express: How to access the version information of Synopsys FPGA Express
Xilinx Answer #6650 : F1.5iS2 Sim: Warning 9204: Cannot find corresponding block pin for terminal Q15.
Xilinx Answer #6654 : M1.5is2/NGDBUILD: ERROR:basnu:93 - logical block "<blockname>" of type "f402" is unexpanded
Xilinx Answer #6655 : FPGA Express 3.2: LOC attribute not passed from HDL source
Xilinx Answer #6656 : CPLD: 9500XL: What is the drive strength of the IO (sink and source currents)?
Xilinx Answer #6657 : 1.5i SP2 PAR - Fatal Error bascmpindly .c 256:1.18 config string parse error -- primitive ocemuh is not in clkiob
Xilinx Answer #6660 : 2.1i Design Manager - The server threw an exception
Xilinx Answer #6661 : Design Manager 2.1i: On Win95 if you press implement twice,"RPC Wmsg Window" appears
Xilinx Answer #6662 : M1.5i/2.1i: Timing: Instantiated TDO Pad Conflicts With UCF Constraint Causing error baste:263
Xilinx Answer #6663 : 1.5i Map - Using the -c switch to achieve the smallest pack of a design may not give the best results
Xilinx Answer #6664 : JTAG BSDL - Does Xilinx provide configured BSDL files for post configured parts?
Xilinx Answer #6665 : 2.1i NGDAnno: NGDAnno leaves BlockRAM's inputs unconnected if they are driven by more than one power/ground or constant signals.
Xilinx Answer #6668 : 1.5i Map - INIT attribute on FDRE leads to DRC error: ERROR:xvkma:135 - Attempt to use INIT=S on RST pin of FF ...
Xilinx Answer #6669 : FPGA Express: STARTBUF is not recognized as STARTUP block
Xilinx Answer #6670 : Virtex: What happens to the I/O pins of the Virtex device during power ramp up.
Xilinx Answer #6672 : LogiCORE PCI: M2.1i PAR does not guide all connections for 4KXLA/XLT, SpartanXL/Spartan PCI cores
Xilinx Answer #6673 : Foundation Project Manager - How to add command line options to Templates for Implementing programs
Xilinx Answer #6676 : JTAG - How to instantiate the BSCAN symbol to use JTAG in xc4000 and Spartan devices using HDL?
Xilinx Answer #6679 : F1.5i Simulator: Driving a bus in CC Mode get overwritten
Xilinx Answer #6680 : 1.5i Virtex Map - Request for support of map -c (pack factor) option for virtex.
Xilinx Answer #6683 : 2.1i 9500XL Hitop - Fitting Report shows VCCIO pins as TIE on XC95288XL-BG256
Xilinx Answer #6686 : 2.1i: FPGA Editor: The pinwire property (attrib) sheet does not work.
Xilinx Answer #6690 : 2.1i Virtex PAR - FATAL_ERROR:Place:xvkapanal.c:1860:1.1.2.21.2.1
Xilinx Answer #6691 : LogiCORE PCI 64/66 Virtex: VHDL- 2040 Warnings about unsupported attributes (syn_edif_bit_format, syn_edif_scalar_format, black_box)
Xilinx Answer #6693 : 2.1i COREGEN USER GUIDE: Permissions for $XILINX/coregen/ip directory do not need to be 777.
Xilinx Answer #6694 : XFLOW 2.1i: Command Line tool that allows you to do away with batch files and scripts in order to run the Xilinx tools !
Xilinx Answer #6695 : jtag programmer 2.1i: Does verify work for virtex using parallel III cable?
Xilinx Answer #6696 : LogiCORE PCI: All signals designated s/t/s in the spec must have pull-ups on them during simulation
Xilinx Answer #6698 : LogiCORE PCI: Why does the top level PCI wrapper instantiate the PCI core wrapper instead of the core itself?
Xilinx Answer #6701 : VERILOG-XL: Running simulation
Xilinx Answer #6702 : 1.5i/2.1i: FPGA Editor/FloorPlanner: XPrinter driver files (*.drv) have incorrect permissions on HP-UX 10.2
Xilinx Answer #6704 : Design Manager M1: How to specify files (EDN, EDF, VHD, VER, SCH, etc...) to be automatically copied to your version or revision subdirectories for maintainance
Xilinx Answer #6705 : 1999 Databook: Dual-Port RAM table for XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines.
Xilinx Answer #6708 : 2.1i Virtex Map - ERROR:xvkpu - Unable to obey design constraints...
Xilinx Answer #6709 : FPGA Configuration: Done goes not high, STARTUP block used
Xilinx Answer #6710 : 2.1i: Constraints Editor; Constraints w/out quotes are interpreted as source constraints.
Xilinx Answer #6711 : 2.1i: Floorpanner: Floorplanner does not remove 'constrained' blocks when 'area constraints' is used
Xilinx Answer #6712 : 1999 DataBook: Typo in the Express Mode PROM Size for Spartan XL chips
Xilinx Answer #6713 : Virtex: What is the recommended way of setting or resetting FFs in a Virtex design? Do you still need to use STARTUP_VIRTEX block?
Xilinx Answer #6715 : Template Manager 2.1i: Selecting "List Options" produces msg. - "Cannot find this file. Please verify that the correct filename and path are given"
Xilinx Answer #6716 : 1.5is2, Constraints Editor - Crashes with access violation 0xc0000005 at address 0x002cb120/page fault 0052b120
Xilinx Answer #6718 : A1.5/F1.5 RAM16X1D Dual port RAM: Doing a read on the dpra port reads an 'X' when the clock not defined, even though this is an async read RAM
Xilinx Answer #6720 : NGD2VHDL 2.1i - Instance dll0_clkdll does not have generic named 'tperiod_clkin_posedge' (X_CLKDLL)
Xilinx Answer #6724 : 1.5i SP2 - New SpartanXL speed files are available with updated -5 numbers.
Xilinx Answer #6728 : 1.5i SP2 Virtex Map - Crash during map.
Xilinx Answer #6732 : COREGEN: What state will SOUTR and SOUTF be in if the SDA FIR is generated in non-cascadeable mode?
Xilinx Answer #6733 : Vitex BRAM VHDL simulation: setup violation on CLK A with respect to CLK B, or setup violation on CLKB with respect to CLK A
Xilinx Answer #6737 : 2.1i VirtexE PAR - PAR fails with Acess Violation on XCV100E and XCV200E.
Xilinx Answer #6738 : HP 1.5i Install : 1 archive had fatal errors. file #0. bad zipfile offset (lseek): 0
Xilinx Answer #6739 : 2.1i Virtex PAR - Virtex design is taking too long to route PWR/GND signals.
Xilinx Answer #6743 : VHDL simulation RAM16X1D: Can not perform a write unless all inputs are at a known level
Xilinx Answer #6745 : 1.5i SpartanXL - Chip Scale package files are available
Xilinx Answer #6749 : Virtex Configuration: DONE does not go high, INIT does not go low
Xilinx Answer #6752 : 1.5i JTAG Programmer - SP2 Patch update-9500XL/Win95 error when programming (Error:basut - Check the target power supply is stable...)
Xilinx Answer #6755 : 2.1i; Constraints Editor: CE is concatenating constraints causing an invalid UCF
Xilinx Answer #6759 : LogiCORE PCI32 Virtex: VHDL version of the core requires more slices than the Verilog version
Xilinx Answer #6761 : LOGIBLOX Multiplexer: When are Tristate Buffers / TBUFs used to implement a LogiBLOX MUX?
Xilinx Answer #6764 : 2.1i JTAGProgrammer - Error:JTag - The boundary-scan 'program' operation is not supported ... using SVF for the 4002xl-pq100
Xilinx Answer #6766 : Virtex: IOB registers clocked by the CLKDLL still use the delay elements on the data path, this will cause longer SETUP delay.
Xilinx Answer #6767 : 1.5i SP2 Virtex Map - FATAL_ERROR:basnc:basnccomp.c:3319:1.105 - Cannot find other bel for
Xilinx Answer #6768 : Virtex: Are Virtex devices Hot-Swap Compliant?
Xilinx Answer #6771 : V2.1i COREGEN, VHDL: "**Error: Library logical name ARITHMETIC is not mapped to a host directory"
Xilinx Answer #6772 : V2.1i COREGEN, SYNOPSYS VSS, LEAPFROG VHDL: " **Error "OTHERS is not legal in this context as it is not the only element association AND the choice is not locally static"
Xilinx Answer #6774 : Virtex: Virtex decoupling capacitor guide for V300
Xilinx Answer #6782 : NGDBUILD netlist priority: What's the searching order NGDBUILD uses to merge hierarchical modules into a .ngd file
Xilinx Answer #6789 : 1.5i SpartanXL PAR - Divide by Zero crash
Xilinx Answer #6793 : 2.1i Virtex MAP - Map will not put two unconstrained SRL16s into a single Virtex slice.
Xilinx Answer #6794 : 1.5is2 Map : FATAL_ERROR:baste:bastetspec.c:1197:1.87.18.4 - Failed to create DP_PATHDELAY_FROMTO for tspec
Xilinx Answer #6796 : 2.1i SpartanXL Map - FATAL_ERROR:OldMap:bastemacro.c:897:1.1.2.2 - Signal doesn't drive comps in macro.
Xilinx Answer #6799 : MAP: 1.5i/2.1i, FPGA Express: basnccomp.c:3346:1.1.2.4-cannot find other bel. . .
Xilinx Answer #6802 : Coregen 2.1: How do I obtain a description for each Coregen core created?
Xilinx Answer #6808 : FPGA Express 3.2: Pullup/pulldown/keeper for Virtex are incorrectly written to the netlist
Xilinx Answer #6809 : LogiCORE PCI: parity lines appear to be in conflict or not driven at all during simulation
Xilinx Answer #6814 : 2.1i Install: Add Implementation Devices does NOT work for A2.1i on Korean, Chinese, Japanese windows.
Xilinx Answer #6815 : 2.1i Install: ERROR:basilisk:6 - Problems encountered invoking program "m1map"..
Xilinx Answer #6816 : 2.1i Install: Alliance Solaris setup gives error: Exception in thread "main" java.lang.NoClassDefFoundError: com/xilinx/setup/Setup.
Xilinx Answer #6817 : 2.1i Install: Solaris Remote Access Setup Only option does not run properly.
Xilinx Answer #6818 : 2.1i Install: Win NT Environment problems, $XILINX and $PATH variables.
Xilinx Answer #6819 : 2.1i Install: Permission denied when updating a 2.1i install
Xilinx Answer #6821 : 2.1i Install: Coregen install problems on Y2K HP 10.2 system. (error can't open zipfile..)
Xilinx Answer #6823 : 2.1i Install: Online Docs Uninstall does not remove the $XILINX\doc directory.
Xilinx Answer #6825 : 2.1i Timing Analyzer: TA only produces a summary report of constraints with no paths for advanced analysis.
Xilinx Answer #6828 : Foundation 2.1i: Directory already exists. . . .Please delete it.
Xilinx Answer #6829 : V2.1i COREGEN: How to get a copy of the 2.1i CORE Generator software
Xilinx Answer #6830 : V2.1i COREGEN: How to remove a 2.1i CORE Generator project
Xilinx Answer #6831 : V2.1i COREGEN USER GUIDE, VERILOG: "Error! Module name previously declared" / Verilog parent design example is incorrect
Xilinx Answer #6836 : M1.5i: Timing: BLOCKRAMA not being included in RAMS Timegroup in Virtex Timing Constraints
Xilinx Answer #6840 : Exemplar Spectrum 1998.2 is not inferring Xilinx Virtex flip flops with both synchronous set and reset
Xilinx Answer #6841 : Exemplar Spectrum 1998.2 is connecting GSR on an instantiated OFDT to common Ground causing some trimming.
Xilinx Answer #6843 : V1.5, V1.4 COREGEN, WINDOWS NT: Text/fonts in GUI labels shows up as small squares instead of letters
Xilinx Answer #6845 : PROM: XC18V00: What is the method used to program the 1800 PROM devices?
Xilinx Answer #6847 : ngdbuild 2.1i: msvcrt.dll conflict; ucf file size limitations on NT/95
Xilinx Answer #6848 : Constraints Editor 2.1i: TNM_NET is written twice in UCF
Xilinx Answer #6850 : 2.1i JTAG Programmer - Programming support of XC1800 PROM family
Xilinx Answer #6853 : 2.1i COREGEN, F2.1i FOUNDATION, NGDBUILD: Unexpanded block error -- ... because one or more pins on the block ... were not found
Xilinx Answer #6858 : PROM XC18V00: What is the Security option and how is it selected?
Xilinx Answer #6859 : PROM XC18V00: How to select between SelectMAP, Express, and Serial Modes of configuration
Xilinx Answer #6861 : V2.1i COREGEN USER GUIDE, MTI, VHDL flow: 'Error xxxmyadder8.vhd(20): near "myadder8_top" expecting COMPONENT' in VHDL testbench example
Xilinx Answer #6862 : 2.1i Install: Design Manager not found after removing 1.5i software
Xilinx Answer #6865 : V2.1i COREGEN: Response to double clicks to invoke module customization GUIs may be erratic and/or delayed.
Xilinx Answer #6866 : V2.1i COREGEN: Update Project Core : selecting and unselecting specifc cores to be updated is very slow
Xilinx Answer #6867 : V2.1i COREGEN: The name of every CORE Generator project file MUST be "coregen.prj"
Xilinx Answer #6868 : V2.1i COREGEN, UNIX: CORE Generator does not automatically load the coregen.prj file in its startup directory.
Xilinx Answer #6873 : Libraries Guide: CB2CLED, CB4CLED, CB8CLED, CB16CLED truth table is incorrect for TC and CEO outputs
Xilinx Answer #6879 : Foundation Express F2.1i: When will the "zero-one-hot" synthesis option be supported?
Xilinx Answer #6880 : 1.5i SpartanXL Map : Exception access violation at :0x0000005 address 0x1002d3f4
Xilinx Answer #6886 : V1.5 COREGEN, VIRTEX, BLOCK RAM: Block RAM generated EDIF still contains <> bus delimiters when ( ) (parentheses) or [ ] (square brackets) were specified as the desired delimiter
Xilinx Answer #6888 : V2.1i COREGEN, WINDOWS 95/98: COREGEN starts up with a DOS window which remains on the Windows desktop
Xilinx Answer #6890 : 2.1i Foundation COREGEN: Coregen may not be able to locate the Foundation install directory on Windows
Xilinx Answer #6893 : NGDAnno: What's GSUH
Xilinx Answer #6896 : 2.1i TRCE: WARNING:bastw:544 - Clock nets using non-dedicated resources
Xilinx Answer #6897 : Mentor: I can not check nor convert my old 4K (4000 non-E) schematic design to 4KE or 4KX using A1.5 or later Xilinx software
Xilinx Answer #6899 : Exemplar: How to lock pins in the Spectrum GUI, in the VHDL code, or in a Tcl script.
Xilinx Answer #6900 : V2.1i COREGEN, WVO VIEWDRAW v7.53: How to integrate CORE Generator v2.1i into the Workview Office ViewDraw menu
Xilinx Answer #6901 : SYNPLIFY: The GR pin is not listed in the EDIF netlist when targetting the XC5200
Xilinx Answer #6902 : Virtex SSO: how did we come up with the power/ground pairs in the Select IO application notes
Xilinx Answer #6905 : 2.1i CE/Timing: How to apply a Period constraint on Virtex CLKDLL for 2.1i
Xilinx Answer #6907 : 2.1i Install: HP-UX 11.0 is not supported in this release
Xilinx Answer #6909 : 2.1i JTAG Programmer - Device Properties do not update when selecting edit -> properties
Xilinx Answer #6910 : 2.1i Install: Updating a 1.5i solaris install to 2.1i will error out.
Xilinx Answer #6911 : 2.1i Install: Solaris 2.5 is not supported in this release.
Xilinx Answer #6912 : LogiCORE PCI: Known issues with 2.1 functional simulation for the Spartan, Spartan-XL and 4KXLA PCI cores
Xilinx Answer #6913 : 2.1i Ngdanno: INTERNAL_ERROR:Anno:Ax.c:2094:1.1.2.40.2.4 - Ax::fixConfusedPins() cannot handle this configuration
Xilinx Answer #6914 : LogiCORE PCI: Known issues for Synopsys synthesis with 2.1i software
Xilinx Answer #6915 : LogiCORE PCI: Known issues with timing simulation when using the 2.1i software
Xilinx Answer #6926 : Foundation 1.5isp2 Simulator: What is the difference between .des (simulation) and .tve (waveform) files?
Xilinx Answer #6933 : M1.5i: Epic:basep:602 no component is selected
Xilinx Answer #6934 : Alliance 2.1i Quickstart Guide: Error in Synopsys Virtex run script
Xilinx Answer #6935 : Install 2.1i: An unexpected error has occurred when creating Start button folder (snippet 700)
Xilinx Answer #6937 : 1.5i Virtex Map - V300 FG456 -- Map incorrectly uses an unbonded pad.
Xilinx Answer #6947 : 1.5isp2 xvkdr:42 signal clock (clk2x) is driving pin in of u4 (bufg)
Xilinx Answer #6948 : NGD2VER/NGD2VHDL: What is the usage of the -pms option?
Xilinx Answer #6952 : 2.1i Install: How do I install 2.1i without corrupting my registry settings for 1.5i install?
Xilinx Answer #6953 : 2.1i Virtex PAR - Virtex designs with area constraints may run out of memory during placement.
Xilinx Answer #6955 : DataBook 1999: FG676 package outline drawing for Virtex devices is available on the web
Xilinx Answer #6958 : Synopsys Design/FPGA Compiler: Cannot find a valid implementation for module 'xdw_comp_uns'. (SYNH-14)
Xilinx Answer #6959 : 2.1i: TRCE/NGDBUILD/Timing Analyzer/FPGA Editor: MIN delays & changing speed grades after implementation does not work
Xilinx Answer #6964 : 2.1i Virtex Timing - There are two known issues where back annotated Virtex timing under reports delay.
Xilinx Answer #6965 : 2.1i 4KE/Spartan Timing - There is a known case where back annotated xc4000e and Spartan delays are under reported.
Xilinx Answer #6966 : Foundation 2.1i: Simulator: Timing Simulation of Virtex DLL (CLKDV_DIVIDE )
Xilinx Answer #6967 : DataBook: BSCAN IDCODE Instruction for SpartanXL is not listed in Datasheet
Xilinx Answer #6969 : 2.1i Install: Setup Failed while processing the RegistryUpdater.AddCable task....
Xilinx Answer #6971 : Virtex: Virtex devices have potential high current draw for the engineering samples
Xilinx Answer #6976 : LOGIBLOX, X-BLOX: Is there a LogiBLOX counterpart for an X-BLOX "SLICE" ?
Xilinx Answer #6977 : Virtex: Why is there no option to TIE unused interconnect?
Xilinx Answer #6980 : 2.1i Virtex PAR - Core dump with leverage guide when dealing with non-aligned carry chains.
Xilinx Answer #6981 : 9500: pull-up on JTAG pins TDI, TMS, TCK; error in 1999 DataBook
Xilinx Answer #6983 : JTAG - What to do with mode pins when using JTAG configuration for a xc4000 (any family) or Spartan/XL
Xilinx Answer #6984 : 2.1i Virtex PAR - PAR is failing to allow 2 DLL design with 3 BUFGs to complete.
Xilinx Answer #6985 : Foundation Simulator: Schematic - Problem when a hierarchy tap drives logic internal of a macro
Xilinx Answer #6986 : 2.1i Virtex PAR - Placer can not successfully place DLL configurations that worked in 1.5i.
Xilinx Answer #6987 : Foundation Express: Virtex unified library macros/primitives not recognized in HDL flow
Xilinx Answer #6988 : Foundation 2.1i: Initialization of Project Manager causes confusing behavior.
Xilinx Answer #6989 : Foundation 2.1i: Disable guide or floorplan does not work when selecting the option to copy using custom file.
Xilinx Answer #6990 : Foundation 2.1i: Custom guide file setting is reset for each new revision.
Xilinx Answer #6994 : 1.5i/2.1i Map - Xnf (sxnf) file created by FPGA Compiler is processed differently that xnf files from other vendors.
Xilinx Answer #6995 : Foundation 2.1i: Timing Simulation netlist always created on subsequent runs.
Xilinx Answer #6996 : 2.1i Virtex PAR - FATAL_ERROR:Route:basrtsanity.c:241:1.1.2.2 - Process will terminate.
Xilinx Answer #6999 : 2.1i Virtex PAR - FATAL_ERROR:Route:xvkrtconn.c:116:1.1.2.4 - UNPLACED COMP ENCOUNTERED
Xilinx Answer #7000 : A2.1i: Synopsys Designware libraries compiled for 1998.02 and 1997.08
Xilinx Answer #7004 : 1.5i JTAG Programmer - ERROR:basut - The boundary-scan based 'program' operation is not supported
Xilinx Answer #7005 : Foundation 2.1i: Checkpoint Gate Simulation Control issues error when selecting NGD file.
Xilinx Answer #7006 : Foundation1.5is2,FPGAExpress3.1: How to get report of synthesis result in Foundation HDL macros
Xilinx Answer #7007 : FPGA Express: MAP ERROR:baste:26 - The TBUFs "X" and "Y" drive the same output signal
Xilinx Answer #7008 : 2.1i Virtex Map - Map may configure a BUFT driven by PWR/GND in a way that will not work in the hardware.
Xilinx Answer #7009 : 2.1i Install: Setup window not being activated after double-clicking on setup.exe; only first splash screen shown
Xilinx Answer #7013 : 2.1i; Timing Analyzer: Maximum Delay Path does not match Minimum Period value in Unconstrained section of Unconstrained Report
Xilinx Answer #7015 : Foundation 1.5is2 - error : cannot find pcmdos.pif make sure this file exists...
Xilinx Answer #7016 : 2.1i: NGDBUILD -causes Dr Watson on Windows NT 4.0 SP3 at Address: 0x780125b3
Xilinx Answer #7017 : WEBPACK: Can I use a VHDL or Verilog source file, or is the tool ABEL based?
Xilinx Answer #7022 : Virtex: Are there Virtex Development boards available?
Xilinx Answer #7024 : Foundation 2.1i: ERROR:basilisk:6 - Problem encountered invoking program "m1map".
Xilinx Answer #7025 : 2.1i Virtex PAR - ERROR:Place:1631, 1632 Could not find a legal placement for the following components....
Xilinx Answer #7029 : Foundation 2.1i: Missing speed grades for CPLD devices.
Xilinx Answer #7030 : NGDBUILD does not process all XNF files before it reads NCF file (NgdHelpers:14)
Xilinx Answer #7031 : ngdbuild 1.5isp2, 2.1i: basnb:79, basnu:93, basnu:115, Ngdhelper:312, Ngdhelper:335, Ngdbuild:79
Xilinx Answer #7034 : Virtex: Is it possible to remove Vccint whilst applying Vcco?
Xilinx Answer #7040 : COREGEN: How to cascade the Serial and Parallel ROM-based Correlators
Xilinx Answer #7042 : Foundation 2.1i: Missing speed grades for CPLD devices.
Xilinx Answer #7043 : Foundation 2.1i: Extra speed grades for CPLD devices.
Xilinx Answer #7048 : Foundation 2.1i: Path variable must be manually updated after installation
Xilinx Answer #7049 : 2.1i JTAG Programmer - Done does not go high when configuring 4000XL
Xilinx Answer #7050 : 2.1i: Constraints Editor: An application error has occured and ... Constraint_editor.exe
Xilinx Answer #7051 : FlexLM/Security - floating license for Computer names with spaces in them will not work,"Not a valid server host name"
Xilinx Answer #7052 : 2.1i Virtex PAR - Using the -k switch on Virtex designs may cause a Segmentation Fault/ Access Violation in PAR.
Xilinx Answer #7056 : COREGEN: How to generate a CORE Generator FIR filter with less than 6 taps
Xilinx Answer #7064 : 2.1i Virtex PAR - Router terminates with Segmentation fault during PWR/GND routing.
Xilinx Answer #7066 : ngdbuil: basts:167 could not find clk net ... referred to by timegroup
Xilinx Answer #7070 : NGDBuild/Virtex 2.1i: ERROR:NgdHelpers:312 - logical block "I_from_net_GND" of type "GND" is unexpanded
Xilinx Answer #7071 : 2.1i Ngdbuild- ngdbuild ignoring drive strength constraints attached to output nets
Xilinx Answer #7072 : 2.1i Virtex Map - Virtex mapper treats OBUF driving PU, PD, or KEEPER inconsistently.
Xilinx Answer #7074 : 2.1i Install: Startup splash screen appears, but then dissappears and install fails without errors
Xilinx Answer #7076 : NGDBUILD 2.1i: ERROR:basla:20 Launcher: virtex is not a valid PM name (ERROR basnb:64 could not initialize netlister)
Xilinx Answer #7077 : 2.1i Install: Setup Failed while processing the Environment updated.addtask
Xilinx Answer #7078 : 2.1i Virtex PAR - Placer ignores list constraint involving IOB.
Xilinx Answer #7082 : 2.1i: Timing Analyzer: Delay numbers not reported for pad to ifd/ofd to pad
Xilinx Answer #7083 : 1.5i/2.1i 4K Map - ERROR:OldMap:532 - Unable to obey design constraints which require the following symbols into a single CLB. . .
Xilinx Answer #7084 : V1.5 COREGEN: problems with Delay Element locking up and providing only 2 clock delays due to illegal state in LFSR
Xilinx Answer #7085 : 2.1i Spartan Par - Crashes with access violation when two bufgs are locked to same location
Xilinx Answer #7086 : 2.1i Virtex Map/PAR - Designs combining non-RLOC'd carry chains and macros may fail.
Xilinx Answer #7087 : Exemplar Leonardo Spectrum v1999.1c: ngdhelpers:312 - logical block of type GND is unexpanded
Xilinx Answer #7092 : HW-130: Version 4.5 and future versions do not suport DOS or Workstation platforms.
Xilinx Answer #7093 : 2.1i JTAGProgrammer: 4002XL support added in the latest Service Pack
Xilinx Answer #7095 : Xinfo 2.0: Self Diagnostic Tool to help debug/troubleshoot issues (i.e - Install, Env Variables, GUI's, etc...) - PC ONLY
Xilinx Answer #7097 : FPGA Express 3.x: Virtex/E flip flops are not merged into the IOB
Xilinx Answer #7105 : Mentor: pld_edif2tim gives Error: Unable to resolve reference "my_bus_7_0_" of type "portRef"
Xilinx Answer #7108 : LogiCORE PCI Virtex (v3.x): Are the Virtex Devices PCI compliant?
Xilinx Answer #7112 : Virtex SelectMAP configuration: Is D0 pin the MSB or LSB
Xilinx Answer #7118 : Foundation Simulator 2.1i: Warning 9218: LDNODE: (x_suh).IN - Unknown pin name
Xilinx Answer #7119 : V2.1i COREGEN, SYNPLICITY: CORE Generator does not write out a "/* synthesis black_box */ compiler directive to .VEO file for Synplicity Verilog designs
Xilinx Answer #7120 : Hardware Debugger M1/M2: Xchecker cannot bring D/P low to reconfigure the device. Reset the Target board to continue.
Xilinx Answer #7121 : 2.1i PAR - How to determine the amount of memory used by PAR (and other Xilinx applications).
Xilinx Answer #7123 : 2.1i Install: Solaris: setup failed whil processing the FileCopier.Readme
Xilinx Answer #7124 : 2.1i Virtex Map - A case has been seen where map does not pack CYMUX and XORCY with the register they drive.
Xilinx Answer #7127 : 2.1i INSTALL, COREGEN: "ERROR: Error opening preference file <install_dir>/coregen/preferences/coregen_<username>.prf"
Xilinx Answer #7128 : V2.1i COREGEN: Sine Cosine LUT module appears to be missing in CORE Generator tree
Xilinx Answer #7130 : 1.5is2: EPIC: Dismissing Carry Strings windows by double clicking on 'X' will delete all the Carry Stings information
Xilinx Answer #7131 : TRCE/Timing Analyzer 2.1i: 0 items analysed on OFFSET constraints in Virtex designs on ofd/ifds
Xilinx Answer #7139 : 1999 Databook: Alliance software does not ship with the hardware cables and demoboard
Xilinx Answer #7140 : FPGA Express 3.3: How to infer ROM for Virtex
Xilinx Answer #7141 : 2.1i Virtex PAR - FATAL_ERROR:Route:xvkrtconn.c:116:1.1.2.4 - UNPLACED COMP ENCOUNTERED
Xilinx Answer #7142 : 2.1i XC4000XL Map - FATAL_ERROR:OldMap:x4emamerge.c:2410:1.1.2.6 - Illegal merge detected
Xilinx Answer #7143 : V2.1i COREGEN, VIEWLOGIC: "ERROR: cleanUpSymbolFile: Could not read symbol file: <project_directory>\sym\<modulename>.1"
Xilinx Answer #7147 : 2.1i Virtex Map - Can any component drive the CLKIN input of a clkdll?
Xilinx Answer #7148 : V2.1i COREGEN, VIRTEX: Problems with synchronous control signal (SCLR, SINIT) HDL behavioral modelling in the LD-Based LATCH module
Xilinx Answer #7149 : V2.1i COREGEN, C_IP1: Known Issues in the C_IP1 Cores update
Xilinx Answer #7151 : 2.1i COREGEN, C_IP1, FOUNDATION: "Line: 3 Wrong number of fields BUS" on modules during symbol generation
Xilinx Answer #7152 : LogiCORE PCI64 Virtex (v3.x): Plugging a 64-bit card in a 32-bit slot
Xilinx Answer #7156 : 2.1i, 1.5i, 1.4 NGDBUILD, EDIF2NGD, COREGEN: Warning: basnu:74: invalid target package PQ240 (or BG256) ignored.
Xilinx Answer #7158 : FPGA Express: VHDL Error: Range 'U' to 'X' (or 'Z' to '-') not covered by choices. (VSS-838)
Xilinx Answer #7160 : FPGA Compiler, FPGA Express: What netlist formats are supported for Xilinx devices?
Xilinx Answer #7161 : Foundation 2.1i The PLC attribute for clbmap primitive not supported
Xilinx Answer #7167 : FPGAEditor 2.1i - BlockRAM initialization values are not stored after saving changes
Xilinx Answer #7172 : Virtex JTAG - How to perform a Readback Verify on the Virtex devices?
Xilinx Answer #7174 : Foundation 2.1i: Functional and timing simulation of the CLKDLL
Xilinx Answer #7175 : Foundation 2.1i: How to install additional device families.
Xilinx Answer #7176 : LogiCORE PCI: Base Address Registers (BAR's) and configuration accesses in a PCI system
Xilinx Answer #7180 : Virtex: Things to be careful with when converting 4K designs to Virtex
Xilinx Answer #7185 : 2.1i package files - The 40150xv BG432 package is incorrect
Xilinx Answer #7186 : 2.1i Virtex Bitgen - "WARNING:Bitgen:73 - Can't find arc ...."
Xilinx Answer #7187 : Foundation 2.1i install: FileCopier.AddCable error
Xilinx Answer #7188 : 2.1i JTAGProgrammer - Looks for the incorrect bsdl file for the 5215 and V800 HQ240.
Xilinx Answer #7192 : 2.1i LOGIBLOX/PROM FILE FORMATTER/TIMING ANALYZER: Bus error when launched on HP 10.20 platform
Xilinx Answer #7193 : Foundation Schematic - Macro created with incorrect pins from VHDL code
Xilinx Answer #7197 : Timespec constraints: UCF/NCF PERIOD constraints are not written correctly in the PCF file
Xilinx Answer #7201 : COREGEN, VIRTEX : Virtex BaseBLOX Cores released in the C_IP1 Cores update
Xilinx Answer #7209 : V2.1i, V1.5 LOGIBLOX: LogiBLOX online Help Index tab entries consistently put you on the wrong page
Xilinx Answer #7213 : 2.1i Map - FATAL_ERROR:Ncd:basncinfo.c:139:1.1.2.4 SiteParams are out of sync
Xilinx Answer #7215 : 2.1i Timing Analyzer: Running Custom Analysis Report after running Advanced Analysis Report produces the same report.
Xilinx Answer #7219 : 2.1i JTAG Programmer - operation INITIALIZE CHAIN gives incorrect device name
Xilinx Answer #7222 : 2.1i Virtex MAP Error:xvkpu - Unable to obey design constraints
Xilinx Answer #7223 : 2.1i Install: HP: No option given for network installation as with PC version
Xilinx Answer #7228 : 2.1i Virtex Map - Some pullup/pulldown/keeper configurations are not being handled properly.
Xilinx Answer #7233 : ngd2edif: What's the bus designator in the edif file produced by ngd2edif, and why is it buses don't have the designator when ngdanno run with the .ngm file
Xilinx Answer #7234 : 2.1i Hitop: - 9500XL Fitter report shows GND and NC as TIE on XC95288XL-BG256
Xilinx Answer #7235 : 2.1i: Constraints Editor: Spartan PQ208 Prohibit IO locations for config pins are incorrect
Xilinx Answer #7237 : V2.1i COREGEN, VIRTEX, FOUNDATION: Invalid EDIF with shorted nets produced for Virtex Dual & Single port Block memory on first iteration / Foundation simulator "duplicate net" errors
Xilinx Answer #7238 : 2.1i Install: Coregen: HP-UX 10.2 Error message containing Coregen.java:1506 and 'exception in thread "main"
Xilinx Answer #7239 : 2.1i 4000XL Map - Guided map creates a corrupted CLB configuration
Xilinx Answer #7240 : Foundation 2.1i, FPGA Express 3.2: Is it possible to infer signed arithmetic modules in VHDL or Verilog?
Xilinx Answer #7241 : 2.1i Design Manager: MPPR is producing the same results for each new MPPR revision
Xilinx Answer #7242 : FPGA Express inserts ILD for ILDX_1 instantiation
Xilinx Answer #7243 : 2.1i Virtex Map/PAR - Map and PAR issues related to Virtex Carry chains
Xilinx Answer #7245 : 2.1i 4KX* PAR - Application error has occured. Exception:Access Violation (0xc0000005), Address: 0x039313b9
Xilinx Answer #7248 : Foundation 2.1i Schematic: Warning: multiple drivers or sourceless/loadless nets detected.
Xilinx Answer #7249 : 2.1i 4KX* PAR - Dr Watson during routing. Access violation (0xc0000005), Address: 0x0024b0b1
Xilinx Answer #7250 : Foundation 2.1i Simulator: Memory write address exceeds defined memory bounds
Xilinx Answer #7251 : DataBook: Documentation error on p.6-166 of 1999 databook, in Table 9, It should not said 4000xla only.
Xilinx Answer #7261 : 2.1i Design Manager 2.1 - XPROJ directory is created with user permissions only
Xilinx Answer #7262 : FPGA Express: Is there an option to disable carry logic?
Xilinx Answer #7264 : 2.1i Virtex Map - exception: Access Violation (oxc0000005), address:ox00255920
Xilinx Answer #7267 : Foundation 2.1i Installer: setup.exe failed with error code 15
Xilinx Answer #7270 : JTAG - Mixed voltage JTAG chain considerations among E, XL, XV or 5V, 3.3V, 2.5V devices
Xilinx Answer #7271 : Synopsys Design Compiler / FPGA Compiler: Can't make an adder in Synopsys bigger than 48-bits
Xilinx Answer #7274 : Foundation 2.1i: Multimedia QuickStart: Director Player 6.0: This program requires at least 3MB of free virtual memory to run
Xilinx Answer #7277 : 2.1i Virtex Map - ERROR:xvkpu - Unable to obey design constraints ...
Xilinx Answer #7278 : Foundation/Alliance 2.1i Installer: Setup failed while processing the Unbundler.xc4000xla_85 task.
Xilinx Answer #7279 : 2.1i Virtex Map - Map drops inverter when FF pushed into IOB.
Xilinx Answer #7290 : 2.1i Virtex Map - IOB=true attribute is ingored for tri-state enable register in Virtex
Xilinx Answer #7291 : FPGA Express: BSCAN_VIRTEX is removed from the design without warning
Xilinx Answer #7296 : 2.1i 4KX* PAR - Prohibit constraint ignored
Xilinx Answer #7299 : 2.1i Virtex Map - Map: exception:0xc0000005 at 0x00245970
Xilinx Answer #7300 : LogiCORE PCI: Inserting initial latency in a target design
Xilinx Answer #7302 : 2.1i Install: Alliance 2.1i Release Notes: the_netscape_file.tar.gz is not found in Implementation Tools CD
Xilinx Answer #7303 : Foundation 2.1i:This application is not supported by WindowNT. Can not run 16bit applications.
Xilinx Answer #7307 : 2.1i Ngdbuild: KEEPER is not applied to design IO ports via UCF.
Xilinx Answer #7309 : FPGA Editor 2.1i: How to Show the attributes on multiple nets or components?
Xilinx Answer #7312 : Timing Analyzer 2.1i; 9500/XL: Custom Report for CPLD gives stack fault error (timingan.exe, mfc42.dll) or Process Exit Code 2
Xilinx Answer #7313 : Cable - Is it possible to use an extension on the Xilinx cables?
Xilinx Answer #7314 : 2.1i 9500/XL Hitop - Incorrect implementation of a <function> = VCC
Xilinx Answer #7316 : 2.1i Virtex PAR - Placer has been enhanced to use MAXSKEW preference to assign secondary global clock buffers for external clock nets.
Xilinx Answer #7317 : 2.1i SP1 - The 2.1i Service Pack 1 Update is due to become available on September 2.
Xilinx Answer #7318 : 2.1i 4KX* Bitgen - Some 4000x family devices won't configure via JTAG
Xilinx Answer #7319 : 2.1i Virtex JTAG Programmer - Reconfiguring without using the program pin requires shutdown sequence
Xilinx Answer #7321 : 2.1i Virtex Map - The Virtex packer is failing to process the local output directive properly.
Xilinx Answer #7322 : 2.1i Ngdanno - Virtex single and dual port RAM give setup violations for Physical Sim only.
Xilinx Answer #7323 : FPGA Express 3.x: Global Clock Buffer is inserted, ignoring DONT USE in Express Constraints Editor
Xilinx Answer #7324 : 2.1i Jtagpgmr on HP - Core dump when running Jtagpgmr from Dsgnmgr.
Xilinx Answer #7325 : 2.1i Virtex Map - Map creates bad .pcf constraints from floorplanner constraints.
Xilinx Answer #7326 : 2.1i SpartanXL - The CS280 packages are missing
Xilinx Answer #7327 : 2.1i - Updated Virtex Speed files are available in 2.1i Service Pack 1.
Xilinx Answer #7328 : 2.1i Design Manager - DM Overwrite Last Version does not work on win95/98 & WS
Xilinx Answer #7329 : 2.1i FPGA Editor - ERROR:Portability:90 - Command line error: Switch '-usedpin' is unexpected
Xilinx Answer #7330 : 2.1i XC4000XV Speed files - The 2.1i Service Pack Update contains Preliminary XC4000XV speed data.
Xilinx Answer #7331 : CONCEPT-HDL: GSR/GTS behavior does not simulate with RAMB4* Verilog models.
Xilinx Answer #7332 : 2.1i TRCE- Results different when -u switch is used.
Xilinx Answer #7333 : Virtex Configuration: How can the users enable the Pullups in the IOs during Virtex Configuration.
Xilinx Answer #7334 : 2.1i FPGA Editor - Busy cursors are not used on many long processes.
Xilinx Answer #7335 : 2.1i SpartanXL PAR - PAR fails to produce consistent results when running a cost table twice.
Xilinx Answer #7336 : 2.1i Ngdanno - Back annotated delay has 3.7ns added to tristate signal on an IOB.
Xilinx Answer #7337 : 2.1i 9500/XL: Hitop (CPLD Fitter) not fitting DFF--> INV --> OBUF correctly
Xilinx Answer #7338 : NGD2VER 2.1i SP1: - glbl.v has a different 'timescale from .v and .tv output of NGD2VER
Xilinx Answer #7339 : 2.1i Virtex Libraries - Updated Virtex XSI libraries with preliminary speeds -4 -5 will become available in 2.1i SP2.
Xilinx Answer #7340 : 2.1i TRCE - Paths are reported against the wrong timing constraint.
Xilinx Answer #7341 : 2.1i Virtex Speed Files - Missing Virtex pin-to-pin timing values cause overly optimistic delays
Xilinx Answer #7342 : 2.1i SpartanXL PAR - FATAL_ERROR:Route:basrtsanity.c:241:1.1.2.2 -Process will terminate.
Xilinx Answer #7343 : 2.1i General - Help -> About Project Manager has been enhanced to show service pack revision.
Xilinx Answer #7345 : 2.1i Virtex PAR - Placer leaves source pin of high fanout net unplaced, leading to router crash.
Xilinx Answer #7348 : 2.1i ChipViewer - Long invocation time of ChipViewer causes confusion to the users.
Xilinx Answer #7349 : 2.1i Virtex Map - Virtex mapper treats OBUF driving PU, PD, or KEEPER inconsistently.
Xilinx Answer #7350 : 2.1i PAR - PAR does not cleanup low-end results when running turns engine (ignores -s)
Xilinx Answer #7351 : 2.1i Ngdbuild - TNM_NET propagation thru DLL to no synchronous loads.
Xilinx Answer #7352 : 2.1i Spartanxl speed files - Updated speed files are available for -5 preliminary speed grades.
Xilinx Answer #7353 : Foundation 2.1i: Can not load Xilinx license dll
Xilinx Answer #7357 : 2.1i 4000 Map - ERROR:OldMap:56 - The LOC constraint "W2" (a MODE1 location) is not valid for OPAD symbol "$xx" which is being mapped to the following site type CLKIOB, FCLKIOB,IOB
Xilinx Answer #7358 : 2.1i Constraints Editor Can't Add Configuration Pins for FG676 & FG680
Xilinx Answer #7359 : 2.1i 4KX* Map - FATAL_ERROR:x4kma:x4kmagrclapse.c:3138:1.110.16.3
Xilinx Answer #7360 : 2.1i SPXL Map - GLUT to FFY connection uses external path
Xilinx Answer #7361 : Foundation 2.1i Schematic : Symbol Wizard writes bidir ports as output ports
Xilinx Answer #7362 : Foundation 2.1i Install: Setup failed with unexpected error
Xilinx Answer #7364 : 2.1i Virtex Map - Mapped design results in sourceless net leading to DRC errors.
Xilinx Answer #7372 : 2.1i Virtex PAR - PC only crash occurs after "Starting the placer".
Xilinx Answer #7377 : V2.1i, V1.5i LOGIBLOX, FOUNDATION: Why is the Logiblox menu option sometimes disabled within the Foundation Project Manager and HDL Editor menus?
Xilinx Answer #7378 : 1.5i/2.1i: Hierarchical constraints with dc2ncf are not supported
Xilinx Answer #7379 : EXEMPLAR 1999.1x: How do I set a slow slew rate when 'Fast Output Buffers' is selected?
Xilinx Answer #7382 : FPGA Express 3.2: Synopsys Internal Error, Abort at 219
Xilinx Answer #7383 : Virtex Configuration: How many loads can the configuration pin CCLK drive?
Xilinx Answer #7391 : C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier module "Set Overrides Clear" option behaves the same way as "Clear Overrides Set"
Xilinx Answer #7393 : C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier module latency does not match the 4K (XC4000) version of the core
Xilinx Answer #7395 : V2.1i COREGEN, C_IP2: Known Issues in the C_IP2 IP Update
Xilinx Answer #7396 : C_IP2, 2.1i COREGEN: Virtex Variable Parallel Multiplier "Combinatorial" and "Pipelined Registers" option interaction
Xilinx Answer #7397 : C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier optional pins appear in a Foundation symbol even when not requested
Xilinx Answer #7402 : Virtex CLKDLL: Will the CLKDLL lock if the input frequency is below 25Mhz, if not, what would the outputs of the CLKDLL be like.
Xilinx Answer #7406 : Foundation 2.1: Unexpected error when installing 2.1
Xilinx Answer #7407 : FPGA Express 3.2: Crashes (Dr. Watson) after "Force Update" project or chip
Xilinx Answer #7408 : 2.1i 4KX* Map - Map does not properly place floorplanned DPRAMs
Xilinx Answer #7409 : 2.1i COREGEN, FOUNDATION: Optional pins which are not requested still appear on the Foundation symbol for a CORE Generator Core
Xilinx Answer #7411 : FPGA Express: Express does not know about dedicated clock pads
Xilinx Answer #7412 : Virtex Configuration: Initialization timing for SelectMap (CS/ assertion)
Xilinx Answer #7413 : LogiCORE PCI: The PCI master may stop bursting data after 2 clocks during simulation
Xilinx Answer #7414 : 2.1i JTAG Programmer - SVF SIR instruction with TDO value comparison has incorrect MASK
Xilinx Answer #7417 : Foundation 2.1: LMACS Errors when attempting to open a new project
Xilinx Answer #7418 : A2.1i: Using Synopsys Design Compiler or FPGA Compiler to target Virtex-E
Xilinx Answer #7419 : How to set the CLKDV_DIVIDE property for the CLKDLL
Xilinx Answer #7426 : Virtex: Configuration -- DONE goes high, but IO never goes active
Xilinx Answer #7427 : FPGA Express 3.x: NCF file will not work with XNF files and "Preserve Hierarchy" (NgdHelpers:14)
Xilinx Answer #7428 : 2.1i Userware: xm.laroux.as virus found within $XILINX/userware/virtex_arch.zip
Xilinx Answer #7432 : 2.1i: FPGA Editor:"Save as" command corrupts pcf file.
Xilinx Answer #7433 : 2.1i COREGEN, ACTIVE-VHDL: Issues compiling the CORE Generator 2.1i VHDL models for the Active HDL simulator
Xilinx Answer #7434 : Foundation 2.1i install/unistall: Foundation installer hangs or issues warning at 86%
Xilinx Answer #7435 : NGD2VER/NGD2VHDL: ERROR:NetListWriters:61 - XILINX environment variable is not set.
Xilinx Answer #7436 : LogiCORE PCI: XPCI Core Generator Server transaction failed. Failure cause: 1097
Xilinx Answer #7438 : OrCad Express v9.x does not interface correctly with Xilinx A2.1 tools for XC9500 CPLDs
Xilinx Answer #7440 : 2.1i Install: Documentation always uses default browser
Xilinx Answer #7441 : V2.1i COREGEN, C_IP2: "ERROR: Unable to find library for core Sine-Cosine_Look-Up_Table|xilinx|xc4000_all"
Xilinx Answer #7448 : 2.1i Floorplanner: Virtex - Crashes due to stack overflow (PC only).
Xilinx Answer #7450 : 2.1i Install: Foundation - "The standalone installer \installs\synsynth\setup.exe failed with error code XX.XXX. Install will continue."
Xilinx Answer #7453 : 2.1i Virtex Map - Map hangs at "Reading NGD file ..." on XCV1000 design
Xilinx Answer #7456 : 2.1i COREGEN: Text in .VEO and .VHO template files is merged into a single line when read in Windows Notepad
Xilinx Answer #7457 : 2.1i 9500/XL Hitop : "Warning NL_PRIMPIN has no net name. The pin is ignored."
Xilinx Answer #7461 : 2.1i COREGEN, VIEWLOGIC: CORE Generator writes out Viewlogic symbol pins in reverse order for Coregen module
Xilinx Answer #7462 : Viewlogic VHDL2SYM syntax
Xilinx Answer #7465 : 2.1i COREGEN: Recommended location of destination directory for compiled Verilog behavioral models
Xilinx Answer #7466 : 2.1i Virtex Map - Mapper creates unroutable connection when F6mux is driven by two F5muxes.
Xilinx Answer #7467 : 2.1i Alliance : Service Pack Install - error message when installing "setup: java: not found"
Xilinx Answer #7468 : 2.1i 3000A LCA2NCD - Bitgen of converted 3000A design results in different bit file than makebits
Xilinx Answer #7470 : XSI Libraries 2.1i: Bidirectional I/O has extra inversion inferred (IOBUF_N)
Xilinx Answer #7471 : 2.1i SpartanXL PAR - Crash caused by design containing signals with no pins.
Xilinx Answer #7472 : PROM XC18V00: What is the function of the CF# pin.
Xilinx Answer #7473 : XC1800: The use of the CF# pin in SO20 and PC20 package is limited
Xilinx Answer #7478 : 2.1i 4K Map - Map can not combine dual port ram with registers into the same CLB when local set /reset signal used.
Xilinx Answer #7480 : Floorplanner 2.1is1 - Locked pin in UCF file are ignored if design is floorplanned
Xilinx Answer #7481 : 2.1i JTAG Programmer - File does not exist: <path>/filename.bsd
Xilinx Answer #7483 : 2.1i TRCE Spartan\XL: Input hold time using Primary Clock and IFF is non-zero even with delay
Xilinx Answer #7487 : 2.1i SP1 Virtex Map -FATAL_ERROR:xvkpk:xvkpkslice.c:146:1.30
Xilinx Answer #7489 : 2.1i V150-FG456 - PAD report does not match datasheets
Xilinx Answer #7494 : FPGA Editor 2.1i: Radio buttons are blank when selected
Xilinx Answer #7495 : Foundation Simulator 2.1i: Netlist Fatal error. 9230: DUMMY cannot read pin #.
Xilinx Answer #7497 : FPGA Express 3.x: Express inverting load/clock signal for 4000/Spartan input latches
Xilinx Answer #7498 : 2.1i Install: Foundation. Error: "XIE internal error 101" after installing F2.1i
Xilinx Answer #7503 : 2.1i Par:placement pass 2 FATAL_ERROR:Utilities:basagconjgradient.c:202:1.1.4.2 - CG SOLVER: residual after solving
Xilinx Answer #7504 : CoolRunner/XPLA Professional: What can be done to get a better fit if a design does not fit into the selected device?
Xilinx Answer #7505 : CoolRunner/XPLA Software: Which third party tool vendors provide support for the CoolRunner/XPLA devices?
Xilinx Answer #7506 : CoolRunner/XPLA Professional: Why does the print out of pin editor look incorrect?
Xilinx Answer #7507 : CoolRunner/XPLA Professional Simulator: What does the "Bitmap allocation error. Possible too many signals" mean?
Xilinx Answer #7509 : 2.1i Virtex Map: FATAL_ERROR:xvkpu:xvkpucarry.c:604:1.23 - The carry multiplexer U_RDCONT/U_OUTCONT/add_102/plus/plus/A_CY_12 has an unconnected output
Xilinx Answer #7510 : Floorplanner 2.1i; VirtexE: Floorplanner crashes when saving a VirtexE400 or greater
Xilinx Answer #7511 : LogiCORE PCI: Updating HOT II card from v1 to v2 after accidental erasure of the Configuration Flash Memory
Xilinx Answer #7513 : CoolRunner/XPLA Professional Simulator: Why doesn't the simulator use the *.scl file when a signal is not recognized?
Xilinx Answer #7515 : CoolRunner/XPLA Professional: What is the recommended procedure to properly install XPLA Professional software?
Xilinx Answer #7516 : CoolRunner/XPLA Professional: How to use the control files with the CoolRunner/XPLA Products?
Xilinx Answer #7517 : 2.1i Documentation - How to read Docscan off the CD
Xilinx Answer #7519 : CoolRunner/XPLA Professional: What are the main software features of the XPLA Professional software?
Xilinx Answer #7522 : XPLA Professional: Targeting an Altera design to a CoolRunner device.
Xilinx Answer #7523 : XPLA Professional: Implementing a latch in a CoolRunner?
Xilinx Answer #7524 : XPLA Professional: Timing simulation gives different results than simulation with the *.vho or *.vo file.
Xilinx Answer #7525 : XPLA Professional: GUI has incorrect graphics and cut off messages.
Xilinx Answer #7526 : XPLA PC-ISP Programmer: GUI has incorrect graphics and cut off messages.
Xilinx Answer #7527 : XPLA Professional: Fitter continues when more PLA terms are required than resources allow.
Xilinx Answer #7528 : XPLA Professional: Compiler fails when tri-state buffers are defined as buried nodes.
Xilinx Answer #7529 : XPLA Professional: Fitter errors when reset signal cannot be assigned to the global reset pin on XPLA2 devices.
Xilinx Answer #7530 : XPLA Professional: How to estimated Icc for a CoolRunner design.
Xilinx Answer #7531 : XPLA Professional: SPICE models for the CoolRunner family.
Xilinx Answer #7532 : XPLA Professional: How to force a value onto internal nodes during simulation?
Xilinx Answer #7533 : XPLA Professional: What does the XPLA Property "TRI-STATE" do?
Xilinx Answer #7537 : XPLA Professional: Creating a soft flip-flop with Q-bar output.
Xilinx Answer #7538 : XPLA Professional: Sequence of statements in a *.scl file.
Xilinx Answer #7539 : 2.1i COREGEN: Missing MIF file for Virtex Single and Dual Port Block RAM modules
Xilinx Answer #7540 : XPLA Professional: Creating equations in the form of a *.phd or *.phj file from a *.jed file.
Xilinx Answer #7541 : XPLA Professional: Description of a node in the CoolRunner parts.
Xilinx Answer #7542 : XPLA Professional: Creating symbols in Schematic Capture for PHDL or Verilog modules.
Xilinx Answer #7543 : XPLA Professional: Pin reassignment.
Xilinx Answer #7544 : XPLA Professional: Timing driven synthesis.
Xilinx Answer #7545 : XPLA Professional: Simultaneous reset and preset.
Xilinx Answer #7546 : XPLA Professional: XPLA Designer XL.
Xilinx Answer #7547 : XPLA Professional: Obtaining XPLA Professional.
Xilinx Answer #7548 : XPLA Professional: Designing into a CoolRunner device using VHDL or Verilog?
Xilinx Answer #7550 : XPLA Professional: Schematic capture support.
Xilinx Answer #7551 : XPLA Professional: PHDL support.
Xilinx Answer #7552 : XPLA Professional: CoolRunner integrated into WebPACK.
Xilinx Answer #7553 : XPLA Professional: Support until CoolRunner is supported in Xilinx software.
Xilinx Answer #7554 : XPLA Professional: Estimated Icc for a CoolRunner design from a Third party *.jed file.
Xilinx Answer #7555 : XPLA Professional: Simulator runs for long periods of time.
Xilinx Answer #7558 : Foundation 2.1i: The standalone installer g:\installs\synsynth\setup.exe failed with error code 65,455
Xilinx Answer #7560 : XPLA Professional: Generating a simulator clock with a delayed starting time.
Xilinx Answer #7561 : XPLA Professional: Attribute ISTYPE INVERT.
Xilinx Answer #7562 : XPLA Professional: Forcing a design into a specific logic block.
Xilinx Answer #7563 : XPLA Professional: XPLA Properties.
Xilinx Answer #7564 : XPLA Professional: Properties for nodes not at the top level of a schematic.
Xilinx Answer #7565 : XPLA PC-ISP Programmer: Generating ATE vectors.
Xilinx Answer #7566 : XPLA PC-ISP Programmer: How to load a JEDEC file, versus a JCD file?
Xilinx Answer #7567 : XPLA PC-ISP Programmer: Supported operating system.
Xilinx Answer #7568 : XPLA PC-ISP Programmer: Programmer cannot find or recognize a file
Xilinx Answer #7569 : XPLA PC-ISP Programmer: Can not find ISP Cable or Board.
Xilinx Answer #7570 : XPLA PC-ISP Programmer: Debug tips on custom built download cables
Xilinx Answer #7571 : XPLA PC-ISP Programmer: Accessing non-CoolRunner devices.
Xilinx Answer #7572 : 2.1i COREGEN, C_IP2: Incorrect latency values reported by Virtex Parallel Multiplier GUI
Xilinx Answer #7573 : XPLA PC-ISP Programmer: CoolRunner does not program when detected in the chain.
Xilinx Answer #7574 : XPLA PC-ISP Programmer: New parts do not program via ISP in a known good system.
Xilinx Answer #7575 : XPLA PC-ISP Programmer: ATE vector clock speed for TCK.
Xilinx Answer #7576 : XPLA PC-ISP Programmer: Generating vectors for Microcontroller use.
Xilinx Answer #7577 : XPLA PC-ISP Programmer: Generating binary files for JEDEC programming.
Xilinx Answer #7578 : 2.1i COREGEN, C_IP1, C_IP2, C_IP3: Version of generated module does not match version number in the corresponding datasheet
Xilinx Answer #7579 : XPLA PC-ISP Programmer: XPLA1 ISP Proto Board CPLD does not function improperly.
Xilinx Answer #7580 : XPLA PC-ISP Programmer: Message "driver vicprt11 not found" when software finds the parts on the board.
Xilinx Answer #7581 : XPLA PC-ISP Programmer: Large amounts of current consumed during a "Verify".
Xilinx Answer #7582 : XPLA PC-ISP Programmer: Generating MCS files for the XCR3960/XCR3320?
Xilinx Answer #7583 : XPLA PC-ISP Programmer: Documentation for the ISP cable & header.
Xilinx Answer #7585 : XPLA PC-ISP Programmer: Software is used to program the CoolRunner ISP CPLDs.
Xilinx Answer #7586 : XPLA PC-ISP Programmer: How to obtain the CoolRunner XPLA PC-ISP Programmer software.
Xilinx Answer #7587 : XPLA PC-ISP Programmer: Which download cable is needed to program an ISP CoolRunner CPLD.
Xilinx Answer #7588 : PC-ISP Programmer: What cable should be used with the CoolRunner ISP Programmer?
Xilinx Answer #7590 : Third Party Tool Flow: Third party tool flows for the Coolrunner Product
Xilinx Answer #7592 : XPLA CoolRunner Programmer: Programming the XCRx032-CS or XCRx032-AS VQ44 type parts.
Xilinx Answer #7593 : XPLA Architecture: JTAG pins with internal weak pull-up/down resistors.
Xilinx Answer #7594 : XPLA Architecture: Which CoolRunner products are pin compatible with Altera products?
Xilinx Answer #7595 : XPLA Architecture: Currently offered CoolRunners
Xilinx Answer #7596 : XPLA Architecture: Applying signals to the CoolRunner's I/Os before power is applied.
Xilinx Answer #7597 : XPLA Architecture: Fast Zero Power or FZP.
Xilinx Answer #7598 : XPLA Architecture: Differences between CPLDs and FPGAs.
Xilinx Answer #7599 : XPLA Architecture: Differences between PALs and PLAs.
Xilinx Answer #7600 : XPLA Architecture: CoolRunners with internal terminations on the I/O.
Xilinx Answer #7601 : XPLA Architecture: 5V tolerant CoolRunners
Xilinx Answer #7602 : XPLA Architecture: Fast Zero Power FZP parts drawing too much current.
Xilinx Answer #7603 : XPLA Architecture: Assembly locations of CoolRunner devices.
Xilinx Answer #7604 : XPLA Architecture: CoolRunners and internal weak pull-up resistors.
Xilinx Answer #7605 : XPLA 22V10: JEDEC compatibility of the XCR22V10.
Xilinx Answer #7606 : XPLA 22V10: FZP and the 22V10.
Xilinx Answer #7607 : XPLA 22V10: Resetting individual registers on the 22V10.
Xilinx Answer #7608 : XPLA 22V10: Programmable clock polarity in the 22V10.
Xilinx Answer #7609 : XPLA 22V10: Is ISP supported in the XCR22V10?
Xilinx Answer #7610 : XPLA 22V10: Asynchronous resets in a 22V10.
Xilinx Answer #7611 : XPLA 22V10: Asynchronous preset in the 22V10
Xilinx Answer #7612 : XPLA 22V10: Clocking resources in the 22V10.
Xilinx Answer #7613 : XPLA 22V10: Output enable resources in the 22V10.
Xilinx Answer #7614 : XPLA 22V10: Active polarity for output enable, asynchronous reset and synchronous preset of the 22V10.
Xilinx Answer #7615 : XPLA 22V10: Power up initial state of the 22V10.
Xilinx Answer #7616 : XPLA 22V10: Complementary outputs in the 22V10.
Xilinx Answer #7617 : XPLA 22V10: Program and erase cycle capability of the XCR22V10.
Xilinx Answer #7618 : XPLA 22V10: User signature area UES of the 22V10.
Xilinx Answer #7619 : XPLA1: Slew rate control on the outputs.
Xilinx Answer #7620 : XPLA1: Transparent latch in macrocells.
Xilinx Answer #7621 : XPLA1: Recommended decoupling.
Xilinx Answer #7622 : XPLA1: ZIA fan-ins to each logic block.
Xilinx Answer #7623 : Foundation Express 2.1i, SpartanXL: The CS144 and CS280 packages are missing in the device list
Xilinx Answer #7627 : XPLA-PC-ISP :Error 02 - Write Registry failed, You may not be able to access parallel port.
Xilinx Answer #7628 : 2.1i Virtex PAR: par.exe, exception:access violation (0x0000005), address: 0x05f07efd
Xilinx Answer #7631 : XPLA1: Number of macrocells in a logic block and presence of a PAL and PLA.
Xilinx Answer #7632 : XPLA1: Number of product available per macrocell.
Xilinx Answer #7633 : XPLA1: Clock resources available
Xilinx Answer #7634 : XPLA Professional: Where can you download the workstation version of the XPLA Professional software?
Xilinx Answer #7635 : XPLA Professional: Where is the XPLA Professional Users Manual?
Xilinx Answer #7636 : XPLA Professional: Schematic Capture library manual.
Xilinx Answer #7637 : XPLA1: CoolRunner startup current or high current demands.
Xilinx Answer #7638 : 2.1i Virtex Map - Pack of two RAMs into one slice fails with incorrect message.
Xilinx Answer #7639 : XPLA1: Hysterisis on inputs or clock pins.
Xilinx Answer #7640 : XPLA1: The XPLA fitter does not allow a pins associated with an asynchronous clock to be used as a standard I/O.L
Xilinx Answer #7641 : XPLA1: Internal pull ups or pull downs.
Xilinx Answer #7642 : XPLA1: What is the active signal polarity for Reset / Preset / Output Enable / Global Tri-State?
Xilinx Answer #7643 : XPLA1: Can the XPLA1 implement asynchronous clocks?
Xilinx Answer #7644 : XPLA1: Fitter error when exceeding maximum number of clocks.
Xilinx Answer #7645 : XPLA Professional: Version 3.31 ignores the pin assignments in a PAF file that was generated in the previous version.
Xilinx Answer #7646 : XPLA1: Availability of inverted outputs (Q!).
Xilinx Answer #7647 : XPLA1: Initial state of registers upon power up.
Xilinx Answer #7648 : XPLA1: Characteristics of I/O's during power up/down.
Xilinx Answer #7649 : XPLA1: Which pins require termination on the Coolrunner devices?
Xilinx Answer #7650 : XPLA1: Internally created asynchronous global clocks disable pins for use as inputs.
Xilinx Answer #7651 : XPLA2: Are the XPLA2 devices SRAM-based or EEPROM-based?
Xilinx Answer #7652 : XPLA2: Configuration modes of the XPLA2 devices.
Xilinx Answer #7653 : XPLA2: Size of download file and amount of device memory space needed for configuration.
Xilinx Answer #7654 : XPLA2: Utilizing the hardware XOR.
Xilinx Answer #7655 : XPLA2: Grouping signals in a fast module.
Xilinx Answer #7656 : XPLA2: How to use the global clocks, global reset, and global tri-states in the XPLA2?
Xilinx Answer #7657 : XPLA2: JTAG programming.
Xilinx Answer #7658 : XPLA2: Available devices and packages.
Xilinx Answer #7659 : XPLA2: Supported by XPLA Professional.
Xilinx Answer #7660 : XPLA2: Reserving device configuration pins using the fitter.
Xilinx Answer #7661 : XPLA2: Configuration PROMs supported.
Xilinx Answer #7662 : XPLA2: Length of time for configuration or download.
Xilinx Answer #7663 : XPLA2: Daisy-chain for configuration.
Xilinx Answer #7664 : XPLA2: Fast modules.
Xilinx Answer #7665 : XPLA2: Delay time through the Global ZIA.
Xilinx Answer #7666 : XPLA2: Fan-in and fan-out size of a fast module to the Global ZIA.
Xilinx Answer #7667 : XPLA2: Fan-in size from the local ZIA to each logic block.
Xilinx Answer #7668 : XPLA2: Number of macrocells in a logic block presence of PAL and PLA.
Xilinx Answer #7669 : XPLA2: Number of product terms per macrocell.
Xilinx Answer #7670 : XPLA2: Usefulness of the hardwired XOR.
Xilinx Answer #7671 : XPLA2: Timing delays associated with the XOR.
Xilinx Answer #7672 : XPLA2: Available number of I/O pins per fast module?
Xilinx Answer #7673 : XPLA Logistics: Future of the existing CoolRunner devices at Xilinx
Xilinx Answer #7675 : XPLA Logistics: CoolRunner web page location.
Xilinx Answer #7676 : XPLA Logistics: CoolRunner data sheet location.
Xilinx Answer #7677 : XPLA Logistics: Technical help on CoolRunner products.
Xilinx Answer #7678 : XPLA Logistics: Future support of the CoolRunner software.
Xilinx Answer #7680 : Foundation 2.1i simulation: Error- Bus Conflicts during Foundations simulation, while simulating multiplexer with tri-stated buffers
Xilinx Answer #7685 : 2.1i Virtex Map - Pack Error: MULT_AND symbol X must be connected to ...
Xilinx Answer #7695 : XPLA Architecture: Weak pull-up resistors for CoolRunner JTAG daisy chain.
Xilinx Answer #7696 : LogiCORE PCI 4000: List of the nets that should be guided by PAR for a 4062XLA
Xilinx Answer #7697 : XPLA Professional: Differences between ABEL and PHDL.
Xilinx Answer #7699 : F2.1i Schematic Editor: How to add PWR and GND symbols now that the "Power Symbol" button has gone.
Xilinx Answer #7700 : 2.1i ngdanno warning : ngdexpander : 5 - STARTUP symbol... can be ignored
Xilinx Answer #7702 : Virtex: What's the factory_JF factor on CLKDLL
Xilinx Answer #7703 : TRCE/Timing Analyzer 2.1i: Clock DLLs with period constraints appear in the reports as if they are not constrained
Xilinx Answer #7706 : Bitgen M1/M2: Why is there no -t (tie down unused interconnect) or -n (write out tied ncd) for Virtex?
Xilinx Answer #7707 : XPLA Professional: Y2K readiness
Xilinx Answer #7709 : 2.1i Virtex Map - MAP uses the incorrect JF setting for a CLKDLLHF
Xilinx Answer #7710 : 2.1i: Problems printing on Solaris
Xilinx Answer #7711 : 2.1i COREGEN, C_IP2: "Shrink method not supported" or "ERROR: Could not load/define class file xxxxxx" / "ERROR locating library "
Xilinx Answer #7713 : FPGA Editor 2.1i: Dr. Watson error - Access violation (0xc0000005), Address 0x003652e0 (Edit CLB/IOB/Slice & Save)
Xilinx Answer #7714 : 2.1i: Installation: out of memory
Xilinx Answer #7715 : FPGA Editor 2.1i: Exits when routing a net with unplaced comps
Xilinx Answer #7717 : FPGA Editor 2.1i: Sorting listview column with popup menu doesn't work for the "Name" column
Xilinx Answer #7718 : FPGA Editor 2.1i: Dr. Watson/Core dump when exiting after using Trace.
Xilinx Answer #7721 : 2.1i Ngdanno: Constants become hanging nets in back-annotated HDL file causing unknown states in timing simulation
Xilinx Answer #7727 : FPGA Express 3.3: Instantiated IFDX/IFDXI or OFDX/OFDXI get written to netlist as IFD or OFD
Xilinx Answer #7728 : 2.1i Virtex Map - The default input path delay element usage is being changed.
Xilinx Answer #7731 : 2.1i Virtex Map - Map errors out due to invalid trimming of OBUFT control signal
Xilinx Answer #7732 : Virtex Configuration: Can devices be daisy-chained in SelectMAP mode?
Xilinx Answer #7733 : 2.1i Virtex Map - Unable to pack the register xxx because of connectivity restrictions.
Xilinx Answer #7734 : 2.1i Virtex PAR - The .par results file reports incorrect number of logic levels
Xilinx Answer #7736 : 2.1i Package Files - Incorrect location for Spartan40XL BG256 DONE pin specified in the pad report.
Xilinx Answer #7738 : Virtex-E JTAG - IO bank voltages in Virtex and Virtex-E JTAG pins act differently
Xilinx Answer #7745 : 2.1i PAR - Will Multiple Processors Speed up PAR times?
Xilinx Answer #7748 : 2.1i: Timing: No OFF->PAD paths in the data sheet style report
Xilinx Answer #7749 : Foundation Simulator 2.1i: Functional Simulation works with script file but Timing Simulation does not
Xilinx Answer #7757 : Foundation 2.1i: Unspecified UCF file used for current revision in Project Manager
Xilinx Answer #7758 : FPGA Express 3.3, NCF: ERROR:TSDatabase:19 ...No TNM, TPSYNC or user group named "nco1_N214" is defined
Xilinx Answer #7759 : 2.1i COREGEN, RAM, PC: CORE Generator does not respond / appears to hang when you try to generate/customize a module
Xilinx Answer #7760 : 2.1i Hitop - Hitop (CPLD Fitter) uses SLOW slew when routing internal BUFG net through GTS pin
Xilinx Answer #7762 : Foundation 2.1i: Installation of the design entry tools failed with error code -8
Xilinx Answer #7763 : PromGen 2.1i: Parallel cable doesn't complete configuration with Virtex chains.
Xilinx Answer #7766 : 2.1i Virtex PAR - PAD report does not show usage of VREF pins on Virtex devices, whether or not they are used
Xilinx Answer #7770 : PROM XC18V00: How to program an 1800 series prom with the JTAG programmer
Xilinx Answer #7771 : Virtex Configuration: Virtex devices do not pass anything out on DOUT pin during configuration
Xilinx Answer #7773 : How do I convert a Foundation 1.4 project for use in 2.1i?
Xilinx Answer #7774 : XPLA Professional: How to enable/disable JTAG pins on ISP parts when using Schematic Capture?
Xilinx Answer #7775 : 2.1i Foundation - LOCKED signal does not go high on CLKDLL during Timing Simulation
Xilinx Answer #7778 : XPLA : Warning - wired or in net = <signalname>
Xilinx Answer #7779 : LogiCORE PCI: Simulating the LogiCORE PCI interface in VHDL causes some back-end signals to go unknown
Xilinx Answer #7784 : 2.1i COREGEN USER GUIDE: Errata sheet
Xilinx Answer #7786 : FPGA Express 3.3.1: Do not use this version of Express with Foundation 2.1i
Xilinx Answer #7788 : 2.1i PAR - S40XLPQ240-5 pad report does not match data book
Xilinx Answer #7792 : Virtex CLKDLL timing simulation in MTI: WARNING[1]:No default binding for component : "x_clkdll". ( Generic "tperiod_clkin" is not on the entity)
Xilinx Answer #7794 : FPGA Editor 2.1i CS2: Selecting a Path in the List window does not select the path in the Array window.
Xilinx Answer #7795 : 2.1i 4K* Map - Packing error fails to list the comps involved.
Xilinx Answer #7796 : XPLA: What are the IN0, IN1, IN2, IN3 pins on a Coolrunner device?
Xilinx Answer #7797 : 2.1i:Prom File Formatter - The size of your PROM is too large for the device format you have chosen
Xilinx Answer #7799 : 2.1i: 9500/XL: Hitop: CPLD Fitter gives unexpected error - "zsplit.c:324"
Xilinx Answer #7803 : Virtex Readback/ XAPP138: New equation for calculating readback bit positions
Xilinx Answer #7804 : MODELSIM (MTI): How to save waveform results?
Xilinx Answer #7810 : XPLA Professional: Functional simulation works but timing simulation yields unknown outputs
Xilinx Answer #7812 : FPGA Express 3.x: Address lines unconnected when SRL16 components are instantiated (FPGA-CHECK-7)
Xilinx Answer #7813 : 2.1i Virtex PAR - Router has difficulty connecting Block RAM pins
Xilinx Answer #7816 : Virtex CLKDLL: 2 CLKDLLs cascaded together could cause the second CLKDLL's outputs invalid
Xilinx Answer #7817 : 2.1i COREGEN: "ERROR: Error locating library for class" after installing IP update
Xilinx Answer #7819 : 4000E/X Configuration: In master mode, how many CCLKs are given after DONE goes high?
Xilinx Answer #7820 : FPGA Configuration: What is the maximum time PROG can be held low to delay configuration?
Xilinx Answer #7821 : Virtex SSO: The power/ground pair numbers for various Virtex devices and packages.
Xilinx Answer #7822 : How to infer SRL16 for Virtex/E devices in HDL (Verilog/VHDL)? (in EXEMPLAR and SYNPLIFY)
Xilinx Answer #7825 : 2.1i JTAG Programmer - JTAGPGMR: The program has performed an illegal operation and will be shut down.
Xilinx Answer #7827 : 2.1i PAR - PAR and TRCE report different numbers for the same routing.
Xilinx Answer #7832 : PROM XC18V00: Pins not described in the datasheet are no connects
Xilinx Answer #7833 : SYNPLIFY: How to infer SRL16 in Virtex/E design?
Xilinx Answer #7841 : 2.1i Virtex Map - Application Error crash occurs when loading NGD file. Design contains Pullups on some inputs.
Xilinx Answer #7843 : Virtex: How to pull the IOs to 5V with external Pullups
Xilinx Answer #7844 : Virtex-E IBIS models -- Can Virtex IBIS models be used?
Xilinx Answer #7845 : XPLA Professional: What do the CoolRunner net names X_#_ stand for?
Xilinx Answer #7847 : SYNPLIFY 5.2.2a: The date on this machine appears to have been set back!
Xilinx Answer #7848 : XPLA Professional: IBIS models are not available for the CoolRunner products
Xilinx Answer #7852 : Virtex CLKDLL: How to make sure the DONE does not go high until the CLKDLL has been locked
Xilinx Answer #7854 : 2.1i 4000XL Map/Fplan - Constrain from placement gets tripped up by Map route-thru.
Xilinx Answer #7856 : Viewlogic VHDL simulation:How to simulate Xilinx Virtex primitives (e.g. ramb4_s4)
Xilinx Answer #7859 : 2.1i COREGEN VERILOG, VHDL: How to extract the CORE Generator Verilog and VHDL behavioral simulation models
Xilinx Answer #7860 : Virtex-E NGDbuild error on LVPECL and LVCMOS18 IOSTANDRD: ERROR:NgdHelpers:33 - Invalid UCF/NCF file entry value "LVCMOS1" ...
Xilinx Answer #7861 : 2.1i COREGEN: "ERROR: Duplicate core resource"
Xilinx Answer #7867 : 2.1i COREGEN, BLOCK RAM: "Error:unable to open file for memory initialization: MIF file - binary error xx"
Xilinx Answer #7868 : 2.1i 4KX* Map - ERROR : DesignRules: 207 - Blockcheck: The pin "O" on comp (mapped physical logic cell) "inst_name" is configured to be used but has no signal attached to it.
Xilinx Answer #7879 : F2.1i XABEL: Internal Error 0001: assert event at line 359 in file "Z:\Lib\tsokit\TSOCELL\TSO_SIG.C"
Xilinx Answer #7880 : Virtex-E: Are the Virtex-E I/O pins 5V compatible?
Xilinx Answer #7884 : XPLA Professional Documentation: XCR5128 (Quad Flat Pack 128) Pinout in the XPLA Professional Users Manual is incorrect.
Xilinx Answer #7885 : 2.1i COREGEN: FOUNDATION: ERROR: \path\<project_name>.pdf does not exist or is not readable
Xilinx Answer #7887 : NGD2VER: False setup violation on X_FF instance immediately after time 0
Xilinx Answer #7888 : 2.1i Virtex Map - Eligible flop is not considered for input IOB merge.
Xilinx Answer #7891 : Virtex Configuration: How do you know a device is synchronized (sync word is loaded)?
Xilinx Answer #7895 : 2.1i COREGEN, C_IP3: Known Issues in the C_IP3 IP Update
Xilinx Answer #7896 : 2.1i COREGEN, C_IP3: Distributed Memory module only allows default initialization values of "0" using the MIF file
Xilinx Answer #7897 : 2.1i COREGEN, C_IP3: Error in COUNTER HDL behavioral model when COUNT BY VARIABLE and COUNT TO VALUE = "MAX" are selected
Xilinx Answer #7901 : 2.1i Foundation: ERROR:NgdBuild:335 - Line number 1: Syntax error when using Spartan-II
Xilinx Answer #7905 : 2.1i 4K Map - Map does not support the use of three external inputs to an HLUT.
Xilinx Answer #7906 : 2.1i COREGEN, C_IP3: MAP: "ERROR:xvkpu - Unable to obey design constraints" / Distributed Memory Cores may fail in MAP
Xilinx Answer #7908 : 2.1i COREGEN: Backspace/delete keys do not appear to work in module customization GUI text boxes on Solaris 5.6
Xilinx Answer #7909 : 2.1i COREGEN: Incorrect data written to Virtex Block RAM in VHDL behavioral simulation / model has incorrect timing on address and data lines
Xilinx Answer #7911 : FPGA Editor 2.1i: When routing Probes, It appears to freeze, Not Responding, takes a long time
Xilinx Answer #7915 : MODELSIM-XE (MTI): How do to obtain it? When is it available?
Xilinx Answer #7924 : 2.1i COREGEN, C_IP3, Distributed Memory: Customization GUI does not indicate what legal data width and depth ranges are
Xilinx Answer #7929 : EXEMPLAR:How to infer Virtex Block RAM in HDL? (Verilog/VHDL)
Xilinx Answer #7932 : XPLA Professional: Where can I find a CoolRunner Libraries Guide?
Xilinx Answer #7937 : Foundation 2.1i + SP2: How to instantiate LVDS I/O in Foundation Schematics
Xilinx Answer #7938 : 2.1i XC4000XL PAR - Guided par of 4000XL device does not work in 2.1i Service Pack 1 or 2.
Xilinx Answer #7946 : 2.1i COREGEN, VANTAGE, VHDL: Error: Configuration "cfg_beh" cannot be created because the library already has a configuration with the same name. (util/LBR/58)
Xilinx Answer #7947 : EXEMPLAR: How to instantiate and initialize Virtex Select BlockRAM?
Xilinx Answer #7948 : 2.1i 9500/xl Tsim- Timing model incorrect for negative edge triggered global clock signals
Xilinx Answer #7949 : FPGA Express 3.3: FPGA-buffermap-25 occurs when clock signal is connected to non-clock loads
Xilinx Answer #7950 : 2.1i Virtex PAR - par.exe exception:divide by zero (0xc0000094) Address: 0x0d36689a
Xilinx Answer #7953 : 2.1i Lab Install: Service Pack update of lab install fails with installer\jre\nt\bin\java.exe
Xilinx Answer #7956 : 2.1i FPGA Editor: How does one use the Manual Place option? Seems to be always grayed out.
Xilinx Answer #7963 : Virtex Configuration: Is it possible to abort readback of a device?
Xilinx Answer #7965 : 2.1i Map - Pack errors on floorplanned gates do not always report problem area.
Xilinx Answer #7967 : Hardware Debugger 2.1i: How to do Virtex Readback Verify with the Multilinx cable
Xilinx Answer #7973 : 2.1i COREGEN, MTI: "WARNING[1]:No default binding for component" messages when compiling VHDL designs containing Coregen modules
Xilinx Answer #7976 : Virtex Configuration: DriveDone polarity is incorrect in XAPP151
Xilinx Answer #7988 : 2.1i PAR - PAR fix improves results for all device families.
Xilinx Answer #7990 : LogiCORE PCI Virtex: Virtex-E Speed File based design updates
Xilinx Answer #7993 : 2.1i FPGA Editor : "Warning : FPGAEditor 140 - Nothing found to delete" message when attempting to delete a placed IOB
Xilinx Answer #7994 : 2.1i: VHDL simulation of XDW module COMP_LT_UBIN_x gives wrong results
Xilinx Answer #7995 : 2.1i 4000XL Map- ERROR:OldMap:256 - Clock buffer BUFG symbol "..." cannot be converted to a BUFGLS due to location constraints.
Xilinx Answer #7996 : 2.1i COREGEN: Virtex-E support
Xilinx Answer #8000 : PAR 2.1is2 - par report does not give the correct Vcco value for LVDS IO
Xilinx Answer #8005 : VirtexE CLKDLL: How to create 4X clock using VirtexE CLKDLLs
Xilinx Answer #8006 : VirtexE CLKDLL: What are the input clock frequency range for VirtexE CLKDLLs to be locked.
Xilinx Answer #8007 : Virtex CLKDLL: Why is it the output jitter spec on the data book is less than the cycle-to-cycle input jitter
Xilinx Answer #8008 : Synopsys FPGA Compiler, M2.1i PAR: ERROR:Parsers:3 - Unable to parse "+" in line 4.
Xilinx Answer #8014 : Foundation2.1is2 Functional Simulation: INIT_0X attribute for virtex Block RAM does not work in functional simulation
Xilinx Answer #8015 : 2.1i COREGEN, SYNOPSYS VSS: How do I compile the Coregen Modules for VSS simulation?
Xilinx Answer #8017 : Synopsys Compiler, NGDBuild: A port list construct was found in .... EDIF file, this is not supported. Try enabling bus expansion.
Xilinx Answer #8018 : WebPACK: Window95/98 environment variables incorrectly overwritten on installation
Xilinx Answer #8021 : 2.1i COREGEN (Japanese Version ONLY): "ERROR: Gui Field component_name not found"
Xilinx Answer #8022 : Virtex Configuration: Toggling /WRITE during serial configuration (DONE does not go high)
Xilinx Answer #8023 : 2.1i COREGEN: CoreLINX button in Coregen links you to the C_IP1 update instead of to the latest IP release
Xilinx Answer #8024 : LogiCORE PCI Virtex: Does the Xilinx Real-PCI Virtex solution support Synplify 5.2.2 release?
Xilinx Answer #8026 : F2.1i Schematic:$FILE attribute disappears when schematic editor is closed.
Xilinx Answer #8028 : 2.1i COREGEN: Is there a Virtex version of the Single Port and Dual Port RAM modules in Coregen?
Xilinx Answer #8030 : XPLA Logistics: CoolRunner packages TQFP, LQFP are equivalent to the Xilinx VQ and TQ packages respectively.
Xilinx Answer #8032 : 2.1i Virtex Map/PAR- Error:Place:871 - Carry chain placement conflicts with floor planned register LOCs.
Xilinx Answer #8045 : Where can I find documentation on metastability issues for Xilinx devices?
Xilinx Answer #8046 : 2.1i VirtexE Map - Map does not make use of the fastdll feedback path between DLLIOBs and Secondary DLLs.
Xilinx Answer #8047 : Logicore PCI: Can the user application access the BARs (base address registers) via the back end interface?
Xilinx Answer #8048 : FPGA Express 3.x: Can't see feslw30.dll in path on Windows NT
Xilinx Answer #8050 : 2.1i JTAG Programmer - Data string is larger than the specified svf bit length
Xilinx Answer #8055 : SYNPLIFY: How to LOC/RLOC logic in HDL (VHDL or Verilog)?
Xilinx Answer #8057 : Warning: Ngdhelpers 312: Logical block U## of type <Macro_name> is unexpanded. or ngdbuild 76
Xilinx Answer #8058 : 2.1i COREGEN, VERILOG-XL: "Error! `include file "XilinxCoreLib/xxxx.v not found"
Xilinx Answer #8062 : PROM XC18V00: Is the reset polarity user programmable?
Xilinx Answer #8065 : COREGEN: How to generate a VERILOG or VHDL post-NGDBUILD gate level simulation netlist from a standalone EDIF netlist
Xilinx Answer #8066 : MODELSIM VLOG (MTI): How to compile the XilinxCoreLib (COREGEN) Verilog library?
Xilinx Answer #8067 : FPGA Express: Can not create chip - Unknown error
Xilinx Answer #8068 : 2.1i COREGEN, 4K, Virtex: Dual Channel NCO outputs are identical in Verilog behavioral simulation
Xilinx Answer #8073 : 2.1i Virtex Map - ERROR:basmm:227 - LUT2 symbol "G_6919" (output signal=N_8071) has an equation..
Xilinx Answer #8074 : EXEMPLAR 1999.1x: How to force I/O standards onto ports
Xilinx Answer #8075 : Mentor: Check Design gives Error: Out of date reference; Version 1 of symbol "gnd", or of symbol "vcc"
Xilinx Answer #8076 : Mentor: pld_men2edif gives: Error: An instance in a model references part $LCA/spartanxl/vcc/part interface vcc... General 18
Xilinx Answer #8077 : 2.1i JTAG Programmer - Why is RUNTEST 6067 TCK in the SVF file?
Xilinx Answer #8079 : MODELSIM XE (MTI): How is the performance affected by the number of lines in the HDL source file?
Xilinx Answer #8082 : 2.1i FPGA Editor - FATAL_ERROR:Ncd:x4kcmclb.c:1158:1.1.2.2
Xilinx Answer #8086 : NGDBUILD, EXEMPLAR, SYNPLICITY: Error ngdhelpers 634: Port ".." is specified. There is no pad allocated to this signal
Xilinx Answer #8089 : HP Elite Install: Virtex (V50, V100, V150) pkg and spd files are not delivered
Xilinx Answer #8091 : 2.1i_sp2 Design Manager: Hang / Segmentation Fault on Solaris 2.7 (SunOS 5.7) from Service Pack 2 environment
Xilinx Answer #8092 : 2.1i Virtex Map - FATAL_ERROR:xvkpu:xvkpulocal.c:246:1.3
Xilinx Answer #8093 : 2.1i Virtex PAR - FATAL_ERROR:Utilities:basagconjgradient.c:202:1.1.4.2 - CG SOLVER: residual
Xilinx Answer #8094 : 2.1i VirtexE PAR - Placer continues even if LVDS IO comps have no locate constraints
Xilinx Answer #8095 : 2.1i 9500/XL Hitop: Designs that fit in 1.5x do not fit in 2.1i
Xilinx Answer #8096 : Cable - Voltage Interface Capabilities of the MultiLINX, Parallel cable III, and XChecker cables
Xilinx Answer #8097 : Cable - Support of software combinations, devices, readback, and other features
Xilinx Answer #8098 : Cable - MultiLINX Cable Drive strength capabilities and specifications
Xilinx Answer #8101 : 1800: Are IBIS models available for the 1800 series PROMs?
Xilinx Answer #8102 : XC9500XL JTAG Programmer - ISP Enable instruction different in SVF file and 2.1i JTAG Programmer
Xilinx Answer #8107 : Mentor: NGDBuild gives: ERROR:NgdHelpers:312 - logical block "I$1563/I$1/I$32" of type "vcc!1" is unexpanded (or "gnd!1")
Xilinx Answer #8108 : 2.1i JTAG Programmer - Error: JTAG - Unable to locate BSDL file 'c.bsd'
Xilinx Answer #8109 : 2.1i 9500/XL TAEngine : program abnormally terminated
Xilinx Answer #8110 : Virtex Configuration: Using LOUT writes for debugging purposes in Serial Modes
Xilinx Answer #8114 : Virtex V1000, V2000E BG560: Pin compatibility between V1000 and V2000E
Xilinx Answer #8117 : 2.1i Speed Files - There are several speed file changes available in Service Pack 3
Xilinx Answer #8118 : 2.1i Spartan-II Package Files - Some package files available with Service pack 3 are not correct.
Xilinx Answer #8123 : PROM XC18V00: How should I connect the CF# pin?
Xilinx Answer #8125 : 2.1i Install : The Key entered is not valid.
Xilinx Answer #8133 : 2.1i JTAG Programmer - ERROR:JTag - Error of type 'Unlocatable package file. Check XACT path and package name encountered while parsing BSDL package ...
Xilinx Answer #8137 : FPGA Express 3.3: Converting Constraints (.EXC) to ASCII or TCL and adding Constraints to the FE_SHELL
Xilinx Answer #8140 : XPLA Pro: Error: "No output bin/isp file generated, download aborted"
Xilinx Answer #8143 : 2.1i Virtex Map - FDRSE optimized to zero incorrectly.
Xilinx Answer #8144 : SYNPLIFY: How to instantiate CLKDLL in HDL? (VHDL/Verilog)
Xilinx Answer #8148 : 2.1i Virtex Map - Apparently legal MUXF5 pack is rejected.
Xilinx Answer #8149 : Virtex JTAG - XAPP139 has a misprint on shutdown sequence for AGHIGH command
Xilinx Answer #8150 : 2.1i Virtex PAR - Memory leak seen during timing analysis of V800 design.
Xilinx Answer #8151 : 2.1i COREGEN: Errors about components not being found when simulating myadder8_top.vhd example
Xilinx Answer #8153 : 2.1i COREGEN, C_IP3: Synchronous INIT control does not work when "Restrict Count" option is selected for Virtex Binary Counter
Xilinx Answer #8154 : 2.1i COREGEN: GUI for some Cores may hang when double-clicking the "Pins" or "Initial Contents" buttons
Xilinx Answer #8156 : Virtex: Are the internal Tristate outputs pullup, pulldown or high-Z?
Xilinx Answer #8158 : FPGA Configuration : [XC3000, XC4000, XC5200, Spartan] Data frame error information
Xilinx Answer #8162 : 2.1i Foundation Logic Simulator: How to use the "check" macro on busses?
Xilinx Answer #8165 : 2.1i Foundation: Spartan-II not available in Project Manager after install
Xilinx Answer #8171 : 2.1i COREGEN, LOGIBLOX: Where to find information on CORE Generator Virtex counterparts of 4K LogiBLOX modules
Xilinx Answer #8173 : XPLA Family: Which CoolRunner devices have ISP or Boundary Scan operations capability?
Xilinx Answer #8177 : 2.1i COREGEN, C_IP4: Known Issues in the C_IP4 IP Update
Xilinx Answer #8182 : PAR2.1isp3: Par hangs after the message "Starting Initial Timing Analysis"
Xilinx Answer #8183 : SYNPLIFY: How to infer ROM in HDL (VHDL/Verilog)?
Xilinx Answer #8187 : Virtex-E LVDS: How to use LVDS IOSTANDARD in Virtex-E
Xilinx Answer #8188 : 2.1i Install: Unexpected error occured - couldn't convert MS registry value to java
Xilinx Answer #8189 : 2.1isp3 Virtex Bitgen: Virtex bit file from bitgen with default options causes improper behavior on CLKDLL
Xilinx Answer #8191 : 1.5i/2.1i Ngdbuild: Error : NGDBUILD 303 - <pathname> could not be written to. Please make sure you have adequate disk space and have write privledges.
Xilinx Answer #8193 : Foundation 2.1i: Virtex-E: Cannot access XCV200E-PQ240 package in Project Manager
Xilinx Answer #8196 : FPGA Configuration: Startup sequence has not yet completed
Xilinx Answer #8197 : FPGA Configuration: Configuration data is incorrect
Xilinx Answer #8198 : FPGA Configuration: Configuration memory is not full (Express Mode 4000XLA/XV/SpartanXL)
Xilinx Answer #8201 : 2.1i COREGEN: ERROR: "File com\xilinx\ip\<class name>.class not found in library <library name>"
Xilinx Answer #8202 : Virtex-E FPGA Express 3.3: How to instantiate special Virtex-E I/O standards (LVDS, LVPECL)
Xilinx Answer #8207 : EXEMPLAR: How to instantiate LUT primitives in HDL for Virtex?
Xilinx Answer #8209 : JTAG BSDL: Missing pins in BSDL file for Virtex BG packages
Xilinx Answer #8212 : Foundation 2.1i Schematic Editor: "Line 3; Wrong number of fields; BUS"
Xilinx Answer #8213 : FPGA Configuration: Configuration has not begun
Xilinx Answer #8219 : Virtex: Pin AD26 of FG676 package should be in Bank 4 for Virtex.
Xilinx Answer #8224 : 2.1i JTAG Programmer - JTAG Programmer 2.1i does not support XC1800 SVF generation
Xilinx Answer #8225 : Is there a Utility which converts ABEL or AHDL designs to Verilog or VHDL format
Xilinx Answer #8232 : F2.1i Logiblox: Improper functional simulation of multiple Logiblox instances
Xilinx Answer #8233 : 2.1i COREGEN, C_IP2: Virtex Variable Parallel Multiplier model shows only a 1-cycle latency in Verilog behavioral simulation
Xilinx Answer #8238 : FPGA Configuration : LengthCount match has not been met
Xilinx Answer #8240 : Virtex Configuration: Device doesn't enter the startup sequence
Xilinx Answer #8241 : FPGA Configuration : DONE pin is being held low externally
Xilinx Answer #8243 : 2.1i Alliance Install : How can I set up a client to point to a networked installation?
Xilinx Answer #8244 : 2.1isp3 Virtex Bitgen: Virtex bit file from bitgen with default options causes improper behavior on CLKDLL
Xilinx Answer #8245 : 2.1i : 9500 : Hprep6 : Inverted global tristates do not tristate properly
Xilinx Answer #8246 : 2.1i Foundation ABEL: Combinatorial set assignment within a state machine works only in var=[x,x] format not var=^bxx format.
Xilinx Answer #8251 : 2.1i Virtex PAR - Application Error during Placement of V300 design
Xilinx Answer #8252 : 2.1i COREGEN, C_IP4, FFT: The Xilinx FFT cores do not support the Spartan-II architecture.
Xilinx Answer #8254 : FPGA Compiler, Design Compiler: How do I pass the IOSTANDARD constraint for Virtex designs?
Xilinx Answer #8255 : 2.1i JTAG Programmer - Boundary-scan chain test failed at bit position '3'
Xilinx Answer #8258 : 2.1i : 9500 : Hitop : WARNING: CPLDFitter- The property SLOW set on the instance "<inst>" conflicts with the previous setting FAST.
Xilinx Answer #8260 : F2.1i Docsan: applet d23/docsan/docsan could not be loaded
Xilinx Answer #8261 : 2.1i COREGEN, VIRTEX, FFT, C_IP4: "WARNING: Core vfft16 did not generate product VerilogSim."
Xilinx Answer #8262 : 2.1i 4KXLA Map - FATAL_ERROR:OldMap:x45maclb.c:204:1.1.2.2 - Unknown input pin Q
Xilinx Answer #8263 : Virtex CLKDLL VHDL simulation: DLL outputs are not toggling (No output) CLKIN is delayed
Xilinx Answer #8264 : 2.1i JTAG Programmer - 1802 PROM support added.
Xilinx Answer #8265 : JTAG BSDL - What is the format of the IDCODE for Xilinx devices?
Xilinx Answer #8271 : 2.1i COREGEN: Update Cores-> Custom appears to have all cores selected by default
Xilinx Answer #8288 : 2.1i COREGEN: How to access the CORE Generator User Guide Documentation
Xilinx Answer #8289 : Virtex Configuration: Device hasn't started configuration
Xilinx Answer #8291 : Prom File Formatter 2.1is3 (Solaris only) :Takes a long time to start up (hangs)
Xilinx Answer #8292 : JTAG - Using the TDO pin as a user output on XC4000 based devices (HDL example)
Xilinx Answer #8294 : 2.1i Virtex-E Speed Files - New speed files are available for Virtex-E.
Xilinx Answer #8295 : 2.1i SpartanXL Speed Files - MIN speed values are now available for SpartanXL
Xilinx Answer #8296 : 2.1i Spartan-II Package Files - The TQ144 Package has been added for Spartan-II
Xilinx Answer #8297 : 2.1i XV1000E PAR - A data file fix for XV1000E may improve placement results for some designs.
Xilinx Answer #8298 : 2.1i Virtex-E Packages - The XV600E FG900 and XV1000E FG1156 packages have bad banking information and missing N.C.
Xilinx Answer #8299 : 2.1i SP4 - 2.1i Service Pack 4 update
Xilinx Answer #8301 : Hardware Debugger: Can you download to an XESS demo-board using the Xilinx Parallel Cable
Xilinx Answer #8304 : 2.1i COREGEN, C_IP4, VIRTEX, FFT: "Generating the core will overwrite the following [xdsp_xxxx.edn] files" when generating more than one FFT
Xilinx Answer #8308 : 2.1i COREGEN, C_IP4: "Illegal value FALSE for variable write_mif" when regenerating Coregen RAM for Virtex
Xilinx Answer #8310 : EXEMPLAR 1999.1g, MAP 2.1i: GSR is connected to GND, ERROR:OldMap:928 - There is no signal on pin A0 of CY4 symbol (sourceless)
Xilinx Answer #8312 : 2.1i JTAG Programmer - Virtex-E BSDL files are available.
Xilinx Answer #8313 : 2.1i sp4 Trce/Timing analyzer : Trace gives different timing results than the Timing Analyzer
Xilinx Answer #8314 : 2.1i COREGEN, C_IP4: RAM-based SHIFT REGISTER behavioral model does not match backannotated simulation when CE = 'X'
Xilinx Answer #8315 : 2.1i COREGEN, C_IP4: "FATAL: RPM arrangement for a1/RAM_0/BIT_1 cannot be placed in RPM arrangement for a1/RAM_0 due to resource contention." for RAM-Based Shift Register
Xilinx Answer #8316 : 2.1i COREGEN: "ERROR: ... Can not find initial Contents file to read: <module_name>.mif" when READ MIF is selected
Xilinx Answer #8317 : XPLA Architecture: How to calculate thermal resistance for the CoolRunner packages?
Xilinx Answer #8320 : 2.1is3, HP-UX - ngdbuild core dump/crash when reading ngo file during translate (abnormally terminated)
Xilinx Answer #8321 : 2.1isp3 Virtex Bitgen: Virtex bit file from bitgen with default options causes improper behavior on CLKDLL
Xilinx Answer #8322 : 2.1i Spartan-XL PAR - FATAL_ERROR:Route:basrtsanity.c:234:1.1.2.2 - Process will terminate.
Xilinx Answer #8324 : FPGA Compiler 2, version 3.3.1: Bidirectional pads may cause multiple driver error in Translate (NgdHelpers:336)
Xilinx Answer #8325 : Foundation Base Package: Synopsys Constraints editor license file not found, will load without it!
Xilinx Answer #8327 : 2.1i Timing Analyzer : Memory leak when selecting custom sources
Xilinx Answer #8328 : Coolrunner/XPLA : How do I use the TDO as an output pin?
Xilinx Answer #8336 : INTERNAL_ERROR:NgdBuild:basnbsrch.c:327:1.1.2.6 "entity or component" is missing the TYPE property.
Xilinx Answer #8341 : Virtex-E datasheet: What are the pins for LVDS global clocks?
Xilinx Answer #8342 : FPGA Configuration: Why doesn't the parallel cable have an INIT pin?
Xilinx Answer #8346 : 2.1i SP4 NGDBuild - Program Abnormally Terminated - Dr. Watson on NT4sp5
Xilinx Answer #8348 : 2.1i SP4 Install : HP - warnings during installation of SP4 that 'File does not exist'
Xilinx Answer #8350 : JTAG BSDL - General Description of BSDL and how to read a BSDL file
Xilinx Answer #8354 : Virtex: Virtex has the potential race condition that can occur during the STARTUP
Xilinx Answer #8368 : 2.1i Virtex-E Map: XCV600E-BG32 Map report lists an incorrect number of bonded IOBs.
Xilinx Answer #8372 : 2.1i COREGEN, C_IP4: Virtex Asynchronous FIFO Verilog simulation "ERROR: Module or primitive (ASYNC_FIFO_V1_0) not defined"
Xilinx Answer #8374 : 2.1i COREGEN, VERILOG: 'Error! Too many module instance parameter assignments [in] "XilinxCoreLib/async_fifo_v1_0.v", 839: C_GATE_BIT_V1_0'
Xilinx Answer #8375 : ABEL: Signal properties ignored: Warning 18818:Could not find signal or instance <signal_name> associated with property <property_name>.
Xilinx Answer #8379 : 2.1i, V1.5x COREGEN, VIRTEX: Availability of PDA FIR and SDA FIR filter modules for Virtex
Xilinx Answer #8380 : WEBFITTER, LOGIBLOX: WebFitter error about "invalid filename extensions" on .NGC files produced by LogiBLOX
Xilinx Answer #8381 : 2.1i COREGEN, SOLARIS, HP: Coregen appears to scan newly installed cores every time it is started up
Xilinx Answer #8382 : 2.1i COREGEN, C_IP4: C_IP4 contains FAE beta version of Asynchronous FIFO datasheet
Xilinx Answer #8383 : Virtex: Can Virtex Inputs be driven by input voltages lower that -500mV?
Xilinx Answer #8390 : Virtex: How does signal grouping affect the number of SSO a device can support before ground bounce becomes a problem?
Xilinx Answer #8398 : Foundation 2.1i: Timing simulation of Virtex DLL fails when input frequency is higher than 100MHz
Xilinx Answer #8406 : 2.1i Virtex Constraints Editor: Drive strength constraints is ignored. (FPGA Express only)
Xilinx Answer #8411 : Proms XC18V00: What are the program options for the 1800 in the JTAG Programmer?
Xilinx Answer #8415 : Foundation State Editor/Abel: Syntax Error when //diagramm actions are used
Xilinx Answer #8420 : SYNPLIFY: How to change BUFG limit from 4 to 8 for Spartan-XL design? (BUFGLS)
Xilinx Answer #8421 : 2.1i Spartan-XL PAR - Router gets poor results on XCS30XL and XCS40XL designs compared to 1.5i.
Xilinx Answer #8427 : JTAG Programmer - '<design_name>(Device1)': Programming terminated due to errors.
Xilinx Answer #8428 : JTAG - Is the JTAG functionality available if GTS is asserted in XC4000 designs?
Xilinx Answer #8432 : Virtex-E: Can we tie Vcco to 2.5 V for LVDS, and have LVTTL inputs?
Xilinx Answer #8434 : 2.1i JTAG Programmer - ERROR:JTag - Unable to locate BSDL file 'xcv1000.bsd'.
Xilinx Answer #8443 : CPLD 7200: Are there 7200 devices left? Are there any compatible devices?
Xilinx Answer #8446 : 2.1i COREGEN: Format of the COE file for the C_IP4 Virtex DA FIR Filter core
Xilinx Answer #8454 : XPLA3: Are the XPLA3 devices footprint compatible with other CoolRunner XPLA families?
Xilinx Answer #8457 : XPLA3: What are the primary new features of the XPLA3 devices?
Xilinx Answer #8483 : Virtex: VHDL code for select link application
Xilinx Answer #8486 : 2.1i Virtex PAR - Exception integer divide by zero par.exe caused exception 0xc000094 in module C;\xilinx\virtex\bin\nt\libplvirt_place.dll at 001B : 09c6B88A"
Xilinx Answer #8490 : 2.1i Virtex Map - Inversion between MUXCY and Flop is dropped/
Xilinx Answer #8492 : 2.1i Virtex Map - FATAL_ERROR:baspu:baspupacker.c:313:1.40 - read of floorplanner file ....
Xilinx Answer #8497 : 2.1i COREGEN: Not all EDIF files may be copied over when generating cores made up of multiple EDIF files
Xilinx Answer #8508 : Virtex: How many DLLs can be cascaded together?
Xilinx Answer #8509 : CPLD XC9500/XL/XV: GSR is not used when using registers that are synchronously reset
Xilinx Answer #8514 : Virtex: Will Vref pin draw any power if the IO standard is CTT
Xilinx Answer #8518 : Parallel Cable: How is it possible to power the parallel cable with 3.3V and 5V without an adaptor?
Xilinx Answer #8519 : 2.1i 9500/XL Hitop: ERROR:CPLDFitter - NGD2NDS failed. The NDS network is not created due to errors
Xilinx Answer #8520 : Virtex Configuration: What is an ABORT? How do I cause one?
Xilinx Answer #8525 : 2.1i SP5 - 2.1i Service Pack 5 update
Xilinx Answer #8531 : ModelSim XE (MXE) : starting the vsim GUI I get a window titled Error in Startup Script
Xilinx Answer #8532 : 2.1i, V1.5 COREGEN: How to run CORE Generator in verbose mode
Xilinx Answer #8534 : SP5 Install, SP5, C_IP4: "Setup failed while processing the FileCopier.SrvcPackReplacetask. "
Xilinx Answer #8545 : 2.1i Spartan-XL PAR - Placer fails to place TDO comp when Exact Guide is used.
Xilinx Answer #8552 : Modelsim (MTI) VHDL Coregen: Using a Generate Statment I can not get my simulation to run (Configuration)
Xilinx Answer #8556 : Virtex Configuration: INIT goes low
Xilinx Answer #8561 : WebPACK: What is WebPACK?
Xilinx Answer #8572 : 2.1i Virtex-E Map - Map outputs incorrect message when processing invalid Virtex LOC constraints.
Xilinx Answer #8576 : 2.1i COREGEN: 64 point FFT datasheet erroneously refers to YK_R and YK_I ports in the pinout table
Xilinx Answer #8599 : 2.1WP5.1 (WebPACK): Where are the original and 3.3V enhanced part selections for the XPLA Fitter and ISP Programmer? (XCR3032, XCR3064, XCR3128, XCR3064A, XCR3128A)
Xilinx Answer #8601 : 2.1i 9500 Family Hitop: hi811 - Cannot assign Fastclock Pin D2_PAD to Pin 40 (FB1_1).